KR20180123429A - 기판 상에 실리콘 질화막을 선택적으로 형성하는 방법 및 관련 반도체 소자 구조체 - Google Patents

기판 상에 실리콘 질화막을 선택적으로 형성하는 방법 및 관련 반도체 소자 구조체 Download PDF

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KR20180123429A
KR20180123429A KR1020180037384A KR20180037384A KR20180123429A KR 20180123429 A KR20180123429 A KR 20180123429A KR 1020180037384 A KR1020180037384 A KR 1020180037384A KR 20180037384 A KR20180037384 A KR 20180037384A KR 20180123429 A KR20180123429 A KR 20180123429A
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silicon nitride
substrate
nitride film
silicon
deposition
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제이콥 허프만 우드러프
베드 샤르마
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에이에스엠 아이피 홀딩 비.브이.
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Abstract

제1 금속 표면 및 제2 유전체 표면을 포함하는 기판 상에 실리콘 질화막을 주기적인 증착 공정에 의해 선택적으로 형성하기 위한 방법이 개시된다. 상기 방법은 기판을 실리콘 할로겐화물 소스를 포함하는 제1 반응물과 접촉시키는 단계, 및 상기 기판을 질소 소스를 포함하는 제2 반응물과 접촉시키는 단계를 포함할 수 있고, 제1 금속 표면에 대한 인큐베이션 기간은 제2 유전체 표면에 대한 인큐베이션 기간보다 짧다. 선택적 실리콘 질화막을 포함하는 반도체 소자 구조체가 또한 개시된다.

Description

기판 상에 실리콘 질화막을 선택적으로 형성하는 방법 및 관련 반도체 소자 구조체{METHODS FOR SELECTIVELY FORMING A SILICON NITRIDE FILM ON A SUBSTRATE AND RELATED SEMICONDUCTOR DEVICE STRUCTURES}
본 개시는 일반적으로 기판 상에 실리콘 질화막을 선택적으로 형성하는 방법 및 선택적 실리콘 질화막을 포함하는 관련 반도체 소자 구조체에 관한 것이다.
반도체 소자 기술 분야에서, 실리콘 질화막은 반도체 집적 회로의 제조 과정 중 사용될 수 있다. 예를 들면, 실리콘 질화막은, 예를 들면, 반도체 소자 구조체, 예컨대, 트랜지스터, 메모리 셀, 논리 소자, 메모리 어레이 등의 제조 과정 중 절연 재료로서 사용될 수 있다.
고품질의 실리콘 질화막을 위한 저온 증착 공정용 반도체 소자 기술이 해당 분야에서 요구되며; 이러한 저온 증착 공정은 또한 막 두께, 두께 균일성 및 컨포멀리티(conformality)의 정밀한 제어를 제공해야 한다.
통상의 실리콘 질화막 증착 공정은 디클로로실란(DCS) 및 암모니아(NH3)와 같은 전구체들 사이에서의 반응을 형성하기 위해 고온 증착, 즉 600℃ 내지 800℃ 부근의 고온 증착을 요구한다. 최근 기술의 소자 구조체는 이러한 높은 열처리량(thermal budget)을 견뎌낼 수 없으며, 이는 또한 소자 성능이 열화되는 결과를 낳을 수 있고, 소자 집적에 문제를 일으킬 수 있다.
고온 증착 공정에 대한 대안적 해결책은 전구체를 활성화시키기 위해 플라즈마를 사용하는 것일 수 있으며, 이는 결과적으로 실리콘 질화막을 위한 저온 반응 및 감소된 증착 온도를 허용할 수 있다. 그러나, 플라즈마 기반 증착 공정은 증착 성능, 즉, 높은 종횡비의 구조체를 달성할 수 있는 스텝 커버리지(step coverage) 및 막 품질의 균일성에서 제한될 수 있고, 플라즈마 기반 증착 공정은 하부의 소자 구조체를 손상시킬 수 있다.
일부 응용에서, 기판의 특정 영역들에만 실리콘 질화막을 형성하는 것이 바람직할 수 있다. 전형적으로, 이러한 결과는 연속적인 막을 증착하고 후속의 리소그라피 및 식각 단계를 이용하여 이 막을 패터닝함으로써 달성된다. 이러한 처리는 시간을 소비하고 고비용이 소요되며, 많은 응용을 위해 필요한 정밀도를 제공하지 않는다. 가능한 해법은 선택적 증착 공정의 사용이고, 이에 의해 재료는 원하는 영역에만 증착되어 후속 패터닝 단계에 대한 필요성을 없앤다.
따라서, 실리콘 질화막 및 이러한 선택적 실리콘 질화막을 포함하는 반도체 소자 구조체를 위한 저온 증착 공정이 반도체 소자 성능을 향상시키기 위해 필요할 수 있다.
본 개시의 적어도 일 구현예에 따르면, 제1 금속 표면 및 제2 유전체 표면을 포함하는 기판 상에 실리콘 질화막을 주기적 증착 공정에 의해 선택적으로 증착하는 방법을 제공한다. 상기 방법은 실리콘 할로겐화물 소스를 포함하는 제1 반응물과 기판을 접촉시키는 단계, 및 질소 소스를 포함하는 제2 반응물과 상기 기판을 접촉시키는 단계를 포함하고, 제1 금속 표면을 위한 인큐베이션 지연은 제2 유전체 표면을 위한 인큐베이션 지연보다 작다.
본 명세서는 본 발명의 구현예로 간주되는 것을 특별히 지적하고 명백하게 주장하는 청구범위로 결론을 내지만, 본 개시의 구현예들의 장점들은 첨부한 도면들과 관련하여 읽을 때 본 개시의 구현예들의 특정 예의 설명으로부터 더욱 쉽게 확인될 수 있고, 도면들 중:
도 1은 본 개시의 구현예들에 기술된 바와 같이 선택적 실리콘 질화막을 기판 상에 형성하는 방법을 위한 공정 흐름을 도시하고;
도 2는 본 개시의 구현예들에 따라 형성된 실리콘 질화막들에 대한 증착 두께 대 주기적인 증착 사이클의 수를 도시하고;
도 3은 본 개시의 구현예들에 기술된 바와 같이 선택적 실리콘 질화막을 기판 상에 형성하는 방법을 위한 또 다른 공정을 도시하고;
도 4는 본 개시의 구현예들을 수행하도록 구성된 예시적 반응 시스템을 도시하고;
도 5는 본 개시의 구현예들에 의해 형성된 실리콘 질화막을 포함하는 예시적 반도체 소자 구조체를 예시한다.
도면의 구성 요소들은 간략하게 그리고 명료하게 도시되어 있으며, 반드시 축적대로 그려지지 않았음을 이해할 것이다. 예를 들어, 본 개시에서 도시된 구현예의 이해를 돕기 위해 도면 중 일부 구성 요소의 치수는 다른 구성 요소에 비해 과장될 수 있다.
특정 구현예 및 실시예가 아래에 개시되었지만, 당업자는 본 발명이, 구체적으로 개시된 구현예 및/또는 본 발명의 용도 그리고 이들의 명백한 변형 및 등가물로 확장된다는 것을 이해할 것이다. 따라서, 개시된 발명의 범주는 후술되는 구체적인 개시된 구현예에 의해 제한되지 않도록 의도된다.
본원에서 사용되는 바와 같이, 용어 "금속 표면"은 금속 이온들을 포함하는 표면을 지칭할 수 있고, 이들에 제한되지는 않지만, 금속, 금속 합금, 금속 염, 금속 산화물, 금속 실리사이드, 금속 붕소화물, 반금속 및 금속 질화물을 더 포함할 수 있다.
본원에서 사용되는 바와 같이, 용어 "주기적 증착(cyclic deposition)"은 반응 챔버 내로 전구체(반응물)를 순차적으로 도입시켜 기판 상에 층을 증착하는 것을 지칭할 수 있으며 원자층 증착 및 주기적인 화학 기상 증착과 같은 공정 기술을 포함한다.
본원에서 사용되는 바와 같이, 용어 "인큐베이션 기간(incubation period)"은 구분 가능한 어떠한 증착도 관찰되지 않는 주기적 증착의 초기 단계들에서 주기적인 증착 사이클의 수를 지칭할 수 있다.
본원에서 사용되는 바와 같이, 용어 "원자층 증착"(ALD)은 증착 사이클, 바람직하게는, 복수의 연속 증착 사이클이 공정 챔버에서 수행되는 기상 증착 공정을 지칭할 수 있다. 일반적으로, 각각의 사이클 동안, 전구체는 증착 표면(예들 들면, 기판 표면, 또는 이전 ALD 사이클로부터의 물질과 같은 이전에 증착된 하부 표면)에 화학 흡착되고, 추가적인 전구체와 쉽게 반응하지 않는(즉, 자기 제한적 반응) 단층 또는 서브 단층을 형성한다. 따라서 필요하다면, 증착 표면에서 화학 흡착된 전구체를 원하는 물질로 전환시키는 용도로, 반응물(예들 들어, 다른 전구체 또는 반응 가스)이 후속해서 공정 챔버로 유입될 수 있다. 일반적으로, 이러한 반응물은 전구체와 더 반응할 수 있다. 또한, 각각의 사이클 동안 공정 챔버로부터 과량의 전구체를 제거하고/제거하거나, 화학 흡착된 전구체의 변환 후 공정 챔버로부터 과량의 반응물 및/또는 반응 부산물을 제거하기 위해 퍼징(purging) 단계들이 사용될 수도 있다. 추가로, 본원에 사용된 용어 "원자층 증착"은 "화학 기상 원자층 증착", "원자층 에피택시(atomic layer epitaxy)"(ALE), 분자 빔 에피택시(molecular beam epitaxy)(MBE), 가스 공급원 MBE, 또는 유기금속 MBE, 및 전구체 조성물(들), 반응 가스, 및 퍼지(예를 들면, 불활성 캐리어) 가스의 교번 펄스(alternating pulses)로 수행되는 경우의 화학적 빔 에피택시와 같은 관련 용어들에 의해 지정된 공정을 포함하는 것을 또한 의미한다.
본원에서 사용되는 바와 같이, 용어 "주기적인 화학 기상 증착"은 원하는 증착을 생성시키기 위해 기판 상에서 반응 및/또는 분해되는 두 개 이상의 휘발성 전구체에 기판이 순차적으로 노출되는 임의의 공정을 지칭할 수 있다.
본원에서 사용되는 바와 같이, 용어 "기판"은, 사용될 수 있는, 또는 그 위에 소자, 회로, 또는 막이 형성될 수 있는, 임의의 하부 재료 또는 재료들을 지칭할 수 있다. 기판은 웨이퍼, 예컨대, 실리콘 웨이퍼, 글래스 웨이퍼, 또는 다른 종류의 기판을 포함할 수 있다. 기판은 완전히 또는 부분적으로 제조된 반도체 소자 구조체들도 포함할 수 있고, 이 구조체들은 금속 표면들 및 유전체 표면들을 포함한다.
본 개시에 수 많은 재료들 및 이들의 화학식이 제공되며, 이러한 재료들 및 화학식들은 제공된 재료 또는 재료 표면의 화학양론을 제한하는 것으로 해석되어서는 안된다.
본 개시의 구현예는 기판 상에 실리콘 질화막을 선택적으로 형성하는 방법 및 특히 감소된 증착 온도에서 기판 상에 고품질의 선택적 실리콘 질화막을 형성하는 방법을 포함할 수 있다. 본 개시의 비제한적인 예시적 구현예로서, 기판 상에 선택적 실리콘 질화막을 형성하는 방법은 원자층 증착 공정 또는 주기적인 화학 기상 증착 공정을 포함할 수 있다. 특별한 구현예에서, 기판은 제1 금속 표면 및 제2 유전체 표면을 포함할 수 있고, 선택적 실리콘 질화물을 형성하는 방법들은 제2 유전체 표면 상에서의 증착에 비해 제1 금속 표면 상에서의 증착을 선호할 수 있다.
본 개시의 방법은, 제1 금속 표면 및 제2 유전체 표면을 포함하는 기판 상에 실리콘 질화막을 선택적으로 형성하는 방법(100)에 대한 비제한적인 예시적 구현예를 도시하는 도 1을 참조하여 이해될 수 있다. 예를 들면, 도 1은 주기적인 증착 공정에 의해 기판 상에 실리콘 질화막을 선택적으로 형성하는 방법(100)을 도시한다. 보다 상세하게, 선택적 실리콘 질화물을 형성하기 위한 주기적인 증착 공정은 원자층 증착 공정을 포함하거나, 대안적으로 주기적인 화학 기상 증착 공정을 포함할 수 있다. 선택적 증착 공정의 비제한적이고 예시적인 구현예는 ALD를 포함할 수 있으며, 여기서 ALD는 일반적으로 자기 제한적 반응에 기반하고, 이에 의해 반응물들의 순차적이고 교호적인 펄스가 증착 사이클당 약 하나의 원자(또는 분자) 단층을 증착하기 위해 사용된다. 증착 조건 및 전구체는 통상적으로 자기 포화 반응을 제공하도록 선택되어, 하나의 반응물의 흡착된 층이 동일한 반응물의 가스상 반응물과 비반응성인 표면 말단부를 남긴다. 후속하여, 기판은 이전의 말단부와 반응하는 상이한 반응물과 접촉되어, 연속되는 증착을 가능하게 한다. 따라서, 교번 펄스의 각각의 사이클은 통상적으로 원하는 재료의 대략 하나의 단층만을 남긴다. 그러나, 상술한 바와 같이, 당업자는 하나 이상의 ALD 사이클에서, 예를 들면 공정의 교번 특성에도 불구하고 몇몇 기상 반응이 발생하는 경우, 하나 이상의 재료의 단층이 증착될 수 있음을 인식할 것이다.
선택적 실리콘 질화막을 증착하는 ALD형 공정에서, 하나의 ALD 사이클은, 도 1의 공정 블록(104)에 도시된 바와 같이 기판을 제1 반응물에 노출시키는 단계, 도 1의 공정 블록(106)에 도시된 바와 같이 임의의 미반응된 제1 반응물 및 반응 부산물을 반응 공간으로부터 제거하고 기판을 제2 반응물에 노출시키는 단계, 및 이어서 제2 제거 단계를 포함할 수 있다. 제1 반응물은 실리콘 할로겐화물 소스를 포함할 수 있고, 제2 반응물은 질소 소스를 포함할 수 있다.
반응물 사이의 가스상 반응을 방지하고 자기 포화적 표면 반응을 가능하게 하도록, 전구체는 아르곤(Ar) 또는 질소(N2)와 같은 불활성 가스에 의해 분리될 수 있다. 그러나, 일부 구현예에서, 기판은 제1 기상 반응물 및 제2 기상 반응물과 개별적으로 접촉되도록 이동될 수 있다. 반응은 자기 포화적이므로, 기판의 엄격한 온도 제어 및 전구체의 정밀한 투여량 제어가 일반적으로 요구되지 않는다. 그러나, 기판 온도는 들어오는 가스종이 단층으로 응축되지 않게 하거나, 다수의 단층들이 표면 상에서 분해되지 않게 하는 것이 바람직하다. 과잉 화학 물질 및 반응 부산물이 존재하면, 이들은 기판이 다음 반응 화학 물질과 접촉하기 전에, 예를 들어, 반응 공간을 퍼징하거나 기판을 이동함으로써 기판 표면으로부터 제거된다. 원하지 않는 가스 분자들은 불활성 퍼지 가스의 도움으로 반응 공간으로부터 효과적으로 방출될 수 있다. 진공 펌프는 퍼징을 돕는 데 사용될 수 있다.
선택적 실리콘 질화막을 증착하기 위해 사용될 수 있는 반응기가 증착을 위해 사용될 수 있다. 이러한 반응기는 전구체들을 제공하기 위한 적절한 장비 및 수단을 구비하는 CVD 반응기뿐만 아니라 ALD 반응기를 포함한다. 일부 구현예에 따르면, 샤워헤드 반응기가 사용될 수 있다.
사용될 수 있는 적합한 반응기의 예는 상업적으로 입수 가능한 단일 기판 (또는 단일 웨이퍼) 증착 설비, 예를 들면, 미국 애리조나주 피닉스 소재의 ASM America, Inc. 및 네덜란드 알메레 소재의 ASM Europe B.V로부터 입수 가능한 Pulsar® 반응기(예를 들면 Pulsar® 2000 및 Pulsar® 3000 및 Pulsar® XP ALD), 및 EmerALD® XP 및 EmerALD® 반응기를 포함한다. 상업적으로 이용 가능한 다른 반응기는 Eagle® XP 및 XP8의 상표명을 가진 ASM Japan K.K(일본, 동경)사의 제품들을 포함한다. 일부 구현예에서, 반응기는, 기판이 가공 과정에서 이동 또는 회전하는 공간 ALD 반응기이다.
일부 구현예에서, 배치식(batch) 반응기가 사용될 수 있다. 적합한 배치식 반응기로, A400 및 A412 PLUS라는 상표명으로 ASM Europe B.V(네덜란드, 알메르)사로부터 상업적으로 입수 가능한 Advance® 400 시리즈 반응기가 포함되나, 이에 한정되지 않는다. 일부 구현예에서, 공정 과정 중 보트(boat)가 회전하는 수직 배치식 반응기, 예컨대 A412이 사용된다. 이처럼, 일부 구현예에서, 웨이퍼는 처리 동안 회전한다. 다른 구현예에서, 배치식 반응기는 10개 이하의 웨이퍼, 8개 이하의 웨이퍼, 6개 이하의 웨이퍼, 4개 이하의 웨이퍼, 또는 2개의 웨이퍼를 수용하도록 구성된 소형 배치식 반응기를 포함한다. 배치식 반응기가 사용되는 일부 구현예에서, 웨이퍼 대 웨이퍼의 균일도는 3%(1 시그마) 미만, 2% 미만, 1% 미만, 또는 심지어 0.5% 미만이다.
본원에서 설명되는 증착 공정은 클러스터 도구에 연결된 반응기 또는 반응 공간에서 선택적으로 수행될 수 있다. 클러스터 도구에서, 각각의 반응 챔버는 한 유형의 공정에 전용되기 때문에, 각각의 모듈 내 반응 쳄버의 온도는 일정하게 유지될 수 있으며, 이로부터 기판이 각각 실행되기 전에 공정 온도로 가열되는 반응기에 비해 처리량이 향상된다. 추가적으로 클러스터 도구에서는, 기판들 사이의 원하는 공정 압력 레벨까지 반응 공간을 펌핑하는 시간이 줄어들 수 있다.
독립형 반응기는 로드-록(load-lock)이 장착될 수 있다. 이러한 경우, 각 실행 사이에 반응 공간을 냉각할 필요가 없다. 일부 구현예에서, 선택적 실리콘 질화물 박막을 증착하기 위한 증착 공정은 복수의 ALD 사이클을 포함할 수 있다.
일부 구현예에서, 주기적인 증착 공정은 기판 상에 선택적 실리콘 질화막을 형성하기 위해 사용되고, 선택적 증착 공정은 ALD형 공정일 수 있다. 일부 구현예에서, 주기적인 증착은 하이브리드 ALD/CVD 또는 주기적인 CVD 공정일 수 있다. 예를 들면, 일부 구현예에서, ALD 공정의 증착 속도는 CVD 공정에 비해 낮을 수 있다. 증착 속도를 증가시키는 하나의 접근법은 ALD 공정에서 통상적으로 사용되는 것보다 높은 기판 온도에서 작동시키는 것이며, 이는 결국 화학 기상 증착 공정이 될 수 있지만, 전구체의 순차적 도입의 장점을 여전히 취하는 것일 수 있고, 이러한 공정은 주기적인 CVD라고 지칭될 수 있다.
일부 구현예에 따르면, ALD 공정은 집적 회로 대상물과 같은 기판 상에 선택적 실리콘 질화막을 형성하는 데 사용된다. 본 개시의 일부 구현예에서, 각각의 ALD 사이클은 구별되는 두 개의 증착 단계 또는 상태를 포함한다.
주기적인 증착 공정의 제1 단계("실리콘 단계")에서, 증착이 요구되는 기판 표면은 기판 표면 상에 화학 흡착되는 실리콘 전구체를 포함하는 제1 기상 반응물과 접촉되어(도 1의 공정 블록(104)), 기판 표면 상에 반응물 화학종의 대략 하나의 단층만이 기판 표면 상에 형성된다. 일부 구현예에서, 각각의 접촉 단계는 후속 공정 단계로 진행되기 전에, 즉 후속 접촉 단계 또는 제거/퍼징 단계 전에, 1회 이상 반복될 수 있다고 이해해야 한다.
일부 구현예에서, "실리콘 화합물"로 본원에서 또한 지칭되는 실리콘 전구체는 실리콘 할로겐화물 소스를 포함할 수 있다. 일부 구현예에서, 제1 반응물은 실리콘 할로겐화물 소스를 포함할 수 있고, 실리콘 테트라이오다이드(SiI4), 실리콘 테트라브로마이드(SiBr4), 실리콘 테트라클로라이드(SiCl4), 헥사클로로디실란(Si2Cl6), 헥사이오도디실란 (Si2I6), 옥토이오도트리실란(Si3I8) 중 적어도 하나를 더 포함할 수 있다. 실리콘 할로겐화물 소스가 실리콘 테트라이오다이드(SiI4)를 포함하는 구현예에서, 실리콘 테트라이오다이드 소스는 반응 챔버로의 전달을 위한 충분한 증기압이 제공되도록 예열될 수 있는데, 예를 들면, 일부 구현예에서 실리콘 테트라이오다이드 전구체 소스는 약 90℃ 내지 약 125℃의 온도까지 예열될 수 있고, 일부 구현예에서 실리콘 테트라이오다이드는 약 100℃의 온도까지 예열될 수 있다.
일부 구현예에서, 기판을 실리콘 할로겐화물 소스에 노출시키는 것은 실리콘 전구체(예를 들어, 실리콘 테트라이오다이드(SiI4))를 약 0.5초 내지 약 30초, 약 0.5초 내지 약 10.0초, 약 0.5초 내지 약 5.0초의 시간 동안 기판 위로 펄싱(pulsing)하는 것을 포함할 수 있다. 또한, 실리콘 할로겐화물 소스를 기판 위로 펄싱하는 동안, 실리콘 할로겐화물 소스의 유량은 2000 sccm 미만, 또는 1000 sccm 미만, 또는 500 sccm 미만, 또는 250 sccm 미만, 또는 심지어 100 sccm 미만일 수 있다.
과량의 실리콘 할로겐화물 소스 및 반응 부산물은(존재하는 경우), 예를 들면, 불활성 가스로 퍼징함으로써 기판 표면으로부터 제거될 수 있다. 예를 들면, 본 개시의 일부 구현예에서, 방법은 기판 표면이 약 5.0초 미만의 시간 동안 퍼징되는 퍼지 사이클을 포함할 수 있다. 과량의 실리콘 할로겐화물 소스 및 임의의 반응 부산물은 펌핑 시스템에 의해 생성된 진공의 도움으로 제거될 수 있다.
주기적인 선택적 증착의 제2 단계("질소 단계")에서, 기판은 질소 소스를 포함하는 제2 기상 반응물과 접촉한다(도 1의 공정 블록(106)). 본 개시의 일부 구현예에서, 방법은 암모니아(NH3), 하이드라진(N2H4), 또는 알킬-하이드라진 중 적어도 하나를 포함하도록 질소 소스를 선택하는 것을 더 포함할 수 있으며, 여기서 이러한 알킬-하이드라진은 알킬 기능기를 포함하고 추가적인 기능기를 포함할 수 있는 하이드라진 유도체를 지칭할 수 있고, 알킬-하이드라진의 비제한적인 예시적 구현예는 터트부틸하이드라진(C4H9N2H3), 메틸하이드라진(CH3NHNH2), 또는 디메틸하이드라진((CH3)2N2H2) 중 적어도 하나를 포함할 수 있다.
일부 구현예에서, 기판을 질소 소스에 노출시키는 것은 질소 소스(예를 들어, 암모니아(NH3))를 약 0.5초 내지 약 30.0초, 약 0.5초 내지 약 10초, 또는 약 0.5초 내지 약 5초의 시간 동안 기판 위로 펄싱하는 것을 포함할 수 있다. 질소 소스를 기판 위로 펄싱하는 동안, 질소 소스의 유량은 4000 sccm 미만, 또는 2000 sccm 미만, 또는 1000 sccm 미만, 또는 500 sccm 미만, 또는 심지어 250 sccm 미만일 수 있다.
질소 소스를 포함하는 제2 기상 반응물은 기판 표면에 남아 있는 실리콘 함유 분자와 반응할 수 있다. 일부 구현예에서, 제2 단계의 질소 소스는 기판 표면에 남아 있는 실리콘 함유 분자들과 반응하여 기판의 선택 부분들 상에 실리콘 질화막을 증착할 수 있다.
과량의 제2 소스 화학 물질 및 반응 부산물은, 존재하는 경우, 가스 펄스 및/또는 펌핑 시스템에 의해 생성된 진공을 퍼징함으로써 기판 표면으로부터 제거될 수 있다. 퍼지 가스는 제한 없이 임의의 불활성 가스, 예를 들어 아르곤(Ar), 질소(N2), 또는 헬륨(He)인 것이 바람직하다. 퍼지(즉, 퍼징 가스 펄스) 또는 다른 반응물을 제거하는 단계가 개입되는 경우, 하나의 단계는 다른 단계를 곧바로 뒤따르는 것으로 일반적으로 간주된다.
도 1의 방법(100)에 도시된 바와 같이, 선택적 증착 공정(102)은 기판과 제1 반응물을 접촉시키고(104), 후속하여 기판을 제2 반응물에 접촉시키는(106) 단계를 포함할 수 있으나, 본 개시의 구현예에서는 접촉 순서가 역전될 수 있어서, 기판이 제2 반응물에 먼저 접촉되고(106), 후속하여 기판이 제1 반응물과 접촉될(104) 수 있음을 이해해야 한다. 또한, 기판과 제2 반응물을 접촉시키기 전에 기판이 제1 반응물과 여러 번 접촉될 수 있으며, 그 반대의 경우도 가능하다는 것을 이해해야 한다.
본 개시의 구현예들은 선택적 증착 공정(102) 동안 기판을 가열하는 단계를 더 포함할 수 있다. 일부 구현예들에서, 방법들은 기판을 약 200℃ 내지 약 350℃의 온도로 가열하는 단계를 포함할 수 있다. 일부 구현예들에서, 방법들은 기판을 약 250℃ 미만의 온도, 또는 약 225℃ 미만의 온도, 또는 심지어 약 200℃ 미만의 온도까지 가열하는 단계를 포함할 수 있다. 일부 또 다른 구현예들에서, 방법들은 기판을 약 250℃의 온도까지 가열하는 단계를 포함할 수 있다.
본 개시의 구현예들은 선택적 실리콘 질화물을 증착하기 위해 사용되는 반응 챔버 내 압력을 감소시키는 단계를 더 포함할 수 있다. 예를 들면, 일부 구현예에서, 선택적 증착은 50 Torr 미만의 반응 챔버 압력, 또는 25 Torr 미만의 반응 챔버 압력, 또는 10 Torr 미만의 반응 챔버 압력, 또는 심지어 5 Torr 미만의 반응 챔버 압력에서 수행될 수 있다.
본 개시의 일부 구현예들에서, 기판은 제1 금속 표면 및 제2 유전체 표면을 포함할 수 있다. 구분 가능한 어떠한 증착도 일어나지 않는 주기적인 선택적 증착 공정의 초기 단계들에서 주기적인 증착 사이클의 수는, 주기적인 선택적 증착 공정에서 사용되는 공정 파라미터 및 반응물의 화학적 성질을 제어함으로써 변경될 수 있다. 그러므로, 본 개시의 구현예들은 선택적 실리콘 질화막 증착 공정을 가능하게 하기 위해 제1 금속 표면 및 제2 유전체 표면의 인큐베이션 기간을 제어하기 위한 방법들을 제공한다. 그러므로, 일부 구현예들에서, 제1 금속 표면에 대한 인큐베이션 기간은 제2 표면에 대한 인큐베이션 기간보다 작을 수 있고, 즉 주기적인 선택적 증착 공정의 초기 단계들에서, 주기적인 선택적 증착은 금속 표면 상에서의 증착을 선호할 수 있다.
도 2는 클러스터화된 티타늄 질화물(TiN) 표면과 산화된 티타늄 질화물 표면 상에서의 증착 대비 자연 실리콘 산화물 표면 상에서 실리콘 질화막의 선택적 증착을 도시한다. 보다 상세히, 도 2는 시료의 중앙에 증착된 실리콘 질화물의 두께 대 주기적인 선택적 증착 사이클의 수를 도시하고 있고, 여기서 202로 표시된 데이터는 자연 실리콘 산화물 상에서 실리콘 질화물의 증착을 도시하고, 204로 표시된 데이터는 산화된 티타늄 질화물 상에서 실리콘 질화물의 증착을 도시하고, 206으로 표시된 데이터는 클러스터화된 티타늄 질화물 상에서 실리콘 질화물의 증착을 도시한다. 특별한 증착 공정에 대한 인큐베이션 기간은 증착 데이터와 y=0인 축의 교차에 의해 결정될 수 있다. 자연 실리콘 산화물 상에서 실리콘 질화물 증착에 대한 인큐베이션 기간은 208로 표시되어 있고 약 100회의 수 많은 사이클을 도시하므로, 본 개시의 일부 구현예들에서, 제2 유전체 표면들에 대한 인큐베이션 기간은 약 100 사이클보다 적다. 클러스터화된 티타늄 질화물 상에서 그리고 산화된 티타늄 질화물 상에서 실리콘 질화물 증착에 대한 인큐베이션 기간들은 실질적으로 동일하고 도 2에서 210으로 표시되고 약 20 사이클의 인큐베이션 기간을 나타낸다. 그러므로, 일부 구현예들에서, 제1 금속 표면에 대한 인큐베이션 기간은 제2 유전체 표면에 대한 인큐베이션 기간보다 작고, 일부 또 다른 구현예들에서, 실리콘 질화막의 핵생성율은 제2 유전체 상에서보다 제1 금속 표면 상에서 더 높다.
초기 인큐베이션 기간이 종료된 후, 제1 금속 표면 상 및 제2 유전체 표면 상 모두에서 실리콘 질화물 증착은 실질적으로 정해진 속도로 진행된다. 일반적으로
Figure pat00001
/펄싱 사이클로서 제시되는, 선택적 실리콘 질화막의 증착율은, 예를 들어 화학 흡착 분자들의 표면 상의 많은 이용 가능한 반응성 표면 부위나 활성 부위의 개수 및 그 흡착 분자들의 벌키성(bulkiness)을 비롯한 많은 인자들에 따라 달라진다. 일부 구현예에서, 이러한 막의 증착률은 약 0.1 내지 약 5.0 Å/펄싱 사이클의 범위일 수 있다. 일부 구현예에서, 증착률은 약 0.1, 0.2, 0.3, 0.5, 1.0, 1.5, 2.0, 2.5, 3.0, 3.5, 4.0, 4.5, 5.0 Å/펄싱 사이클일 수 있다.
제1 금속 표면 및 제2 유전체 표면을 포함하는 기판 상에 선택적 실리콘 질화막을 형성하기 위한 선택적 증착 공정은 선택적 실리콘 질화물의 원하는 두께가 이루어질 때까지 1회 이상 반복될 수 있다. 도 1을 다시 참조하면, 공정 블록(108)은 선택적 증착 공정을 반복 또는 반복하지 않아야 하는지의 여부를 결정하기 위한 결정 게이트(decision gate)를 도시하며, 이러한 결정 게이트는 선택적 실리콘 질화막의 원하는 두께에 의해 결정된다. 예를 들면, 일부 구현예들에서, 선택적 증착 공정에 의해 기판 상에 선택적 실리콘 질화막을 형성하는 단계는 약 10 옴스트롬 내지 약 40 옹스트롬의 두께를 갖는 선택적 실리콘 질화막을 형성하는 단계를 포함한다. 일부 구현예들에서, 방법들은 기판 상에 50 옹스트롬 미만, 또는 40 옹스트롬 미만, 또는 30 옹스트롬 미만, 또는 20 옹스트롬 미만, 또는 심지어 10 옹스트롬 미만의 두께를 갖는 선택적 실리콘 질화막을 형성하는 단계를 포함할 수 있다.
도 2는 자연 실리콘 산화물 표면 상에 실리콘 질화막의 선택적 증착을 위한 인큐베이션 기간 동안, 자연 실리콘 산화막 표면 상에 실질적으로 어떠한 증착도 없는 반면에 클러스터화된 티타늄 질화물 표면 상 및 클러스터화된 티타늄 질화막 표면 상 모두에 상당한 증착이 있는 것을 도시한다. 증착 공정의 선택도는 제1 금속 표면 (A) 상에 형성된 재료의 양에 대한 제1 금속 표면 (A) 상에 형성된 재료의 양 - 제2 유전체 표면 (B) 상에 형성된 재료의 양의 비로서 표현될 수 있다(즉, 선택도는 [(제1 금속 표면 상의 증착)-(제2 유전체 표면 상 증착)/(제1 금속 표면 상 증착) 또는 [(A-B)/A]. 일부 구현예들에서, 선택도는 약 70%를 초과할 수 있거나, 약 80%를 초과할 수 있거나, 약 90%를 초과할 수 있거나, 약 95%를 초과할 수 있거나, 약 98%를 초과할 수 있거나, 약 99%를 초과할 수 있거나, 약 100%일 수 있다. 일부 경우들에서, 80%를 초과하는 선택도는 특정 응용들에 대해 타당할 수 있다. 일부 경우들에서, 50%를 초과하는 선택도는 특정 응용들에 대해 타당할 수 있다. 일부 구현예들에서, 증착 온도는 선택도가 약 90%를 초과하도록 선택될 수 있다. 일부 구현예들에서, 증착 온도는 약 100%의 선택도가 달성될 수 있도록 선택될 수 있다. 비제한적인 예로서, (그리고 도 2를 참조하면), 자연 실리콘 산화물 표면(즉, 제2 유전체 표면)의 인큐베이션 기간 동안, 선택적 실리콘 질화물 증착 공정은 제1 금속 표면 상(즉, 클러스터화된 티타늄 질화물 표면 상 또는 산화된 티타늄 질화물 표면 상)의 증착에 대하여 100% 선택적이다. 도 2에 도시된 바와 같이, 제2 유전체 표면(즉, 자연 산화물 표면)의 인큐베이션 기간 동안, 제1 금속 표면 상(예컨대, 클러스터화된 티타늄 질화물 표면 상 또는 산화된 티타늄 질화물 표면 상)에 100%의 선택도를 갖는 약 25 옹스트롬 미만의 실리콘 질화물을 증착하는 것이 가능하다.
본 개시의 일부 구현예들에서, 제2 유전체 표면 상에 어떠한 또는 실질적으로 어떠한 실리콘 질화물 형성이 없이 제1 금속 표면 상에 실리콘 질화막들을 더 두껍게 증착하는 것이 바람직할 수 있다. 도 3은 제2 유전체 표면 상보다 제1 금속 표면 상에서 더 두꺼운 실리콘 질화막들을 선택적으로 형성하기 위한 방법들을 포함할 수 있는 방법(300)을 도시한다. 이 방법(300)은 방법(100)에 대하여 앞서 서술된 바와 같이 주기적인 선택적 증착 공정으로 시작할 수 있고, 실리콘 할로겐화물 소스(304)를 포함하는 제1 반응물과 기판을 접촉시키는 단계 및 질소 공급원(306)을 포함하는 제2 반응물과 기판을 접촉시키는 단계를 포함하는 하나 이상의 증착 사이클(예컨대, ALD 사이클)을 포함할 수 있다. 주기적인 선택적 증착 공정(302)은 원하는 두께의 실리콘 질화막이 증착될 때까지 반복될 수 있다. 이러한 구현예들에서, 실리콘 질화막이 제1 금속 표면 상 및 제2 유전체 표면 상 모드에 증착되도록 주기적인 선택적 증착 공정은 제2 유전체 표면의 경우 인큐베이션 기간을 넘어서 작동될 수 있다. 그러므로, 본 개시의 구현예들은 제1 금속 표면 상에 실리콘 질화막을 제1 두께까지 형성하는 단계 및 제2 유전체 표면 상에 실리콘 질화막을 제2 두께까지 형성하는 단계를 더 포함할 수 있고, 상기 제1 두께는 상기 제2 두께보다 두껍다.
제1 금속 표면 및 제2 유전체 표면 상 모두에 원하는 두께까지 실리콘 질화막을 형성할 때, 기판 및 그 위에 놓인 실리콘 막은 도 3의 공정 블록(310)에 도시된 바와 같이 식각 공정에 노출되어 실리콘 질화막의 일부를 제거할 수 있다. 일부 구현예들에서, 주기적인 선택적 증착 공정을 수행하기 위한 반응 챔버 및 식각 공정을 수행하기 위한 반응 챔버는 동일할 수 있다. 다른 구현예들에서, 기판은 주기적인 선택적 실리콘 질화물 증착을 위해 구성된 제1 반응 챔버로부터 실리콘 질화막을 식각하도록 구성된 제2 반응 챔버로 이송된다. 제1 반응 챔버 및 제2 반응 챔버는 동일한 반도체 처리 장치의 일부일 수 있고 제어되는 환경 조건들을 갖는 이송 챔버를 장착하고 있는 클러스터 도구를 포함할 수 있어서, 기판이 주위 조건에 노출되는 것을 방지한다. 일부 구현예들에서, 실리콘 질화막의 일부를 식각하도록 구성된 제2 반응 챔버는 반응성 이온 식각, 유도 결합형 플라즈마 식각 또는 전자 사이클론 공명 식각 중 적어도 하나를 위해 구성될 수 있다. 일부 구현예들에서, 실리콘 질화막의 일부를 식각하도록 구성된 제2 반응 챔버는 원자층 식각(ALE)을 위해 구성될 수 있다.
기판이 실리콘 질화막의 일부를 식각하도록 구성된 반응 챔버 내에 위치되면, 상기 방법들은 제2 유전체 표면 상의 실리콘 질화막이 실질적으로 제거될 때까지 제2 유전체 표면 상의 실리콘 질화막을 식각하는 단계 및 이와 동시에 제1 금속 표면 상의 실리콘 질화막이 부분적으로 제거될 때까지 제1 금속 표면 상의 실리콘 질화막을 식각하는 단계를 포함할 수 있다. 비제한적인 예로서, 실리콘 질화막은 염소계 식각 화학 현상 또는 불소계 식각 화학 현상을 이용하여 식각될 수 있다. 그러므로, 제2 유전체 표면 상에 증착되었던 과량의 임의 실리콘 질화물은 제거될 수 있고, 반면에 제1 금속 표면 상의 실리콘 질화막의 일부는 남아 있을 수 있다.
식각 공정을 완료하면, 제1 금속 표면 상의 실리콘 질화물의 두께가 결정될 수 있고(도 3의 공정 블록 312), 제1 금속 표면 상에 추가적인 실리콘 질화물이 필요하면, 주기적인 선택적 실리콘 질화막을 위해 구성된 반응 챔버로 기판이 이송될 수 있다. 그러므로, 일부 구현예들에서, 실리콘 질화막을 식각하고 선택적으로 형성하는 공정들은 2회 이상 반복되고, 즉 방법(300)은 그 방법이 종료될 수 있는 지점(도 3의 공정 블록 314)에서 원하는 두께의 실리콘 질화물이 증착될 때까지 2회 이상 반복된다.
일부 구현예들에서, 제1 금속 표면 및 제2 유전체 표면을 포함하는 기판이 제공된다. 일부 구현예들에서, 제1 금속 산화물 표면, 제1 금속 질화물 표면, 제1 금속 실리사이드 표면, 제1 금속 붕소화물 표면, 또는 제1 반금속 표면을 포함하는 기판이 제공된다. 일부 구현예들에서, 제2 유전체 표면은 -OH 기를 포함할 수 있다. 일부 구현예들에서, 제2 유전체 표면은 SiO2 표면일 수 있다. 일부 구현예들에서, 제2 유전체 표면은 Si-O 결합을 포함할 수 있다. 일부 구현예들에서, 제2 유전체 표면은 SiO2계 낮은 k 재료를 포함할 수 있다. 일부 구현예들에서, 제2 유전체 표면은 약 30% 초과, 또는 일부 구현예들에서 약 50% 초과의 SiO2를 포함할 수 있다. 또 다른 구현예들에서, 제2 유전체 표면은 실리콘 질화물 표면 또는 실리콘 산질화물 표면을 포함할 수 있다. 일부 구현예들에서, 제2 유전체 표면은 GeO2를 포함할 수 있다. 일부 구현예들에서, 제2 유전체 표면은 Ge-O 결합을 포함할 수 있다.
본 개시의 일부 구현예들에서, 상기 방법들은 티타늄 질화물, 티타늄 실리콘 질화물(TiSiN), 탄탈륨 질화물(TaN), 탄탈륨 실리콘 질화물, 텅스텐(W), 몰리브덴(Mo), 실리콘(Si), 실리콘 게르마늄(SiGe), 게르마늄 안티몬 텔루륨(GeSbTe), 코발트(Co), 탄탈륨 실리사이드(TaSi), 티타늄 실리사이드(TiSi), 갈륨 비소 또는 갈륨 질화물 중 적어도 하나를 포함하는 제1 금속 표면을 선택하는 단계를 포함할 수 있다.
본 개시의 일부 구현예들에서, 상기 방법들은 실리콘 산화물, 실리콘 질화물, 실리콘 산질화물, 탄소, 하프늄 산화물(HfO), 지르코늄 산화물(ZrO), 알루미늄 산화물(AlO), 티타늄 산화물(TiO) 또는 실리콘산탄화물(silicon oxycarbide, SiOC) 중 적어도 하나를 포함하는 제2 유전체 표면을 선택하는 단계를 포함할 수 있다.
본원에서 설명되는 공정들은 반도체 소자 구조체, 예컨대, 메모리 소자, 소자 라이너(device liner), 소자 스페이서, 희생층, 발광 다이오드를 포함하는 다이오드, 및 FinFETs과 같은 다중 게이트 트랜지스터뿐만 아니라 평면 소자를 포함하는 트랜지스터의 제조를 포함하지만 이에 한정되지 않는 많은 환경에 적용 가능하다는 것을 당업자는 인식할 것이다. 비제한적인 예로서, 도 5는 하나 이상의 반도체 소자들을 전기적으로 연결하기 위한 소자 연결 구조체의 일부를 포함할 수 있는 반도체 소자 구조체(500)를 도시한다. 반도체 소자 구조체(500)는 층간 유전체(502), 층간 유전체(502) 내에 배치된 구리 배선(504), 및 구리 배선(504)과 층간 유전체(502) 사이에 배치된 확산 장벽층(506)을 포함할 수 있다. 일부 구현예들에서, 층간 유전체(502)는 실리콘 산화물 및/또는 낮은 k 유전체 재료를 포함할 수 있고, 확산 장벽층(506)은 탄탈륨, 탄탈륨 질화물, 텅스텐 또는 텅스텐 질화물을 포함할 수 있다. 도 5에 도시된 바와 같이, 구리 배선(504)은 실리콘 질화물 캐핑층(508)으로 덮여질 수 있고, 실리콘 질화물 캐핑층(508)은 본 개시의 선택적 증착 공정들을 이용하여 구리 배선(504)의 표면(504A) 상에 선택적으로 증착될 수 있어서, 실리콘 질화물 재료는 층간 유전체 표면(502A) 상에서 어떠한 또는 실질적으로 어떠한 실리콘 질화물 증착 없이 구리 배선(504)의 표면(504A) 상에 선택적으로 증착된다.
본 개시의 구현예들은 또한 본 개시의 실리콘 질화막을 선택적으로 형성하도록 구성된 반응 시스템을 포함할 수 있다. 보다 상세하게는, 도 4는 소정의 압력, 온도, 및 주변 조건하에서 기판(미도시)을 유지하기 위한, 그리고 다양한 가스에 기판을 선택적으로 노출시키기 위한 메커니즘을 더 포함하는 반응 챔버(402)를 갖는 반응 시스템(400)을 개략적으로 도시한다. 전구체 반응물 공급원(404)은 도관 또는 다른 적절한 수단(404A)에 의해 반응 챔버(402)에 연결될 수 있고, 매니폴드, 밸브 제어 시스템, 질량 유량 제어 시스템, 또는 전구체 반응물 공급원(404)으로부터 유래되는 가스 전구체를 제어하기 위한 메커니즘에 추가로 연결될 수 있다. 전구체 반응물 공급원(404)에 의해 공급되는 전구체(미도시), 반응물(미도시)은 실온 및 표준 대기압 조건하에서 액체 또는 고체일 수 있다. 이러한 전구체는, 전구체 공급원 챔버 내에서 기화 온도 이상으로 유지될 수 있는 반응물 공급원 진공 용기(vessel) 내에서 기화될 수 있다. 이러한 구현예에서, 기화된 전구체는 캐리어 가스(예를 들어, 비활성 또는 불활성 가스)와 함께 이동된 후 도관(404A)을 통해 반응 챔버(402) 내로 공급될 수 있다. 다른 구현예에서, 전구체는 표준 조건 하의 증기일 수 있다. 이러한 구현예에서, 전구체는 기화될 필요가 없으며, 캐리어 가스를 요구하지 않을 수 있다. 예를 들면, 일 구현예에서, 전구체는 가스 실린더 내에 저장될 수 있다. 반응 시스템(400)은 추가적인 전구체 반응물 공급원을 또한 포함할 수 있으며, 이러한 전구체 반응물 공급원(406)은 또한 위에서 설명된 바와 같이 도관(406A)에 의해 반응 챔버에게 연결될 수 있다.
퍼지 가스 공급원(408)은 도관(408A)을 통해 반응 챔버(402)로 연결될 수 있으며, 다양한 불활성 또는 비활성(noble) 가스를 반응 챔버(402)에 선택적으로 공급하여 반응 챔버로부터 전구체 가스 또는 폐가스를 제거하는 것을 돕는다. 공급될 수 있는 다양한 불활성 또는 비활성 가스는 고체, 액체 또는 저장된 기체 형태로부터 유래될 수 있다.
도 4의 반응 시스템(400)은 또한, 반응 시스템(400)에 포함된 밸브, 매니폴드, 펌프 및 기타 설비를 선택적으로 조작하기 위한 전자 회로 및 기계적 부품을 제공하는 시스템 조작 및 제어 메커니즘(410)을 포함할 수 있다. 이러한 회로 및 부품을 조작하여, 각각의 전구체 공급원(404, 406) 및 퍼지 가스 공급원(408)으로부터 전구체, 퍼지 가스를 도입한다. 시스템 조작 및 제어 메커니즘(410)은 가스 펄스 순서의 타이밍, 기판 및 반응 챔버의 온도, 및 반응 시스템(400)의 적절한 동작을 제공하는데 필요한 반응 챔버의 압력 및 다양한 다른 동작 또한 제어한다. 조작 및 제어 메커니즘(410)은 반응 챔버(402) 내외로의 전구체, 반응물, 및 퍼지 가스의 유동을 제어하기 위한 제어 소프트웨어 및 전기적 또는 공기압적 제어 밸브를 포함할 수 있다. 제어 시스템은 소프트웨어 또는 하드웨어 구성 요소, 예를 들어 특정 작업을 수행하는 FPGA 또는 ASIC과 같은 모듈을 포함할 수 있다. 유리하게는, 모듈은 제어 시스템의 어드레스 가능한 저장 매체에 탑재되어 하나 이상의 공정을 실행하도록 구성될 수 있다.
당업자는 상이한 개수 및 종류의 전구체 반응물 공급원 및 퍼지 가스 공급원을 포함하는 본 반응 시스템의 다른 구성이 가능함을 이해한다. 또한, 당업자는 가스를 반응 챔버(402) 내로 선택적으로 공급하는 목적을 달성하는데 사용될 수 있는 밸브, 도관, 전구체 공급원, 퍼지 가스 공급원의 다수의 배열이 존재함을 이해할 것이다. 또한, 반응 시스템이 개략적으로 표현되었기 때문에, 예시의 단순화를 위해 다수의 부품이 생략되어 있으며, 이러한 부품들은 예를 들면 다양한 밸브, 매니폴드, 정화기, 가열기, 용기, 벤트, 및/또는 우회로를 포함할 수 있다. 일부 구현예에서, 반응 시스템(400)은 두 개 이상의 반응 챔버를 포함할 수 있으며, 여기서 반응 챔버 각각은 원하는 공정을 위해 구성될 수 있는데, 예를 들면, 제1 반응 챔버는 주기적인 선택적 증착 공정을 위해 구성될 수 있고, 제2 반응 챔버는 식각 공정을 위해 구성될 수 있다. 또한, 반응 시스템(400)은 기판을 제어된 조건하에서 제1 반응 챔버로부터 제2 반응 챔버로 이송하기 위한 이송 챔버를 포함할 수 있다.
위에 설명된 본 개시의 예시적 구현예들은 본 발명의 구현예들의 예시일 뿐이기 때문에 이들 구현예들은 첨부된 청구범위 및 그의 법적 등가물에 의해 정의되는 본 발명의 범주를 제한하지 않는다. 임의의 등가적인 구현예들은 본 발명의 범주 내에 있도록 의도된다. 확실하게, 본원에 나타나고 설명된 것 외에도, 설명된 요소들의 대안적인 유용한 조합과 같은 본 개시의 다양한 변경은 상세한 설명으로부터 당업자에게 분명해질 수 있다. 이러한 변경 및 구현예들도 첨부된 청구범위의 범주 내에 있는 것으로 의도된다.

Claims (22)

  1. 제1 금속 표면 및 제2 유전체 표면을 포함하는 기판 상에 실리콘 질화막을 주기적인 증착 공정에 의해 선택적으로 형성하기 위한 방법으로서,
    실리콘 할로겐화 소스를 포함하는 제1 반응물과 상기 기판을 접촉시키는 단계, 및
    질소 소스를 포함하는 제2 반응물과 상기 기판을 접촉시키는 단계를 포함하고,
    상기 제1 금속 표면에 대한 인큐베이션 기간은 상기 제2 유전체 표면에 대한 인큐베이션 기간보다 작은, 방법.
  2. 제1항에 있어서, 상기 실리콘 질화막의 핵생성율은 상기 제2 유전체 표면 상에서보다 상기 제1 금속 표면 상에서 더 높은, 방법.
  3. 제1항에 있어서, 상기 기판을 반응 챔버 내에서 약 225℃ 내지 약 280℃의 온도로 가열하는 단계를 더 포함하는, 방법.
  4. 제3항에 있어서, 상기 기판을 상기 반응 챔버 내에서 약 225℃ 내지 약 250℃의 온도로 가열하는 단계를 더 포함하는, 방법.
  5. 제1항에 있어서, 상기 주기적 증착 공정은 원자층 증착을 포함하는, 방법.
  6. 제1항에 있어서, 상기 주기적 증착 공정은 주기적인 화학 기상 증착을 포함하는, 방법.
  7. 제1항에 있어서, 상기 방법은, 상기 기판이 상기 제1 반응물 및 상기 제2 반응물과 교대로 순차적으로 접촉되는 적어도 1회의 증착 사이클을 포함하는, 방법.
  8. 제7항에 있어서, 상기 증착 사이클이 2회 이상 반복되는, 방법.
  9. 제1항에 있어서, 실리콘 테트라이오다이드(SiI4), 실리콘 테트라브로마이드(SiBr4), 실리콘 테트라클로라이드(SiCl4), 헥사클로로디실란(Si2Cl6), 헥사이오도디실란 (Si2I6) 또는 옥토이오도트리실란(Si3I8) 중 적어도 하나를 포함하도록 상기 실리콘 할로겐화 소스를 선택하는 단계를 더 포함하는, 방법.
  10. 제1항에 있어서, 암모니아(NH3), 하이드라진(N2H4) 또는 알킬-하이드라진 중 적어도 하나를 포함하도록 상기 질소 소스를 선택하는 단계를 더 포함하는, 방법.
  11. 제1항에 있어서, 상기 제2 유전체 표면에 대한 인큐베이션 기간은 약 100 사이클 미만인, 방법.
  12. 제1항에 있어서, 상기 제1 금속 표면에 대한 인큐베이션 기간은 약 20 사이클 미만인, 방법.
  13. 제1항에 있어서, 티타늄 질화물(TiN), 티타늄 실리콘 질화물(TiSiN), 탄탈륨 질화물(TaN), 탄탈륨 실리콘 질화물(TaSiN), 텅스텐(W), 몰리브덴(Mo), 실리콘(Si), 실리콘 게르마늄(SiGe), 게르마늄 안티몬 텔루륨(GeSbTe), 코발트(Co), 탄탈륨 실리사이드(TaSi), 티타늄 실리사이드(TiSi), 갈륨 비소(GaAs) 또는 갈륨 질화물(GaN) 중 적어도 하나를 포함하는 제1 금속 표면을 선택하는 단계를 더 포함하는 방법.
  14. 제1항에 있어서, 실리콘 산화물(SiO), 실리콘 질화물(SiN), 실리콘 산질화물(SiON), 탄소(C), 하프늄 산화물(HfO), 지르코늄 산화물(ZrO), 알루미늄 산화물(AlO), 티타늄 산화물(TiO) 또는 실리콘산탄화물(silicon oxycarbide, SiOC) 중 적어도 하나를 포함하는 제2 유전체 표면을 선택하는 단계를 더 포함하는 방법.
  15. 제1항에 있어서, 상기 제1 금속 표면 상에 상기 실리콘 질화막을 제1 두께까지 형성하는 단계 및 상기 제2 유전체 표면 상에 상기 실리콘 질화막을 제2 두께까지 형성하는 단계를 더 포함하고, 상기 제1 두께는 상기 제2 두께보다 두꺼운, 방법.
  16. 제15항에 있어서, 상기 제2 유전체 표면 상의 상기 실리콘 질화막이 실질적으로 제거될 때까지 상기 제2 유전체 표면 상의 상기 실리콘 질화막을 식각하는 단계 및 이와 동시에 상기 제1 금속 표면 상의 상기 실리콘 질화막이 부분적으로 제거될 때까지 상기 제1 금속 표면 상의 상기 실리콘 질화막을 식각하는 단계를 더 포함하는 방법.
  17. 제16항에 있어서, 식각은 원자층 식각을 포함하는, 방법.
  18. 제17항에 있어서, 상기 실리콘 질화막의 형성 및 상기 원자층 식각은 클러스터 도구에서 수행되는, 방법.
  19. 제16항에 있어서, 실리콘 질화막을 식각 및 선택적으로 제거하는 공정들은 2회 이상 반복되는, 방법.
  20. 제1항에 있어서, 상기 실리콘 할로겐화물 소스를 약 100℃ 미만의 온도로 예열하는 단계를 더 포함하는, 방법.
  21. 제1항의 방법에 의해 형성된 실리콘 질화막을 포함하는 반도체 소자 구조체.
  22. 제1항의 방법을 수행하도록 구성된 반응 시스템.
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