US7172497B2 - Fabrication of semiconductor interconnect structures - Google Patents

Fabrication of semiconductor interconnect structures Download PDF

Info

Publication number
US7172497B2
US7172497B2 US10264726 US26472602A US7172497B2 US 7172497 B2 US7172497 B2 US 7172497B2 US 10264726 US10264726 US 10264726 US 26472602 A US26472602 A US 26472602A US 7172497 B2 US7172497 B2 US 7172497B2
Authority
US
Grant status
Grant
Patent type
Prior art keywords
surface
process
method
substrate
conductive material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active, expires
Application number
US10264726
Other versions
US20030032373A1 (en )
Inventor
Bulent M. Basol
Homayoun Talieh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Novellus Systems Inc
Original Assignee
ASM NuTool Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Grant date

Links

Images

Classifications

    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/04Electroplating with moving electrodes
    • C25D5/06Brush or pad plating
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B24GRINDING; POLISHING
    • B24BMACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00Lapping machines or devices; Accessories
    • B24B37/04Lapping machines or devices; Accessories designed for working plane surfaces
    • B24B37/042Lapping machines or devices; Accessories designed for working plane surfaces operating processes therefor
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B24GRINDING; POLISHING
    • B24BMACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00Lapping machines or devices; Accessories
    • B24B37/04Lapping machines or devices; Accessories designed for working plane surfaces
    • B24B37/046Lapping machines or devices; Accessories designed for working plane surfaces using electric current
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B24GRINDING; POLISHING
    • B24BMACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B49/00Measuring or gauging equipment for controlling the feed movement of the grinding tool or work; Arrangements of indicating or measuring equipment, e.g. for indicating the start of the grinding operation
    • B24B49/16Measuring or gauging equipment for controlling the feed movement of the grinding tool or work; Arrangements of indicating or measuring equipment, e.g. for indicating the start of the grinding operation taking regard of the load
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/22Electroplating combined with mechanical treatment during the deposition
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00Electroplating characterised by the article coated
    • C25D7/12Semiconductors
    • C25D7/123Semiconductors coated first with a seed layer, e.g. for filling vias
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67155Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67161Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers
    • H01L21/67173Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers in-line arrangement
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67155Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67207Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67155Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67207Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
    • H01L21/67219Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process comprising at least one polishing chamber
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67155Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67207Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
    • H01L21/6723Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process comprising at least one plating chamber
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684Smoothing; Planarisation
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D17/00Constructional parts, or assemblies thereof, of cells for electrolytic coating
    • C25D17/001Apparatus specially adapted for plating wafers, e.g. semiconductors, solar cells

Abstract

A system and a method of forming copper interconnect structures in a surface of a wafer is provided. The method includes a step of performing a planar electroplating process in an electrochemical mechanical deposition station for filling copper material into a plurality of cavities formed in the surface of the wafer. The electroplating continues until a planar layer of copper with a predetermined thickness is formed on the surface of the wafer. In a following chemical mechanical polishing step the planar layer is removed until the copper remains in the cavities, insulated from one another by exposed regions of the dielectric layer.

Description

REFERENCE TO RELATED APPLICATIONS

This Application is a continuation in part of U.S. patent application Ser. No. 09/795,687 filed Feb. 27, 2001, now U.S. Pat. No. 6,953,392 claiming priority to Prov. No. 60/261,263 filed Jan. 16, 2001 and Prov. No. 60/259,676 filed Jan. 5, 2001, all incorporated herein by reference.

FIELD

The present invention relates to manufacture of semiconductor integrated circuits and more particularly to a method of electrochemical mechanical deposition and chemical mechanical polishing of conductive layers.

BACKGROUND

Conventional semiconductor devices generally include a semiconductor substrate, usually a silicon substrate, and a plurality of sequentially formed dielectric interlayers such as silicon dioxide and conductive paths or interconnects made of conductive materials. Copper and copper alloys have recently received considerable attention as interconnect materials because of their superior electromigration and low resistivity characteristics. The interconnects are usually formed by filling copper in features or cavities etched into the dielectric interlayers by a metallization process. The preferred method of copper metallization process is electroplating. In an integrated circuit, multiple levels of interconnect networks laterally extend with respect to the substrate surface. Interconnects formed in sequential interlayers can be electrically connected using vias or contacts.

In a typical process, first an insulating interlayer is formed on the semiconductor substrate. Patterning and etching processes are performed to form features such as trenches and vias in the insulating layer. Typically the width of the trenches is larger than the width of the vias. Then, copper is electroplated to fill the features. Once the plating is over, a chemical mechanical polishing (CMP) step is conducted to remove the excess copper layer and other conductive layers that are above the top surface of the substrate to form the interconnect structure. These processes are repeated multiple times to manufacture multi layer interconnects.

An exemplary prior art process can be briefly described with the help of FIGS. 1A and 1B. FIG. 1A shows a substrate 8 which is processed to form an exemplary dual damascene structure shown in FIG. 1B. In this structure, a via 10 and a trench 12 are formed in an isolating layer 14 on the substrate 8, and filled with copper 16 through electroplating process. Conventionally, after patterning and etching which form the cavities such as vias and trenches, the isolating layer 14 is first coated with a barrier layer 18, for example, a Ta/TaN composite layer. The barrier layer 18 coats the insulating layer to ensure good adhesion and acts as a barrier material to prevent diffusion of the copper into the insulating layers and into the semiconductor devices. Next, a seed layer (not shown), which is often a copper layer, is deposited on the barrier layer. The seed layer forms a conductive material base for copper crystal growth during the subsequent copper deposition. As the copper film is electroplated, the copper 16 quickly fills the small via 10 but coats the wide trench and the surface in a conformal manner. When the deposition process is continued, the trench is also filled with copper, but with a step ‘s’ and a thick copper layer ‘t’. Thick copper on the surface presents a problem during CMP step that is expensive and time consuming. As shown in FIG. 1B, during the CMP removal of the thick copper layer on the trench 12 and the barrier layer 18 on the top surface, a non-planar 20 surface may be formed on the remaining surface of the copper layer. The non-planar surface may form due to the difference in polishing rate between the barrier layer and the copper. The non-planar surface 20, or so called “dishing effect”, adversely affects the quality of the subsequently deposited layers.

Some prior art processes attempt to minimize or eliminate the dishing effect by employing multiple polishing steps with different slurries and polishing pads. For example, in one particular prior art process, at a first CMP process step the bulk copper layer on the substrate is removed down to a thickness that is over the barrier layer. The first step is performed in a first CMP station with a polishing pad that has no abrasive particles. A second step is performed in a second CMP station that has a pad with fixed abrasives to expose a portion of the barrier layer that overlies the insulating layer. In a third step, the portion of the barrier layer that overlies the insulating layer is removed using a pad that has no fixed particles. The third step is performed in a third CMP station.

In such prior art processes, multiple polishing steps increase the production time and the production cost. To this end, there is a need for an alternative method of planarizing plated substrates.

SUMMARY

The present invention provides a method of and system for plating a conductor and then chemically mechanically polishing the plated conductor in an advantageous manner that increases throughput and reduces defects. In particular, the conductor is plated using an electrochemical mechanical deposition (ECMD) process, and thereafter subjected to chemical mechanical polishing (CMP).

An exemplary embodiment system and a method of forming copper interconnect structures in a surface of a wafer is provided. The method includes a step of performing a planar electroplating process in an electrochemical mechanical deposition station for filling copper material into a plurality of cavities formed in the in the insulator layer or dielectric layer on the surface of the wafer. The electroplating continues until a planar layer of copper with a predetermined thickness is formed on the surface of the wafer. In a following chemical mechanical polishing step the planar layer is removed until the copper remains only in the cavities, isolated from one another by the dielectric layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a schematic illustration of a prior art dual damascene structure having an electrodeposited copper overburden layer;

FIG. 1B is a schematic illustration of the prior art structure shown in FIG. 1A wherein the copper overburden and the barrier layer are polished using CMP resulting in dishing in the copper layer;

FIG. 2 is a schematic view of an embodiment of an integrated tool to perform the present invention by employing ECMD and CMP modules;

FIG. 3A is a schematic view of a dual damascene structure having a planar copper layer, wherein the planar copper layer has been electroplated using the system shown in FIG. 2;

FIG. 3B is a schematic view of the structure shown in FIG. 3A, wherein the planar copper layer has been polished using the system shown in FIG. 2;

FIG. 3C is a schematic view of the structure shown in FIG. 3B, wherein a barrier layer has been removed from the field regions;

FIG. 4 is a schematic view of a second embodiment of an integrated tool to perform the present invention by employing ECMD and CMP modules;

FIG. 5A is a schematic view of a dual damascene structure having a planar copper layer, wherein the planar copper layer has been electroplated using the system shown in FIG. 4; and

FIG. 5B is a schematic view of the structure shown in FIG. 3A, wherein the both planar copper layer and the barrier layer on the field regions have been polished using the system shown in FIG. 4.

DETAILED DESCRIPTION

As will be described below, the present invention provides a method and a system for manufacturing interconnects for semiconductor integrated circuits. In one embodiment, the present invention employs a planar deposition process, such as electrochemical mechanical deposition (ECMD) process and chemical mechanical polishing process (CMP) to form copper interconnects. In this embodiment, for example, a thin planar copper layer is initially formed by an ECMD process step which is subsequently removed by carrying out two separate CMP process steps to produce final interconnect structure. In another embodiment, an initial ECMD process step is used to form a planar layer that is thinner than the layer formed in the first embodiment. This thin planar layer along with the barrier are removed using a single CMP step to form the final interconnect structure.

Descriptions of various ECMD deposition methods and apparatuses that provide for planar deposition of a conductor can be found in the following patents and pending applications, all commonly owned by the assignee of the present invention. U.S. Pat. No. 6,176,992, entitled “Method and Apparatus for Electrochemical Mechanical Deposition.” U.S. application Ser. No. 09/740,701, now U.S. Patent Publication No. 2002/0074230, entitled “Plating Method and Apparatus that Creates a Differential Between Additive Disposed on a Top Surface and a Cavity Surface of a Workpiece Using an External Influence,” filed on Dec. 18, 2001. A system that uses ECMD, and which can be adapted to obtain the systems described herein and perform the processes described herein is discussed in U.S. Utility application Ser. No. 09/795,687, now U.S. Patent Publication No. 2002/0088543, entitled “Integrated System for Processing Semiconductor Wafers” filed on Feb. 27, 2001 (incorporated herein by reference above) and which is based on priority provisional applications No. 60/259,676 filed Jan. 5, 2001 and No. 60/261,263 filed Jan. 16, 2001. As described in those references, the ECMD uniformly fills holes (or vias) and trenches on a surface of a wafer with a conductive material while mechanically maintaining the planarity of the surface with a pad.

The CMP process conventionally involves pressing a semiconductor wafer or other such substrate against a moving polishing surface that is wetted with a chemical reactive abrasive slurry. The slurries are usually either basic or acidic and generally contain alumina, ceria, silica or other hard ceramic particles. The polishing surface is typically a planar pad made of polymeric materials well known in the art of CMP. The pad itself may also be an abrasive pad. During a CMP process a wafer carrier with a wafer to be processed is placed on a CMP pad and pressed against it. The pad, which may be an abrasive pad, may be moved laterally as a linear belt or may be rotated. The process is performed by moving the wafer against the pad or the linear belt in a CMP slurry solution flowing between the pad and the wafer surface. The slurry may be any of the known CMP slurries in the art, and may be flowed over the pad or may be flowed through the pad if the pad is porous in the latter case.

Reference will now be made to the drawings wherein like numerals refer to like parts throughout. FIG. 2 shows a first system 100 of the present invention. The first system 100 comprises a processing section 102 comprising a planar conductor deposition station 014 such as an ECMD copper process station as well as a first CMP process station 106 and a second CMP process station 108. A buffer section 110 is in communication with the processing section 102 through a robot 116 or robot arm. Although, in this example, the stations 104108 are shown as an integrated part of the first system 100, they may be individual stations that are located separately. In this embodiment, the stations 104108 may preferably be vertically stacked chambers including a lower process chamber (ECMD or CMP chamber) and a top rinsing and drying chamber. One such exemplary vertical chamber design and operation is disclosed in U.S. Pat. No. 6,352,623, entitled “Vertically Configured Chamber Used for Multiple Processes,” filed Dec. 17, 1999, commonly owned by the assignee of the present invention. In operation, a wafer 114 or work piece to be plated may be picked up from a load unload section (not shown) of the system by the robot 116 which is located in the buffer section 110. The wafer 114 can then be transferred to the ECMD station 104 in the processing section 102 to initiate the process. The process stations 104108 can be either adapted to process 200 or 300 millimeter wafers. The system 100 may also have an anneal chamber (not shown) to anneal the planar deposited substrates before or after the CMP processes, or before and after the CMP process.

FIGS. 3A–3C are schematic cross-sectional views exemplifying the process of the present invention to form a copper interconnect using the method of the present invention and the system shown in FIG. 2. Although copper is used as an example material that is deposited and/or removed herein, the present invention may be used when depositing or removing other conductors, for example Ni, Pd, Pt, Au, Pb, Sn, Ag, Co and their alloys. In this example an exemplary dual damascene structure will be formed in accordance with the principles of the present invention. FIG. 3A shows a semiconductor substrate 120 having a planar copper layer 122 formed in a first step of the present invention. In the ECMD station 104 shown in FIG. 2, the planar layer 122 is electroplated into a via 124 and a trench 126 which are patterned and etched into an insulating layer 128. The insulating layer 128 has a top surface 129 and is formed on a semiconductor wafer 130. A conducting layer 132 conformally coats the via 124, the trench 126 and the top surface 129 of insulating layer 128. The conducting layer 132 comprises a barrier layer. The conducting 132 layer may also comprise a copper seed layer (not shown) which is deposited on the barrier layer 132. The thickness of a portion of the flat copper layer 122 that overlies the top surface 129 of the insulator 128 is related to the depth of the largest feature, i.e., the feature with the largest width, to be filled on the substrate 130, which is in this example the trench 126. If the width of the trench 126 which is denoted by ‘W’ is the largest on the substrate, the thickness ‘t’ of the flat copper portion that overlies the top surface 129 can be equal to or less than 0.75 D, where ‘D’ is the depth of the trench. However, it is understood that if there is a larger, i.e., wider feature, on the entire wafer surface, thickness t will be a function of the depth of that larger feature, i.e., it would be less than or equal to about three quarters of the depth of that largest feature. It should be noted that in the prior art process (see FIG. 1A), the thickness of the copper overburden is larger than D, i.e., t>D. Such thin and flat copper layer produced by the planar deposition techniques such as ECMD process advantageously eliminates the use of a conventional step of removing overburden or the excess copper from the surface of the substrate. The ECMD station 104 then rinses the substrate and sends to the first CMP station 106.

As shown in FIG. 3B, in a second step of the present invention, a CMP process is performed in the first CMP station to polish away the excess flat copper layer, in a planar manner, that overlies barrier layer on the top surface 129 of the insulating layer 128. The second step can preferably be performed using a fixed abrasive pad 134 without an abrasive slurry. The fixed abrasive pad 134 selectively removes the copper layer 122 down to the barrier layer. The first CMP station 106 then rinses the substrate and transfers to the second CMP station 108.

As shown in FIG. 3C, at the final polishing step that is performed in the second CMP station, the barrier layer 132 overlying the top surface 129 of the insulating layer 128 is removed with a slurry based CMP process using a non-abrasive pad 136. Any remaining portions of copper is also removed during this step. Removal of copper and barrier layers using different polishing pad and slurries is disclosed in the co-pending U.S. Provisional Patent Application No. 60/365,001, entitled “Method and Apparats for Integrated Chemical Mechanical Polishing of Copper and Barrier Layers,” filed Mar. 13, 2002, commonly owned by the assignee of the present invention.

FIG. 4 shows a second system 200 of the present invention. The second system 200 comprises a processing section 202 comprising an ECMD process station 204 and a CMP process station 206. A buffer section 210 is connected to the processing section 202. Although, in this example, the stations 204 and 206 are shown as an integrated part of the second system 200, they may be individual stations that are located separately. In this embodiment, the stations 204 and 206 may preferably be vertically stacked chambers including a lower process chamber (ECMD or CMP chamber) and a top rinsing and drying chamber. One such exemplary vertical chamber design and operation is disclosed in the co-pending U.S. Pat. No. 6,352,623, entitled “Vertically Configured Chamber Used for Multiple Processes,” filed Dec. 17, 1999, commonly owned by the assignee of the present invention. In operation, a wafer 214 or work piece to be plated may be picked up from a load/unload section (not shown) of the system by a robot 216 which is located in the buffer section 212. The wafer 214 can then be transferred to the ECMD station in the processing section 202 to initiate the process. The process stations 204 and 206 can be either adapted to process 200 or 300 millimeter wafers. The system 200 may also have an anneal chamber (not shown) to anneal substrates processed in ECMD chamber prior to or after the CMP process, or before and after the CMP process.

FIGS. 5A and 5B are schematic cross-sectional views exemplifying the process of the present invention to form a copper interconnect using the system shown in FIG. 4. In this embodiment a dual damascene structure will be formed in accordance with the principles of the present invention.

FIG. 5A shows a semiconductor substrate having a thin planar copper layer 222 formed in a first step of the present invention. In the ECMD station 204 shown in FIG. 4, the planar layer is electroplated into a via 224 and a trench 226 which are patterned and etched into an insulating layer 228. The insulating layer 228 has a top surface 229 and is formed on a semiconductor wafer 230. A barrier layer 232 coats the via 224, the trench 226 and the top surface 229 of insulating layer 228. In this embodiment, the thickness of a portion of the flat copper layer 222 that overlies the top surface 229 of the insulator 228 is less than or equal to 2000 Angstroms, preferably, less than 1000 Angstroms. Such thin and flat copper layer produced by the ECMD process advantageously eliminates the use of a conventional steps of removing overburden or the excess copper and the barrier layer from the surface of the substrate. The ECMD station 204 then rinses the substrate and sends to the CMP station 206 (see FIG. 4).

As shown in FIG. 5B, in the final step of the present invention, a CMP process is performed to polish away the excess flat copper layer and the barrier layer, in a single polishing step, that overlies barrier layer on the top surface 129 of the insulating layer 128. This step can be performed using a pad 234 with an abrasive slurry or an abrasive pad with non-abrasive slurry. The pad 234 removes the copper layer 222 and the barrier layer 232 down to the top surface 229 of the interconnect 228. Ultimately, a metallic interconnect is formed, thereby forming a complete dual damascene structure. A non-selective slurry may also be used in this step to remove a small thickness of the insulator or dielectric layer, thereby minimizing dishing effects.

It should be noted that although the present invention is described through the use of the ECMD process, it is also applicable to any planar deposition process that can yield thin layers.

Although, exemplary system comprising specific number of process modules have been illustrated and described above, it is understood that the above described systems may include more or less number of ECMD and CMP process modules depending upon throughput considerations. Further, in this application, the systems are shown schematically, thus, the process modules within the systems may be varied without changing the process results of the invention.

Although various preferred embodiments and the best mode have been described in detail above, those skilled in the art will readily appreciate that many modifications of the exemplary embodiment are possible without materially departing from the novel teachings and advantages of this invention.

Claims (16)

1. A method of fabricating conductive structures in a plurality of cavities formed in a surface of a substrate, wherein the surface and the cavities are coated with a conducting film, and wherein the conducting film comprises a barrier layer, the method comprising the steps of:
performing in a first station an electrochemical mechanical deposition (ECMD) process for filling a conductive material into the plurality of cavities until a planar layer of conductive material with a predetermined thickness is formed on the surface of the substrate;
moving the substrate to a second station after performing the ECMD process; and
applying a chemical mechanical polishing process in the second station to polish the conductive material and the conducting film off the surface of the substrate.
2. The method of claim 1, wherein the applying step comprises a first chemical mechanical process step to remove the planar layer until the barrier layer is exposed on the surface and the conductive material remains in the cavities.
3. The method of claim 2, wherein the applying step further comprises a second chemical mechanical process step to remove the barrier layer from the surface while leaving the conductive material in the cavities, isolated from one another, the second chemical mechanical process step being performed after the first chemical mechanical process step.
4. The method of claim 3, wherein the second chemical mechanical polishing process step uses a non-abrasive polishing pad and a polishing slurry.
5. The method of claim 2, wherein the planar layer has a thickness that is less than ¾ of a depth of the cavities.
6. The method of claim 2, wherein the first chemical mechanical polishing process step uses a fixed abrasive polishing pad and a polishing slurry.
7. The method of claim 1, wherein the applying step removes the planar conductive layer and the barrier layer on the surface of the substrate in a single step so that the conductive material remains in the cavities, isolated from one another.
8. The method of claim 7, wherein the predetermined thickness of the planar layer is less than 2000 Angstroms.
9. The method of claim 7, further comprising polishing the surface of the substrate so as to remove a predetermined thickness of an insulator layer on the substrate surface.
10. The method of claim 1, further comprising performing an anneal step for annealing the conductive material prior to chemical mechanical polishing.
11. The method of claim 1, further comprising performing an anneal step for annealing the conductive material prior to chemical mechanical polishing and then subsequent to chemical mechanical polishing.
12. The method of claim 1, further comprising performing an anneal step for annealing the conductive material subsequent to chemical mechanical polishing.
13. The method of claim 1, wherein performing in a first station an electrochemical mechanical deposition (ECMD) process comprises using a pad to maintain the planarity of the surface.
14. A method of fabricating conductive structures in a plurality of cavities formed in a surface of a substrate, wherein the surface and the cavities are coated with a conducting film, and wherein the conducting film comprises a barrier layer, the method comprising the steps of:
performing an electrochemical mechanical deposition (ECMD) process for filling a conductive material into the plurality of cavities until a planar layer of conductive material with a predetermined thickness is formed on the surface of the substrate; and
applying a two step chemical mechanical polishing process to polish the conductive material and the conducting film off the surface of the substrate, wherein a first step of the polishing process removes the conductive material on the surface of the substrate and then a second step of the polishing process removes the barrier layer on the surface so that the conductive material remains in the cavities, isolated from one another.
15. A method of fabricating conductive structures in a plurality of cavities formed in a surface of a substrate, wherein the surface and the cavities are coated with a conducting film, and wherein the conducting film comprises a barrier layer, the method comprising the steps of:
performing in a first station an electrochemical mechanical deposition process for filling a conductive material into the plurality of cavities until a planar layer of conductive material with a predetermined thickness is formed on the surface of the substrate;
moving the substrate into a second station after performing the electrochemical mechanical deposition process; and
applying in a second station a single step chemical mechanical polishing process to polish the conductive material and the conductive film off the surface of the substrate so that the conductive material remains in the cavities, isolated from one another.
16. A method of manufacturing a semiconductor device comprising:
electroplating in a first station a planar layer of conductive material onto a substrate using an electrochemical mechanical deposition (ECMD) process;
moving the substrate into a second station after electroplating; and
performing in a second station a chemical mechanical process to polish the conductive layer.
US10264726 2001-01-05 2002-10-03 Fabrication of semiconductor interconnect structures Active 2021-07-25 US7172497B2 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
US25967601 true 2001-01-05 2001-01-05
US26126301 true 2001-01-16 2001-01-16
US09795687 US6953392B2 (en) 2001-01-05 2001-02-27 Integrated system for processing semiconductor wafers
US32702501 true 2001-10-03 2001-10-03
US36500102 true 2002-03-13 2002-03-13
US10264726 US7172497B2 (en) 2001-01-05 2002-10-03 Fabrication of semiconductor interconnect structures

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10264726 US7172497B2 (en) 2001-01-05 2002-10-03 Fabrication of semiconductor interconnect structures
US10703293 US7204743B2 (en) 2001-02-27 2003-11-07 Integrated circuit interconnect fabrication systems
US11672005 US20070128851A1 (en) 2001-01-05 2007-02-06 Fabrication of semiconductor interconnect structures

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US09795687 Continuation-In-Part US6953392B2 (en) 2001-01-05 2001-02-27 Integrated system for processing semiconductor wafers

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US09795687 Continuation-In-Part US6953392B2 (en) 2001-01-05 2001-02-27 Integrated system for processing semiconductor wafers
US11672005 Division US20070128851A1 (en) 2001-01-05 2007-02-06 Fabrication of semiconductor interconnect structures

Publications (2)

Publication Number Publication Date
US20030032373A1 true US20030032373A1 (en) 2003-02-13
US7172497B2 true US7172497B2 (en) 2007-02-06

Family

ID=38119338

Family Applications (2)

Application Number Title Priority Date Filing Date
US10264726 Active 2021-07-25 US7172497B2 (en) 2001-01-05 2002-10-03 Fabrication of semiconductor interconnect structures
US11672005 Abandoned US20070128851A1 (en) 2001-01-05 2007-02-06 Fabrication of semiconductor interconnect structures

Family Applications After (1)

Application Number Title Priority Date Filing Date
US11672005 Abandoned US20070128851A1 (en) 2001-01-05 2007-02-06 Fabrication of semiconductor interconnect structures

Country Status (1)

Country Link
US (2) US7172497B2 (en)

Cited By (65)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050016861A1 (en) * 2003-07-24 2005-01-27 Thomas Laursen Method for planarizing a work piece
US20090280648A1 (en) * 2008-05-09 2009-11-12 Cyprian Emeka Uzoh Method and apparatus for 3d interconnect
US20100270626A1 (en) * 2009-04-27 2010-10-28 Raisanen Petri I Atomic layer deposition of hafnium lanthanum oxides
US20120086537A1 (en) * 2010-10-07 2012-04-12 Touch Micro-System Technology Corp. Planar coil and method of making the same
US8728832B2 (en) 2012-05-07 2014-05-20 Asm Ip Holdings B.V. Semiconductor device dielectric interface layer
US8802201B2 (en) 2009-08-14 2014-08-12 Asm America, Inc. Systems and methods for thin-film deposition of metal oxides using excited nitrogen-oxygen species
US8877655B2 (en) 2010-05-07 2014-11-04 Asm America, Inc. Systems and methods for thin-film deposition of metal oxides using excited nitrogen-oxygen species
US8883270B2 (en) 2009-08-14 2014-11-11 Asm America, Inc. Systems and methods for thin-film deposition of metal oxides using excited nitrogen—oxygen species
US8894870B2 (en) 2013-02-01 2014-11-25 Asm Ip Holding B.V. Multi-step method and apparatus for etching compounds containing a metal
US8933375B2 (en) 2012-06-27 2015-01-13 Asm Ip Holding B.V. Susceptor heater and method of heating a substrate
US8946830B2 (en) 2012-04-04 2015-02-03 Asm Ip Holdings B.V. Metal oxide protective layer for a semiconductor device
US8986456B2 (en) 2006-10-10 2015-03-24 Asm America, Inc. Precursor delivery system
US8993054B2 (en) 2013-07-12 2015-03-31 Asm Ip Holding B.V. Method and system to reduce outgassing in a reaction chamber
US9005539B2 (en) 2011-11-23 2015-04-14 Asm Ip Holding B.V. Chamber sealing member
US9018111B2 (en) 2013-07-22 2015-04-28 Asm Ip Holding B.V. Semiconductor reaction chamber with plasma capabilities
US9017481B1 (en) 2011-10-28 2015-04-28 Asm America, Inc. Process feed management for semiconductor substrate processing
US9021985B2 (en) 2012-09-12 2015-05-05 Asm Ip Holdings B.V. Process gas management for an inductively-coupled plasma deposition reactor
US9029253B2 (en) 2012-05-02 2015-05-12 Asm Ip Holding B.V. Phase-stabilized thin films, structures and devices including the thin films, and methods of forming same
US9096931B2 (en) 2011-10-27 2015-08-04 Asm America, Inc Deposition valve assembly and method of heating the same
US9117866B2 (en) 2012-07-31 2015-08-25 Asm Ip Holding B.V. Apparatus and method for calculating a wafer position in a processing chamber under process conditions
US9167625B2 (en) 2011-11-23 2015-10-20 Asm Ip Holding B.V. Radiation shielding for a substrate holder
US9169975B2 (en) 2012-08-28 2015-10-27 Asm Ip Holding B.V. Systems and methods for mass flow controller verification
US9202727B2 (en) 2012-03-02 2015-12-01 ASM IP Holding Susceptor heater shim
US9240412B2 (en) 2013-09-27 2016-01-19 Asm Ip Holding B.V. Semiconductor structure and device and methods of forming same using selective epitaxial process
US9324811B2 (en) 2012-09-26 2016-04-26 Asm Ip Holding B.V. Structures and devices including a tensile-stressed silicon arsenic layer and methods of forming same
US9341296B2 (en) 2011-10-27 2016-05-17 Asm America, Inc. Heater jacket for a fluid line
US9396934B2 (en) 2013-08-14 2016-07-19 Asm Ip Holding B.V. Methods of forming films including germanium tin and structures and devices including the films
US9394608B2 (en) 2009-04-06 2016-07-19 Asm America, Inc. Semiconductor processing reactor and components thereof
US9404587B2 (en) 2014-04-24 2016-08-02 ASM IP Holding B.V Lockout tagout for semiconductor vacuum valve
US9447498B2 (en) 2014-03-18 2016-09-20 Asm Ip Holding B.V. Method for performing uniform processing in gas system-sharing multiple reaction chambers
US9455138B1 (en) 2015-11-10 2016-09-27 Asm Ip Holding B.V. Method for forming dielectric film in trenches by PEALD using H-containing gas
US9478415B2 (en) 2015-02-13 2016-10-25 Asm Ip Holding B.V. Method for forming film having low resistance and shallow junction depth
US9484191B2 (en) 2013-03-08 2016-11-01 Asm Ip Holding B.V. Pulsed remote plasma method and system
US9543180B2 (en) 2014-08-01 2017-01-10 Asm Ip Holding B.V. Apparatus and method for transporting wafers between wafer carrier and process tool under vacuum
US9556516B2 (en) 2013-10-09 2017-01-31 ASM IP Holding B.V Method for forming Ti-containing film by PEALD using TDMAT or TDEAT
US9558931B2 (en) 2012-07-27 2017-01-31 Asm Ip Holding B.V. System and method for gas-phase sulfur passivation of a semiconductor surface
US9589770B2 (en) 2013-03-08 2017-03-07 Asm Ip Holding B.V. Method and systems for in-situ formation of intermediate reactive species
US9607837B1 (en) 2015-12-21 2017-03-28 Asm Ip Holding B.V. Method for forming silicon oxide cap layer for solid state diffusion process
US9605343B2 (en) 2013-11-13 2017-03-28 Asm Ip Holding B.V. Method for forming conformal carbon films, structures conformal carbon film, and system of forming same
US9627221B1 (en) 2015-12-28 2017-04-18 Asm Ip Holding B.V. Continuous process incorporating atomic layer etching
US9640416B2 (en) 2012-12-26 2017-05-02 Asm Ip Holding B.V. Single-and dual-chamber module-attachable wafer-handling chamber
US9647114B2 (en) 2015-08-14 2017-05-09 Asm Ip Holding B.V. Methods of forming highly p-type doped germanium tin films and structures and devices including the films
US9659799B2 (en) 2012-08-28 2017-05-23 Asm Ip Holding B.V. Systems and methods for dynamic semiconductor process scheduling
US9657845B2 (en) 2014-10-07 2017-05-23 Asm Ip Holding B.V. Variable conductance gas distribution apparatus and method
US9711345B2 (en) 2015-08-25 2017-07-18 Asm Ip Holding B.V. Method for forming aluminum nitride-based film by PEALD
US9735024B2 (en) 2015-12-28 2017-08-15 Asm Ip Holding B.V. Method of atomic layer etching using functional group-containing fluorocarbon
US9754779B1 (en) 2016-02-19 2017-09-05 Asm Ip Holding B.V. Method for forming silicon nitride film selectively on sidewalls or flat surfaces of trenches
US9793148B2 (en) 2011-06-22 2017-10-17 Asm Japan K.K. Method for positioning wafers in multiple wafer transport
US9793135B1 (en) 2016-07-14 2017-10-17 ASM IP Holding B.V Method of cyclic dry etching using etchant film
US9793115B2 (en) 2013-08-14 2017-10-17 Asm Ip Holding B.V. Structures and devices including germanium-tin films and methods of forming same
US9812320B1 (en) 2016-07-28 2017-11-07 Asm Ip Holding B.V. Method and apparatus for filling a gap
US9859151B1 (en) 2016-07-08 2018-01-02 Asm Ip Holding B.V. Selective film deposition method to form air gaps
US9887082B1 (en) 2016-07-28 2018-02-06 Asm Ip Holding B.V. Method and apparatus for filling a gap
US9890456B2 (en) 2014-08-21 2018-02-13 Asm Ip Holding B.V. Method and system for in situ formation of gas-phase compounds
US9891521B2 (en) 2014-11-19 2018-02-13 Asm Ip Holding B.V. Method for depositing thin film
US9899405B2 (en) 2014-12-22 2018-02-20 Asm Ip Holding B.V. Semiconductor device and manufacturing method thereof
US9899291B2 (en) 2015-07-13 2018-02-20 Asm Ip Holding B.V. Method for protecting layer by forming hydrocarbon-based extremely thin film
US9905420B2 (en) 2015-12-01 2018-02-27 Asm Ip Holding B.V. Methods of forming silicon germanium tin films and structures and devices including the films
US9909214B2 (en) 2015-10-15 2018-03-06 Asm Ip Holding B.V. Method for depositing dielectric film in trenches by PEALD
US9916980B1 (en) 2016-12-15 2018-03-13 Asm Ip Holding B.V. Method of forming a structure on a substrate
US9960072B2 (en) 2015-09-29 2018-05-01 Asm Ip Holding B.V. Variable adjustment for precise matching of multiple chamber cavity housings
US10032628B2 (en) 2016-05-02 2018-07-24 Asm Ip Holding B.V. Source/drain performance through conformal solid state doping
US10043661B2 (en) 2015-07-13 2018-08-07 Asm Ip Holding B.V. Method for protecting layer by forming hydrocarbon-based extremely thin film
US10083836B2 (en) 2015-07-24 2018-09-25 Asm Ip Holding B.V. Formation of boron-doped titanium metal films with high work function
US10090316B2 (en) 2016-09-01 2018-10-02 Asm Ip Holding B.V. 3D stacked multilayer semiconductor memory using doped select transistor channel

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100395767B1 (en) * 2001-09-13 2003-08-21 삼성전자주식회사 Ferroelectric memory device and method of forming the same
US7202161B2 (en) * 2003-05-26 2007-04-10 Ebara Corporation Substrate processing method and apparatus

Citations (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5620578A (en) 1994-12-08 1997-04-15 Sony Corporation Sputtering apparatus having an on board service module
US5679059A (en) 1994-11-29 1997-10-21 Ebara Corporation Polishing aparatus and method
US5821168A (en) * 1997-07-16 1998-10-13 Motorola, Inc. Process for forming a semiconductor device
US5826129A (en) 1994-06-30 1998-10-20 Tokyo Electron Limited Substrate processing system
US5827110A (en) 1994-12-28 1998-10-27 Kabushiki Kaisha Toshiba Polishing facility
US5830045A (en) 1995-08-21 1998-11-03 Ebara Corporation Polishing apparatus
US5885138A (en) 1993-09-21 1999-03-23 Ebara Corporation Method and apparatus for dry-in, dry-out polishing and washing of a semiconductor device
US5954072A (en) 1997-01-24 1999-09-21 Tokyo Electron Limited Rotary processing apparatus
US5972110A (en) 1996-09-06 1999-10-26 Tokyo Electron Limited Resist processing system
EP0978867A2 (en) 1998-08-07 2000-02-09 Ushiodenki Kabushiki Kaisha Heating device of the light irradiation type and holding device therefor
US6059637A (en) * 1997-12-15 2000-05-09 Lsi Logic Corporation Process for abrasive removal of copper from the back surface of a silicon substrate
US6110011A (en) 1997-11-10 2000-08-29 Applied Materials, Inc. Integrated electrodeposition and chemical-mechanical polishing tool
US6122566A (en) 1998-03-03 2000-09-19 Applied Materials Inc. Method and apparatus for sequencing wafers in a multiple chamber, semiconductor wafer processing system
EP1037263A2 (en) 1999-03-05 2000-09-20 Applied Materials, Inc. Apparatus for electro-chemical deposition of copper with the capability of in-situ thermal annealing
US6132289A (en) 1998-03-31 2000-10-17 Lam Research Corporation Apparatus and method for film thickness measurement integrated into a wafer load/unload unit
US6176992B1 (en) 1998-11-03 2001-01-23 Nutool, Inc. Method and apparatus for electro-chemical mechanical deposition
US6224638B1 (en) 1996-10-21 2001-05-01 Applied Materials, Inc. Method and apparatus for scheduling wafer processing within a multiple chamber semiconductor wafer processing tool having a multiple blade robot
US6251759B1 (en) 1998-10-03 2001-06-26 Applied Materials, Inc. Method and apparatus for depositing material upon a semiconductor wafer using a transition chamber of a multiple chamber semiconductor wafer processing system
US6346479B1 (en) * 2000-06-14 2002-02-12 Advanced Micro Devices, Inc. Method of manufacturing a semiconductor device having copper interconnects
US6355153B1 (en) * 1999-09-17 2002-03-12 Nutool, Inc. Chip interconnect and packaging deposition methods and structures
US20020031985A1 (en) * 2000-07-28 2002-03-14 Applied Materials, Inc. Chemical mechanical polishing composition and process
US6368880B2 (en) 1999-10-21 2002-04-09 Applied Materials, Inc. Barrier applications for aluminum planarization
WO2002029861A2 (en) 2000-10-05 2002-04-11 Applied Materials, Inc. System architecture of semiconductor manufacturing equipment
US6409576B1 (en) 1999-07-26 2002-06-25 Ebara Corporation Polishing apparatus
US6409904B1 (en) 1998-12-01 2002-06-25 Nutool, Inc. Method and apparatus for depositing and controlling the texture of a thin film
US6413869B1 (en) * 2000-11-06 2002-07-02 Advanced Micro Devices, Inc. Dielectric protected chemical-mechanical polishing in integrated circuit interconnects
US6451697B1 (en) * 2000-04-06 2002-09-17 Applied Materials, Inc. Method for abrasive-free metal CMP in passivation domain
US6461225B1 (en) * 2000-04-11 2002-10-08 Agere Systems Guardian Corp. Local area alloying for preventing dishing of copper during chemical-mechanical polishing (CMP)
US6468022B1 (en) 2000-07-05 2002-10-22 Integrated Dynamics Engineering, Inc. Edge-gripping pre-aligner
US6494985B1 (en) 1998-11-06 2002-12-17 Ebara Corporation Method and apparatus for polishing a substrate
US6578853B1 (en) 2000-12-22 2003-06-17 Lam Research Corporation Chuck assembly for use in a spin, rinse, and dry module and methods for making and implementing the same
US6613200B2 (en) 2001-01-26 2003-09-02 Applied Materials, Inc. Electro-chemical plating with reduced thickness and integration with chemical mechanical polisher into a single platform
US6656842B2 (en) * 1999-09-22 2003-12-02 Applied Materials, Inc. Barrier layer buffing after Cu CMP
US20040007478A1 (en) * 1998-12-01 2004-01-15 Basol Bulent M. Electroetching system and process
US20040052930A1 (en) 2000-04-27 2004-03-18 Bulent Basol Conductive structure fabrication process using novel layered structure and conductive structure fabricated thereby for use in multi-level metallization
US6736929B2 (en) 2002-02-15 2004-05-18 Nutool, Inc. Distributed control system for semiconductor manufacturing equipment
US6857838B2 (en) 2002-03-25 2005-02-22 Tokyo Electron Limited Substrate processing system with positioning device and substrate positioning method

Family Cites Families (60)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US446864A (en) * 1891-02-24 Electric motor
US2965556A (en) * 1959-04-15 1960-12-20 Struers Chemiske Lab H Apparatus for the electro-mechanical polishing of surfaces
US3448023A (en) * 1966-01-20 1969-06-03 Hammond Machinery Builders Inc Belt type electro-chemical (or electrolytic) grinding machine
FR1585605A (en) * 1968-04-29 1970-01-30
US3595089A (en) * 1969-09-23 1971-07-27 Frank J Jirik Rotary grain sampler device
US3779887A (en) * 1972-03-14 1973-12-18 Sifco Ind Inc Vibratory applicator for electroplating solutions
US3959089A (en) * 1972-07-31 1976-05-25 Watts John Dawson Surface finishing and plating method
FR2288389B1 (en) * 1974-10-17 1982-04-23 Nat Res Dev
NL7510771A (en) * 1975-03-11 1976-09-14 Oxy Metal Industries Corp A method for the electrolytic deposition of copper from aqueous acidic electroplating baths.
GB2081742B (en) * 1980-07-17 1983-07-20 Rolls Royce Manufacture of articles having internal passages by electromachining
FI802444A (en) * 1980-08-05 1982-02-06 Outokumpu Oy Apparat Foer elektrolytisk Polering
US4610772A (en) * 1985-07-22 1986-09-09 The Carolinch Company Electrolytic plating apparatus
US5024735A (en) * 1989-02-15 1991-06-18 Kadija Igor V Method and apparatus for manufacturing interconnects with fine lines and spacing
US5171412A (en) * 1991-08-23 1992-12-15 Applied Materials, Inc. Material deposition method for integrated circuit manufacturing
JP3200468B2 (en) * 1992-05-21 2001-08-20 日本エレクトロプレイテイング・エンジニヤース株式会社 Wafer for plating apparatus
ES2137459T3 (en) * 1994-08-09 1999-12-16 Ontrak Systems Inc Polished linear method for the planarization of semiconductor wafers.
US5567300A (en) * 1994-09-02 1996-10-22 Ibm Corporation Electrochemical metal removal technique for planarization of surfaces
US5593344A (en) * 1994-10-11 1997-01-14 Ontrak Systems, Inc. Wafer polishing machine with fluid bearings and drive systems
US5516412A (en) * 1995-05-16 1996-05-14 International Business Machines Corporation Vertical paddle plating cell
US5755859A (en) * 1995-08-24 1998-05-26 International Business Machines Corporation Cobalt-tin alloys and their applications for devices, chip interconnections and packaging
KR100217006B1 (en) * 1995-10-17 1999-09-01 미따라이 하지메 Etching method, process for producing a semiconductor element using said etching method, and apparatus suitable for practicing said etching method
RU2077611C1 (en) * 1996-03-20 1997-04-20 Виталий Макарович Рябков Method and apparatus for treating surfaces
US5862605A (en) * 1996-05-24 1999-01-26 Ebara Corporation Vaporizer apparatus
US5933753A (en) * 1996-12-16 1999-08-03 International Business Machines Corporation Open-bottomed via liner structure and method for fabricating same
US5807165A (en) * 1997-03-26 1998-09-15 International Business Machines Corporation Method of electrochemical mechanical planarization
US5911619A (en) * 1997-03-26 1999-06-15 International Business Machines Corporation Apparatus for electrochemical mechanical planarization
US5930669A (en) * 1997-04-03 1999-07-27 International Business Machines Corporation Continuous highly conductive metal wiring structures and method for fabricating the same
JP3462970B2 (en) * 1997-04-28 2003-11-05 三菱電機株式会社 Plating apparatus and a plating processing method
US5833820A (en) * 1997-06-19 1998-11-10 Advanced Micro Devices, Inc. Electroplating apparatus
US6074546A (en) * 1997-08-21 2000-06-13 Rodel Holdings, Inc. Method for photoelectrochemical polishing of silicon wafers
WO1999016936A1 (en) * 1997-09-30 1999-04-08 Semitool, Inc. Electroplating system having auxiliary electrode exterior to main reactor chamber for contact cleaning operations
US6024857A (en) * 1997-10-08 2000-02-15 Novellus Systems, Inc. Electroplating additive for filling sub-micron features
JP3191759B2 (en) * 1998-02-20 2001-07-23 日本電気株式会社 A method of manufacturing a semiconductor device
US6004880A (en) * 1998-02-20 1999-12-21 Lsi Logic Corporation Method of single step damascene process for deposition and global planarization
US6218306B1 (en) * 1998-04-22 2001-04-17 Applied Materials, Inc. Method of chemical mechanical polishing a metal layer
US6143155A (en) * 1998-06-11 2000-11-07 Speedfam Ipec Corp. Method for simultaneous non-contact electrochemical plating and planarizing of semiconductor wafers using a bipiolar electrode assembly
US6395152B1 (en) * 1998-07-09 2002-05-28 Acm Research, Inc. Methods and apparatus for electropolishing metal interconnections on semiconductor devices
CN1180133C (en) * 1998-10-14 2004-12-15 法拉第技术公司 Electrodeposition of metals in smal recesses using modulated electric fields
US6709565B2 (en) * 1998-10-26 2004-03-23 Novellus Systems, Inc. Method and apparatus for uniform electropolishing of damascene ic structures by selective agitation
US6902659B2 (en) * 1998-12-01 2005-06-07 Asm Nutool, Inc. Method and apparatus for electro-chemical mechanical deposition
US6227950B1 (en) * 1999-03-08 2001-05-08 Speedfam-Ipec Corporation Dual purpose handoff station for workpiece polishing machine
US6251235B1 (en) * 1999-03-30 2001-06-26 Nutool, Inc. Apparatus for forming an electrical contact with a semiconductor substrate
JP3422731B2 (en) * 1999-07-23 2003-06-30 理化学研究所 Elid centerless grinding machine
US6224737B1 (en) * 1999-08-19 2001-05-01 Taiwan Semiconductor Manufacturing Company Method for improvement of gap filling capability of electrochemical deposition of copper
US6352623B1 (en) * 1999-12-17 2002-03-05 Nutool, Inc. Vertically configured chamber used for multiple processes
US6354916B1 (en) * 2000-02-11 2002-03-12 Nu Tool Inc. Modified plating solution for plating and planarization and process utilizing same
US6497800B1 (en) * 2000-03-17 2002-12-24 Nutool Inc. Device providing electrical contact to the surface of a semiconductor workpiece during metal plating
JP2001326201A (en) * 2000-05-16 2001-11-22 Ebara Corp Polishing device
US6645550B1 (en) * 2000-06-22 2003-11-11 Applied Materials, Inc. Method of treating a substrate
US6534116B2 (en) * 2000-08-10 2003-03-18 Nutool, Inc. Plating method and apparatus that creates a differential between additive disposed on a top surface and a cavity surface of a workpiece using an external influence
US6436267B1 (en) * 2000-08-29 2002-08-20 Applied Materials, Inc. Method for achieving copper fill of high aspect ratio interconnect features
US7220166B2 (en) * 2000-08-30 2007-05-22 Micron Technology, Inc. Methods and apparatus for electromechanically and/or electrochemically-mechanically removing conductive material from a microelectronic substrate
US7349090B2 (en) * 2000-09-20 2008-03-25 Kla-Tencor Technologies Corp. Methods and systems for determining a property of a specimen prior to, during, or subsequent to lithography
US6610190B2 (en) * 2000-11-03 2003-08-26 Nutool, Inc. Method and apparatus for electrodeposition of uniform film with minimal edge exclusion on substrate
US6936154B2 (en) * 2000-12-15 2005-08-30 Asm Nutool, Inc. Planarity detection methods and apparatus for electrochemical mechanical processing systems
US6653226B1 (en) * 2001-01-09 2003-11-25 Novellus Systems, Inc. Method for electrochemical planarization of metal surfaces
US6696358B2 (en) * 2001-01-23 2004-02-24 Honeywell International Inc. Viscous protective overlayers for planarization of integrated circuits
US6482656B1 (en) * 2001-06-04 2002-11-19 Advanced Micro Devices, Inc. Method of electrochemical formation of high Tc superconducting damascene interconnect for integrated circuit
KR20040032862A (en) * 2001-07-20 2004-04-17 누툴 인코포레이티드 Planar metal electroprocessing
US6848970B2 (en) * 2002-09-16 2005-02-01 Applied Materials, Inc. Process control in electrochemically assisted planarization

Patent Citations (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5885138A (en) 1993-09-21 1999-03-23 Ebara Corporation Method and apparatus for dry-in, dry-out polishing and washing of a semiconductor device
US5826129A (en) 1994-06-30 1998-10-20 Tokyo Electron Limited Substrate processing system
US5679059A (en) 1994-11-29 1997-10-21 Ebara Corporation Polishing aparatus and method
US5620578A (en) 1994-12-08 1997-04-15 Sony Corporation Sputtering apparatus having an on board service module
US5827110A (en) 1994-12-28 1998-10-27 Kabushiki Kaisha Toshiba Polishing facility
US5830045A (en) 1995-08-21 1998-11-03 Ebara Corporation Polishing apparatus
US5972110A (en) 1996-09-06 1999-10-26 Tokyo Electron Limited Resist processing system
US6224638B1 (en) 1996-10-21 2001-05-01 Applied Materials, Inc. Method and apparatus for scheduling wafer processing within a multiple chamber semiconductor wafer processing tool having a multiple blade robot
US5954072A (en) 1997-01-24 1999-09-21 Tokyo Electron Limited Rotary processing apparatus
US5821168A (en) * 1997-07-16 1998-10-13 Motorola, Inc. Process for forming a semiconductor device
US6110011A (en) 1997-11-10 2000-08-29 Applied Materials, Inc. Integrated electrodeposition and chemical-mechanical polishing tool
US6059637A (en) * 1997-12-15 2000-05-09 Lsi Logic Corporation Process for abrasive removal of copper from the back surface of a silicon substrate
US6122566A (en) 1998-03-03 2000-09-19 Applied Materials Inc. Method and apparatus for sequencing wafers in a multiple chamber, semiconductor wafer processing system
US6132289A (en) 1998-03-31 2000-10-17 Lam Research Corporation Apparatus and method for film thickness measurement integrated into a wafer load/unload unit
EP0978867A2 (en) 1998-08-07 2000-02-09 Ushiodenki Kabushiki Kaisha Heating device of the light irradiation type and holding device therefor
US6251759B1 (en) 1998-10-03 2001-06-26 Applied Materials, Inc. Method and apparatus for depositing material upon a semiconductor wafer using a transition chamber of a multiple chamber semiconductor wafer processing system
US6176992B1 (en) 1998-11-03 2001-01-23 Nutool, Inc. Method and apparatus for electro-chemical mechanical deposition
US6494985B1 (en) 1998-11-06 2002-12-17 Ebara Corporation Method and apparatus for polishing a substrate
US6409904B1 (en) 1998-12-01 2002-06-25 Nutool, Inc. Method and apparatus for depositing and controlling the texture of a thin film
US20040007478A1 (en) * 1998-12-01 2004-01-15 Basol Bulent M. Electroetching system and process
US20020153256A1 (en) * 1998-12-01 2002-10-24 Nutool, Inc. Method and apparatus for depositing and controlling the texture of a thin film
US6136163A (en) 1999-03-05 2000-10-24 Applied Materials, Inc. Apparatus for electro-chemical deposition with thermal anneal chamber
EP1037263A2 (en) 1999-03-05 2000-09-20 Applied Materials, Inc. Apparatus for electro-chemical deposition of copper with the capability of in-situ thermal annealing
US6409576B1 (en) 1999-07-26 2002-06-25 Ebara Corporation Polishing apparatus
US6355153B1 (en) * 1999-09-17 2002-03-12 Nutool, Inc. Chip interconnect and packaging deposition methods and structures
US6656842B2 (en) * 1999-09-22 2003-12-02 Applied Materials, Inc. Barrier layer buffing after Cu CMP
US6368880B2 (en) 1999-10-21 2002-04-09 Applied Materials, Inc. Barrier applications for aluminum planarization
US6451697B1 (en) * 2000-04-06 2002-09-17 Applied Materials, Inc. Method for abrasive-free metal CMP in passivation domain
US6461225B1 (en) * 2000-04-11 2002-10-08 Agere Systems Guardian Corp. Local area alloying for preventing dishing of copper during chemical-mechanical polishing (CMP)
US20040052930A1 (en) 2000-04-27 2004-03-18 Bulent Basol Conductive structure fabrication process using novel layered structure and conductive structure fabricated thereby for use in multi-level metallization
US6346479B1 (en) * 2000-06-14 2002-02-12 Advanced Micro Devices, Inc. Method of manufacturing a semiconductor device having copper interconnects
US6468022B1 (en) 2000-07-05 2002-10-22 Integrated Dynamics Engineering, Inc. Edge-gripping pre-aligner
US20020031985A1 (en) * 2000-07-28 2002-03-14 Applied Materials, Inc. Chemical mechanical polishing composition and process
WO2002029861A2 (en) 2000-10-05 2002-04-11 Applied Materials, Inc. System architecture of semiconductor manufacturing equipment
US6413869B1 (en) * 2000-11-06 2002-07-02 Advanced Micro Devices, Inc. Dielectric protected chemical-mechanical polishing in integrated circuit interconnects
US6578853B1 (en) 2000-12-22 2003-06-17 Lam Research Corporation Chuck assembly for use in a spin, rinse, and dry module and methods for making and implementing the same
US6613200B2 (en) 2001-01-26 2003-09-02 Applied Materials, Inc. Electro-chemical plating with reduced thickness and integration with chemical mechanical polisher into a single platform
US6736929B2 (en) 2002-02-15 2004-05-18 Nutool, Inc. Distributed control system for semiconductor manufacturing equipment
US6857838B2 (en) 2002-03-25 2005-02-22 Tokyo Electron Limited Substrate processing system with positioning device and substrate positioning method

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
U.S. Appl. No. 09/671,800; filed Sep. 28, 2000; Basol et al. (ASMNUT.043A).

Cited By (80)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050016861A1 (en) * 2003-07-24 2005-01-27 Thomas Laursen Method for planarizing a work piece
US8986456B2 (en) 2006-10-10 2015-03-24 Asm America, Inc. Precursor delivery system
US8076237B2 (en) 2008-05-09 2011-12-13 Asm America, Inc. Method and apparatus for 3D interconnect
US20090280648A1 (en) * 2008-05-09 2009-11-12 Cyprian Emeka Uzoh Method and apparatus for 3d interconnect
US9394608B2 (en) 2009-04-06 2016-07-19 Asm America, Inc. Semiconductor processing reactor and components thereof
US20100270626A1 (en) * 2009-04-27 2010-10-28 Raisanen Petri I Atomic layer deposition of hafnium lanthanum oxides
US8071452B2 (en) 2009-04-27 2011-12-06 Asm America, Inc. Atomic layer deposition of hafnium lanthanum oxides
US8802201B2 (en) 2009-08-14 2014-08-12 Asm America, Inc. Systems and methods for thin-film deposition of metal oxides using excited nitrogen-oxygen species
US8883270B2 (en) 2009-08-14 2014-11-11 Asm America, Inc. Systems and methods for thin-film deposition of metal oxides using excited nitrogen—oxygen species
US8877655B2 (en) 2010-05-07 2014-11-04 Asm America, Inc. Systems and methods for thin-film deposition of metal oxides using excited nitrogen-oxygen species
US20120086537A1 (en) * 2010-10-07 2012-04-12 Touch Micro-System Technology Corp. Planar coil and method of making the same
US8310328B2 (en) * 2010-10-07 2012-11-13 Touch Micro-System Technology Corp. Planar coil and method of making the same
US9793148B2 (en) 2011-06-22 2017-10-17 Asm Japan K.K. Method for positioning wafers in multiple wafer transport
US9341296B2 (en) 2011-10-27 2016-05-17 Asm America, Inc. Heater jacket for a fluid line
US9096931B2 (en) 2011-10-27 2015-08-04 Asm America, Inc Deposition valve assembly and method of heating the same
US9892908B2 (en) 2011-10-28 2018-02-13 Asm America, Inc. Process feed management for semiconductor substrate processing
US9017481B1 (en) 2011-10-28 2015-04-28 Asm America, Inc. Process feed management for semiconductor substrate processing
US9167625B2 (en) 2011-11-23 2015-10-20 Asm Ip Holding B.V. Radiation shielding for a substrate holder
US9340874B2 (en) 2011-11-23 2016-05-17 Asm Ip Holding B.V. Chamber sealing member
US9005539B2 (en) 2011-11-23 2015-04-14 Asm Ip Holding B.V. Chamber sealing member
US9202727B2 (en) 2012-03-02 2015-12-01 ASM IP Holding Susceptor heater shim
US8946830B2 (en) 2012-04-04 2015-02-03 Asm Ip Holdings B.V. Metal oxide protective layer for a semiconductor device
US9384987B2 (en) 2012-04-04 2016-07-05 Asm Ip Holding B.V. Metal oxide protective layer for a semiconductor device
US9029253B2 (en) 2012-05-02 2015-05-12 Asm Ip Holding B.V. Phase-stabilized thin films, structures and devices including the thin films, and methods of forming same
US9177784B2 (en) 2012-05-07 2015-11-03 Asm Ip Holdings B.V. Semiconductor device dielectric interface layer
US8728832B2 (en) 2012-05-07 2014-05-20 Asm Ip Holdings B.V. Semiconductor device dielectric interface layer
US8933375B2 (en) 2012-06-27 2015-01-13 Asm Ip Holding B.V. Susceptor heater and method of heating a substrate
US9299595B2 (en) 2012-06-27 2016-03-29 Asm Ip Holding B.V. Susceptor heater and method of heating a substrate
US9558931B2 (en) 2012-07-27 2017-01-31 Asm Ip Holding B.V. System and method for gas-phase sulfur passivation of a semiconductor surface
US9117866B2 (en) 2012-07-31 2015-08-25 Asm Ip Holding B.V. Apparatus and method for calculating a wafer position in a processing chamber under process conditions
US9659799B2 (en) 2012-08-28 2017-05-23 Asm Ip Holding B.V. Systems and methods for dynamic semiconductor process scheduling
US9169975B2 (en) 2012-08-28 2015-10-27 Asm Ip Holding B.V. Systems and methods for mass flow controller verification
US9021985B2 (en) 2012-09-12 2015-05-05 Asm Ip Holdings B.V. Process gas management for an inductively-coupled plasma deposition reactor
US10023960B2 (en) 2012-09-12 2018-07-17 Asm Ip Holdings B.V. Process gas management for an inductively-coupled plasma deposition reactor
US9605342B2 (en) 2012-09-12 2017-03-28 Asm Ip Holding B.V. Process gas management for an inductively-coupled plasma deposition reactor
US9324811B2 (en) 2012-09-26 2016-04-26 Asm Ip Holding B.V. Structures and devices including a tensile-stressed silicon arsenic layer and methods of forming same
US9640416B2 (en) 2012-12-26 2017-05-02 Asm Ip Holding B.V. Single-and dual-chamber module-attachable wafer-handling chamber
US9228259B2 (en) 2013-02-01 2016-01-05 Asm Ip Holding B.V. Method for treatment of deposition reactor
US8894870B2 (en) 2013-02-01 2014-11-25 Asm Ip Holding B.V. Multi-step method and apparatus for etching compounds containing a metal
US9589770B2 (en) 2013-03-08 2017-03-07 Asm Ip Holding B.V. Method and systems for in-situ formation of intermediate reactive species
US9484191B2 (en) 2013-03-08 2016-11-01 Asm Ip Holding B.V. Pulsed remote plasma method and system
US8993054B2 (en) 2013-07-12 2015-03-31 Asm Ip Holding B.V. Method and system to reduce outgassing in a reaction chamber
US9790595B2 (en) 2013-07-12 2017-10-17 Asm Ip Holding B.V. Method and system to reduce outgassing in a reaction chamber
US9412564B2 (en) 2013-07-22 2016-08-09 Asm Ip Holding B.V. Semiconductor reaction chamber with plasma capabilities
US9018111B2 (en) 2013-07-22 2015-04-28 Asm Ip Holding B.V. Semiconductor reaction chamber with plasma capabilities
US9396934B2 (en) 2013-08-14 2016-07-19 Asm Ip Holding B.V. Methods of forming films including germanium tin and structures and devices including the films
US9793115B2 (en) 2013-08-14 2017-10-17 Asm Ip Holding B.V. Structures and devices including germanium-tin films and methods of forming same
US9240412B2 (en) 2013-09-27 2016-01-19 Asm Ip Holding B.V. Semiconductor structure and device and methods of forming same using selective epitaxial process
US9556516B2 (en) 2013-10-09 2017-01-31 ASM IP Holding B.V Method for forming Ti-containing film by PEALD using TDMAT or TDEAT
US9605343B2 (en) 2013-11-13 2017-03-28 Asm Ip Holding B.V. Method for forming conformal carbon films, structures conformal carbon film, and system of forming same
US9447498B2 (en) 2014-03-18 2016-09-20 Asm Ip Holding B.V. Method for performing uniform processing in gas system-sharing multiple reaction chambers
US9404587B2 (en) 2014-04-24 2016-08-02 ASM IP Holding B.V Lockout tagout for semiconductor vacuum valve
US9543180B2 (en) 2014-08-01 2017-01-10 Asm Ip Holding B.V. Apparatus and method for transporting wafers between wafer carrier and process tool under vacuum
US9890456B2 (en) 2014-08-21 2018-02-13 Asm Ip Holding B.V. Method and system for in situ formation of gas-phase compounds
US9657845B2 (en) 2014-10-07 2017-05-23 Asm Ip Holding B.V. Variable conductance gas distribution apparatus and method
US9891521B2 (en) 2014-11-19 2018-02-13 Asm Ip Holding B.V. Method for depositing thin film
US9899405B2 (en) 2014-12-22 2018-02-20 Asm Ip Holding B.V. Semiconductor device and manufacturing method thereof
US9478415B2 (en) 2015-02-13 2016-10-25 Asm Ip Holding B.V. Method for forming film having low resistance and shallow junction depth
US9899291B2 (en) 2015-07-13 2018-02-20 Asm Ip Holding B.V. Method for protecting layer by forming hydrocarbon-based extremely thin film
US10043661B2 (en) 2015-07-13 2018-08-07 Asm Ip Holding B.V. Method for protecting layer by forming hydrocarbon-based extremely thin film
US10083836B2 (en) 2015-07-24 2018-09-25 Asm Ip Holding B.V. Formation of boron-doped titanium metal films with high work function
US10087525B2 (en) 2015-08-04 2018-10-02 Asm Ip Holding B.V. Variable gap hard stop design
US9647114B2 (en) 2015-08-14 2017-05-09 Asm Ip Holding B.V. Methods of forming highly p-type doped germanium tin films and structures and devices including the films
US9711345B2 (en) 2015-08-25 2017-07-18 Asm Ip Holding B.V. Method for forming aluminum nitride-based film by PEALD
US9960072B2 (en) 2015-09-29 2018-05-01 Asm Ip Holding B.V. Variable adjustment for precise matching of multiple chamber cavity housings
US9909214B2 (en) 2015-10-15 2018-03-06 Asm Ip Holding B.V. Method for depositing dielectric film in trenches by PEALD
US9455138B1 (en) 2015-11-10 2016-09-27 Asm Ip Holding B.V. Method for forming dielectric film in trenches by PEALD using H-containing gas
US9905420B2 (en) 2015-12-01 2018-02-27 Asm Ip Holding B.V. Methods of forming silicon germanium tin films and structures and devices including the films
US9607837B1 (en) 2015-12-21 2017-03-28 Asm Ip Holding B.V. Method for forming silicon oxide cap layer for solid state diffusion process
US9627221B1 (en) 2015-12-28 2017-04-18 Asm Ip Holding B.V. Continuous process incorporating atomic layer etching
US9735024B2 (en) 2015-12-28 2017-08-15 Asm Ip Holding B.V. Method of atomic layer etching using functional group-containing fluorocarbon
US9754779B1 (en) 2016-02-19 2017-09-05 Asm Ip Holding B.V. Method for forming silicon nitride film selectively on sidewalls or flat surfaces of trenches
US10087522B2 (en) 2016-04-21 2018-10-02 Asm Ip Holding B.V. Deposition of metal borides
US10032628B2 (en) 2016-05-02 2018-07-24 Asm Ip Holding B.V. Source/drain performance through conformal solid state doping
US9859151B1 (en) 2016-07-08 2018-01-02 Asm Ip Holding B.V. Selective film deposition method to form air gaps
US9793135B1 (en) 2016-07-14 2017-10-17 ASM IP Holding B.V Method of cyclic dry etching using etchant film
US9812320B1 (en) 2016-07-28 2017-11-07 Asm Ip Holding B.V. Method and apparatus for filling a gap
US9887082B1 (en) 2016-07-28 2018-02-06 Asm Ip Holding B.V. Method and apparatus for filling a gap
US10090316B2 (en) 2016-09-01 2018-10-02 Asm Ip Holding B.V. 3D stacked multilayer semiconductor memory using doped select transistor channel
US9916980B1 (en) 2016-12-15 2018-03-13 Asm Ip Holding B.V. Method of forming a structure on a substrate

Also Published As

Publication number Publication date Type
US20030032373A1 (en) 2003-02-13 application
US20070128851A1 (en) 2007-06-07 application

Similar Documents

Publication Publication Date Title
US6184121B1 (en) Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same
US6004880A (en) Method of single step damascene process for deposition and global planarization
US6753249B1 (en) Multilayer interface in copper CMP for low K dielectric
US6319819B1 (en) Process for passivating top interface of damascene-type Cu interconnect lines
US6566250B1 (en) Method for forming a self aligned capping layer
US5969422A (en) Plated copper interconnect structure
US6566242B1 (en) Dual damascene copper interconnect to a damascene tungsten wiring level
US6395642B1 (en) Method to improve copper process integration
US6458696B1 (en) Plated through hole interconnections
US6245658B1 (en) Method of forming low dielectric semiconductor device with rigid, metal silicide lined interconnection system
US6010962A (en) Copper chemical-mechanical-polishing (CMP) dishing
US6346479B1 (en) Method of manufacturing a semiconductor device having copper interconnects
US6368484B1 (en) Selective plating process
US6518184B1 (en) Enhancement of an interconnect
US6080656A (en) Method for forming a self-aligned copper structure with improved planarity
US6340633B1 (en) Method for ramped current density plating of semiconductor vias and trenches
US6399486B1 (en) Method of improved copper gap fill
US6071809A (en) Methods for forming high-performing dual-damascene interconnect structures
US6242349B1 (en) Method of forming copper/copper alloy interconnection with reduced electromigration
US20020098681A1 (en) Reduced electromigration and stressed induced migration of Cu wires by surface coating
US6380083B1 (en) Process for semiconductor device fabrication having copper interconnects
US6297157B1 (en) Time ramped method for plating of high aspect ratio semiconductor vias and channels
US20070123039A1 (en) Electroless plating of metal caps for chalcogenide-based memory devices
US6350687B1 (en) Method of fabricating improved copper metallization including forming and removing passivation layer before forming capping film
US6056864A (en) Electropolishing copper film to enhance CMP throughput

Legal Events

Date Code Title Description
AS Assignment

Owner name: NUTOOL, INC., CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BASOL, BULENT;TALIEH, HOMAYOUN;REEL/FRAME:016351/0726

Effective date: 20021003

AS Assignment

Owner name: ASM NUTOOL, INC., CALIFORNIA

Free format text: CHANGE OF NAME;ASSIGNOR:NUTOOL, INC.;REEL/FRAME:016705/0440

Effective date: 20040729

AS Assignment

Owner name: NOVELLUS SYSTEMS, INC., CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ASM NUTOOL, INC.;REEL/FRAME:019000/0080

Effective date: 20061204

Owner name: NOVELLUS SYSTEMS, INC.,CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ASM NUTOOL, INC.;REEL/FRAME:019000/0080

Effective date: 20061204

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

MAFP

Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553)

Year of fee payment: 12