KR20100122701A - 반도체 소자의 제조방법 - Google Patents

반도체 소자의 제조방법 Download PDF

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KR20100122701A
KR20100122701A KR1020090041726A KR20090041726A KR20100122701A KR 20100122701 A KR20100122701 A KR 20100122701A KR 1020090041726 A KR1020090041726 A KR 1020090041726A KR 20090041726 A KR20090041726 A KR 20090041726A KR 20100122701 A KR20100122701 A KR 20100122701A
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film
forming
semiconductor device
etch stop
manufacturing
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KR1020090041726A
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김찬배
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주식회사 하이닉스반도체
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
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Abstract

본 발명은 기생 캐패시턴스의 증가를 방지할 수 있는 반도체 소자의 제조 방법을 개시한다. 개시된 본 발명에 따른 반도체 소자의 제조방법은, 반도체 기판 상부에 식각 정지막 및 희생막을 차례로 형성하는 단계와, 상기 식각 정지막이 노출되도록 상기 희생막을 식각하여 트렌치들을 형성하는 단계와, 상기 트렌치 측벽에 스페이서를 형성하는 단계와, 상기 스페이서로부터 노출된 식각 정지막 부분을 식각하는 단계와, 상기 스페이서를 포함한 트렌치들 내에 각각 금속배선을 형성하는 단계와, 상기 희생막을 제거하는 단계 및 상기 금속배선들을 포함하여 상기 식각 정지막 상에 절연막을 형성하되, 상기 금속배선들 사이의 절연막 부분에 에어-갭을 함께 형성하는 단계를 포함한다.

Description

반도체 소자의 제조방법{Method of manufacturing semiconductor device}
본 발명은 반도체 소자의 제조방법에 관한 것으로서, 보다 상세하게는, 기생 캐패시턴스 증가를 방지할 수 있는 반도체 소자의 제조 방법에 관한 것이다.
일반적으로, 반도체 소자에는 소자와 소자 간, 또는, 배선과 배선 간을 전기적으로 연결하기 위해 금속배선이 형성되며, 상부 금속배선과 하부 금속배선 간의 연결을 위해 콘택 플러그가 형성된다. 상기 금속배선의 재료로는 전기 전도도가 우수한 알루미늄(Al) 및 텅스텐(W)이 주로 이용되어 왔으나, 최근에는 알루미늄 및 텅스텐보다 전기 전도도가 우수하고 저항이 낮아 고집적 고속동작 소자에서 RC 신호 지연 문제를 해결할 수 있는 구리(Cu)를 차세대 금속배선 물질로 사용하고자 하는 연구가 진행되고 있다.
그런데, 상기 구리의 경우에 배선 형태로 식각하기가 용이하지 않기 때문에, 다마신(Damascene)이라는 새로운 공정 기술이 이용된다. 다마신 금속배선 공정은 층간 절연막을 식각해서 배선 형성 영역을 형성하고, 상기 배선 형성 영역을 구리막으로 매립하여 금속배선을 형성하는 기술이다.
한편, 반도체 소자의 고집적화가 진행함에 따라 콘택 저항을 비롯한 금속배 선의 저항이 점차 증가하게 되었다. 또한, 상기 금속배선 및 콘택 플러그 간의 간격이 좁아짐에 따라 금속배선을 절연시키는 절연막으로 인해 유발되는 기생 캐패시턴스가 증가하게 되었으며, 금속배선 간 공간의 매립 공정이 어려워지게 되었다.
이로 인해, 구리 배선의 형성 공정이 불안정하고, 기생 캐패시턴스의 증가로 인하여 소자의 동작에 문제가 발생되어 안정된 소자 특성을 얻지 못하게 된다.
본 발명은 기생 캐패시턴스의 증가를 방지할 수 있는 반도체 소자의 제조방법을 제공한다.
또한, 본 발명은 상기 기생 캐패시턴스의 증가를 방지하여 소자의 동작 속도를 향상시킬 수 있는 반도체 소자의 제조 방법을 제공한다.
본 발명의 실시예에 따른 반도체 소자의 제조방법은, 반도체 기판 상부에 식각 정지막 및 희생막을 차례로 형성하는 단계와, 상기 식각 정지막이 노출되도록 상기 희생막을 식각하여 트렌치들을 형성하는 단계와, 상기 트렌치 측벽에 스페이서를 형성하는 단계와, 상기 스페이서로부터 노출된 식각 정지막 부분을 식각하는 단계와, 상기 스페이서를 포함한 트렌치들 내에 각각 금속배선을 형성하는 단계와, 상기 희생막을 제거하는 단계 및 상기 금속배선들을 포함하여 상기 식각 정지막 상에 절연막을 형성하되, 상기 금속배선들 사이의 절연막 부분에 에어-갭을 함께 형성하는 단계를 포함한다.
여기서, 상기 식각 정지막은 산화막으로 형성한다.
상기 희생막은 비정질 카본막으로 형성한다.
상기 스페이서는 산화막으로 형성한다.
본 발명의 실시예에 따른 반도체 소자의 제조방법은, 상기 금속배선들을 형성하는 단계 전에, 상기 스페이서를 포함한 트렌치의 표면 상에 베리어막을 형성하는 단계를 더 포함한다.
상기 베리어막은 Ti막, TiN막, Ta막 및 TaN막 중 어느 하나 이상으로 형성한다.
본 발명의 실시예에 따른 반도체 소자의 제조방법은, 상기 희생막을 제거하는 단계에서, 상기 희생막은 습식 방식을 통해 제거한다.
상기 습식 방식은 SPM(Sulfuric acid-peroxide mixture) 용액을 이용하여 수행한다.
상기 절연막은 산화막으로 형성한다.
상기 절연막은 PE-CVD(Plasma enhanced-Chemical vapor deposition) 공정을 통해 형성한다.
상기 절연막은 에어-갭이 형성되도록 1∼3mTorr의 압력에서 형성한다.
본 발명은 금속배선을 절연시키는 절연막을 형성함과 동시에 상기 금속배선을 이용하여 에어-갭을 형성한다. 이렇게 하면, 상기 에어-갭을 형성하기 위해 추가적으로 후속 공정을 수행할 필요가 없어 공정 시간을 단축시킬 수 있을 뿐만 아 니라, 배선의 형성 공정을 안정화시킬 수 있다.
또한, 본 발명은 상기 에어-갭을 형성함으로써, 기생 캐패시턴스의 증가를 방지하여 소자의 동작 속도를 향상시킬 수 있다.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다.
도 1a 내지 1g는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위해 도시한 공정별 단면도로서, 이를 설명하면 다음과 같다.
도 1a를 참조하면, 배선 형성 영역을 갖는 반도체 기판(100) 상부에 식각 정지막(102) 및 희생막(104)을 차례로 형성한다. 상기 식각 정지막(102)은 산화막으로 형성하며, 상기 희생막(104)은 비정질 카본막으로 형성한다.
도 1b를 참조하면, 상기 희생막(104) 상에 배선 형성 영역을 노출시키는 마스크 패턴(도시안됨)을 형성한 후, 상기 마스크 패턴을 이용해서 상기 식각 정지막(102)이 노출되도록 상기 희생막(104)을 식각하여 트렌치(T)들을 형성한다.
도 1c를 참조하면, 상기 트렌치(T)들을 포함한 희생막(104) 및 식각 정지막(102) 상에 캡핑막(105)을 형성한다. 상기 캡핑막(105)은 산화막으로 형성한다.
도 1d를 참조하면, 상기 식각 정지막(102) 및 희생막(104)이 노출되도록 상기 캡핑막을 식각하여 상기 트렌치(T)들을 포함한 희생막(104)의 측면에 스페이서(S)를 형성한다. 그런 다음, 상기 반도체 기판(100)의 배선 형성 영역이 노출되도록 상기 스페이서(S)를 이용하여 노출된 상기 식각 정지막을 식각한다. 여기서, 상기 스페이서(S)는 상기 희생막(104)을 제거하기 위한 후속 공정시 배선 형성 영역에 형성될 후속하는 금속배선의 손실을 최소화하기 위하여 형성한다.
도 1e를 참조하면, 상기 배선 형성 영역을 노출시키는 상기 트렌치(T)들을 포함한 반도체 기판(100) 상에 베리어막(도시안됨) 및 금속막(도시안됨)을 형성한 후, 상기 희생막(104)이 노출될 때까지 이들을 CMP(Chemical mechanical polishing)하여 상기 트렌치(H)들 내에 각각 금속배선(106)을 형성한다. 여기서, 상기 베리어막은 Ti막, TiN막, Ta막 또는 TaN막의 단일막으로 형성할 수 있으며, 이와 다르게, Ti막과 TiN막의 적층막으로 형성하거나, 또는 Ta막과 TaN막의 적층막으로 형성할 수 있다.
한편, 상기 금속배선(106)을 형성하기 위한 상기 CMP 공정시, 상기 희생막(104)의 측면에만 상기 스페이서(S)가 형성되기 때문에, 상기 희생막(104)의 상면을 식각 정지막으로 사용할 수 있다. 그래서, 상기 금속배선(106)을 형성하기 위한 공정의 안정성을 확보할 수 있다.
도 1f를 참조하면, 상기 희생막을 H2SO4와 H2O2가 혼합된 SPM(Sulfuric acid-peroxide mixture) 식각액을 이용한 습식 방식을 통하여 제거한다. 상기 금속배선(106)들을 포함하여 상기 희생막이 제거된 반도체 기판(100)의 결과물 전면 상에 산화막으로 이루어진 절연막(108)을 형성한다.
여기서, 상기 절연막(108)은 PE-CVD(Plasma enhanced-Chemical vapor deposition) 공정, 또는, 스핀 공정을 이용하여 1∼3mTorr의 압력에서 형성하며, 상기 PE-CVD 공정을 이용하여 상기 절연막(108)을 형성할 경우. 예를 들어, 스텝 커버리지가 일반적으로 70% 정도되기 때문에, 상기 이웃하는 금속배선(106)들의 서로 대향하는 상부에 각각 만곡부, 즉, 오버행(Overhang)이 형성된다.
결과적으로, 상기 오버행에 의하여 상기 절연막(108) 형성시, 상기 금속배선(106)들 사이의 절연막(108) 내에 빈 공간인 에어-갭(A)을 형성할 수 있다.
도 1g를 참조하면, 상기 금속배선(106)이 노출되도록 상기 절연막(108)을 CMP한다.
이후, 공지된 일련의 후속 공정들을 차례로 수행하여 본 발명의 실시예에 따른 반도체 소자의 제조를 완성한다.
전술한 바와 같이, 본 발명은 금속배선을 절연시키는 절연막을 형성함과 동시에 상기 절연막이 상기 금속배선들의 서로 대향하는 상부에 오버행이 형성되도록 형성함으로써, 상기 오버행을 이용하여 상기 금속배선들 사이의 절연막 내에 에어-갭을 형성할 수 있다.
그래서, 본 발명은 상기 에어-갭을 형성하기 위해 추가적으로 후속 공정을 수행할 필요가 없어 공정 시간을 단축시킬 수 있을 뿐만 아니라, 배선의 형성 공정을 안정화시킬 수 있다. 그 결과, 본 발명은 기생 캐패시턴스의 증가를 방지하여 소자의 동작 속도를 향상시킬 수 있다.
이상, 여기에서는 본 발명을 특정 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다.
도 1a 내지 1g는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위해 도시한 공정별 단면도.
* 도면의 주요 부분에 대한 부호의 설명 *
100 : 반도체 기판 102 : 식각 정지막
104 : 희생막 T : 트렌치
105 : 캡핑막 S : 스페이서
106 : 금속배선 108 : 절연막
A : 에어-갭

Claims (11)

  1. 반도체 기판 상부에 식각 정지막 및 희생막을 차례로 형성하는 단계;
    상기 식각 정지막이 노출되도록 상기 희생막을 식각하여 트렌치들을 형성하는 단계;
    상기 트렌치 측벽에 스페이서를 형성하는 단계;
    상기 스페이서로부터 노출된 식각 정지막 부분을 식각하는 단계;
    상기 스페이서를 포함한 트렌치들 내에 각각 금속배선을 형성하는 단계;
    상기 희생막을 제거하는 단계; 및
    상기 금속배선들을 포함하여 상기 식각 정지막 상에 절연막을 형성하되, 상기 금속배선들 사이의 절연막 부분에 에어-갭을 함께 형성하는 단계;
    를 포함하는 반도체 소자의 제조방법.
  2. 제 1 항에 있어서,
    상기 식각 정지막은 산화막으로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.
  3. 제 1 항에 있어서,
    상기 희생막은 비정질 카본막으로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.
  4. 제 1 항에 있어서,
    상기 스페이서는 산화막으로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.
  5. 제 1 항에 있어서,
    상기 금속배선들을 형성하는 단계 전에,
    상기 스페이서를 포함한 트렌치의 표면 상에 베리어막을 형성하는 단계;
    를 더 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.
  6. 제 5 항에 있어서,
    상기 베리어막은 Ti막, TiN막, Ta막 및 TaN막 중 어느 하나 이상으로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.
  7. 제 1 항에 있어서,
    상기 희생막을 제거하는 단계에서, 상기 희생막은 습식 방식을 통해 제거하는 것을 특징으로 하는 반도체 소자의 제조방법.
  8. 제 7 항에 있어서,
    상기 습식 방식은 SPM(Sulfuric acid-peroxide mixture) 용액을 이용하여 수 행하는 것을 특징으로 하는 반도체 소자의 제조방법.
  9. 제 1 항에 있어서,
    상기 절연막은 산화막으로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.
  10. 제 1 항에 있어서,
    상기 절연막은 PE-CVD(Plasma enhanced-Chemical vapor deposition) 공정을 통해 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.
  11. 제 10 항에 있어서,
    상기 절연막은 에어-갭이 형성되도록 1∼3mTorr의 압력에서 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.
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