CN102655086B - 半导体器件的制造方法 - Google Patents

半导体器件的制造方法 Download PDF

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CN102655086B
CN102655086B CN201210053193.8A CN201210053193A CN102655086B CN 102655086 B CN102655086 B CN 102655086B CN 201210053193 A CN201210053193 A CN 201210053193A CN 102655086 B CN102655086 B CN 102655086B
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film
semiconductor device
manufacture method
plasma
treatment chamber
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CN102655086A (zh
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渡部诚一
佐藤学
成重和树
佐藤孝纪
胜沼隆幸
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Tokyo Electron Ltd
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Abstract

本发明提供半导体器件的制造方法和计算机存储介质。本发明提供一种半导体器件的制造方法，其蚀刻基板形成台阶状结构，上述基板具有：多层膜，交替叠层有第一介电常数的第一膜和与第一介电常数不同的第二介电常数的第二膜；和位于多层膜的上层作为蚀刻掩模发挥作用的光致抗蚀剂层，该半导体器件的制造方法，包括：第一工序，以光致抗蚀剂层为掩模，对第一膜进行等离子体蚀刻；第二工序，将光致抗蚀剂层暴露于含氢等离子体；第三工序，修整光致抗蚀剂层；和第四工序：以通过第三工序修整过的光致抗蚀剂层和在第一工序中进行了等离子体蚀刻的第一膜为掩模，蚀刻第二膜，通过反复进行第一工序至第四工序，使多层膜为台阶状结构。

Description

半导体器件的制造方法
技术领域
本发明涉及半导体器件的制造方法和计算机存储介质。
背景技术
目前，在半导体器件的制造工序中，进行使等离子体作用于半导体晶片等的基板上，实施蚀刻或成膜等处理的等离子体处理。在这样的半导体器件的制造工序例如NAND型闪存的制造工序中，已知有对介电常数不同的两种膜例如交替叠层有绝缘膜和导电膜的多层膜，进行等离子体蚀刻和掩模的修整(塑形)，形成台阶状结构(例如参照专利文献1)。
现有技术文献
专利文献1：日本特开2009－170661号公报
发明内容
发明想要解决的问题
如上述方式，在由介电常数不同的两种膜例如交替叠层有绝缘膜和导电膜的多层膜形成台阶状结构的半导体器件的制造工序中，存在如下问题：工序数多，制造效率差，并且由于堆积物的影响，难以形成多级形状良好的台阶状结构。
本发明是对应上述现有情况而完成的，提供能够高效地形成多级形状良好的台阶状结构的半导体器件的制造方法和计算机存储介质。
本发明的半导体器件的制造方法的一个方式，其蚀刻基板形成台阶状结构，上述基板具有：多层膜，交替叠层有具有第一介电常数的第一膜和具有与第一介电常数不同的第二介电常数的第二膜；和位于上述多层膜的上层作为蚀刻掩模发挥作用的光致抗蚀剂层，上述半导体器件的制造方法的特征在于，包括：第一工序，以上述光致抗蚀剂层为掩模，对上述第一膜进行等离子体蚀刻；第二工序，将上述光致抗蚀剂层暴露于含氢等离子体；第三工序，修整上述光致抗蚀剂层；和第四工序，以通过上述第三工序修整过的光致抗蚀剂层和在上述第一工序中进行了等离子体蚀刻的上述第一膜为掩模，蚀刻上述第二膜，通过反复进行上述第一工序至上述第四工序，使上述多层膜为台阶状结构。
发明效果
根据本发明，能够提供能够高效地形成多级形状良好的台阶状结构的半导体器件的制造方法和计算机存储介质。
附图说明
图1是示意性表示用于本发明的一个实施方式的等离子体处理装置的概略结构的图。
图2是示意性表示用于本发明的一个实施方式的半导体晶片的截面的概略结构的图。
图3是表示本发明的一个实施方式的工序的流程图。
图4表示SiF4的流量和修整比的关系。
符号说明
200……光致抗蚀剂膜
201……二氧化硅膜
202……多晶硅膜
210……叠层膜
W……半导体晶片
具体实施方式
以下，参照附图对本发明的实施方式进行说明。图1表示用于实施方式的半导体器件的制造方法的等离子体处理装置的结构。等离子体处理装置，具有：气密地构成，为电气接地电位的处理腔室1。
该处理腔室1呈圆筒状，例如由在表面形成有阳极氧化被膜的铝等构成。在处理腔室1内设置有载置台2，其大致水平地载置有作为被处理基板的半导体晶片W。该载置台2兼为下部电极，例如由铝等导电性材料构成，隔着绝缘板3被支承于导体的支承台4上。另外，在载置台2上的外周部分，以包围半导体晶片W的周围的方式设置有形成为环状的聚焦环5。
载置台2，经由第一匹配箱11a与第一高频电源10a连接，并经由第二匹配箱11b与第二高频电源l0b连接。从第一高频电源10a向载置台2供给规定频率(例如100MHz)的高频电力。另一方面，从第二高频电源10b向载置台2供给比第一高频电源10a低的规定频率(例如13.56MHz)的高频电力。
另一方面，与载置台2相对地在其上方以与载置台2平行相对的方式设置有喷淋头16，该喷淋头16为接地电位。所以，这些喷淋头16和载置台2作为一对相对电极(上部电极和下部电极)发挥作用。
在载置台2的上表面设置有用于静电吸附半导体晶片W的静电卡盘6。该静电卡盘6构成为在绝缘体6b之间夹有电极6a，电极6a与直流电源12连接。而且，通过从直流电源12向电极6a施加直流电压，由此通过库仑力等吸附半导体晶片W。
在载置台2的内部形成有未图示的冷却剂通道，能够使适合的冷却剂在其中循环来控制其温度。另外，载置台2与用于向半导体晶片W的背面侧供给氦气等背面气体(背面侧导热气体)的背面气体供给配管30a、30b连接，能够从背面气体供给源31向半导体晶片W的背面侧供给背面气体。此外，背面气体供给配管30a用于向半导体晶片W的中央部供给背面气体，背面气体供给配管30b用于向半导体晶片W的周缘部供给背面气体。通过这样的结构，能够将半导体晶片W控制在规定的温度。另外，在聚焦环5的外侧下方设置有排气环13。排气环13通过支承台4与处理腔室1导通。
以与载置台2相对的方式设置在处理腔室1的顶壁部分的喷淋头16上，在其下表面设置有多个排气孔18，且在喷淋头16的上部设置有气体导入部16a。而且，在喷淋头16的内部形成有空间17。气体导入部16a与气体供给配管15a连接，该气体供给配管15a的另一端与供给等离子体蚀刻用的气体(蚀刻气体)等的处理气体供给系统15连接。
从处理气体供给系统15供给的气体经由气体供给配管15a、气体导入部16a到达喷淋头16内部的空间17，从排气孔18向半导体晶片W排出。
在处理腔室1的下部形成有排气口19，该排气口19与排气系统20连接。而且，通过使设置于排气系统20上的真空泵工作，能够将处理腔室1内减压至规定的真空度。另一方面，在处理腔室1的侧壁上设置有打开和关闭半导体晶片W的搬入搬出口的闸阀24。
另一方面，在处理腔室1的周围呈同心状配置有环形磁铁21。该环形磁铁21由上侧环形磁铁21a和配置于该上侧环形磁铁21a的下侧的下侧环形磁铁21b构成，在载置台2和喷淋头16之间的空间中形成有规定的磁场。该环形磁铁21能够通过未图示的马达等的旋转机构进行旋转。
上述结构的等离子体处理装置通过控制部60来统一控制其动作。该控制部60具备：过程控制器61，具备CPU，控制等离子体处理装置的各部分；用户界面部62；和存储部63。
用户界面部62，包括：用于工序管理者管理等离子体处理装置而进行指令的输入操作的键盘；和将等离子体处理装置的工作状况进行可视化显示的显示器。
在存储部63收纳有方案，该方案存储有用于将在等离子体处理装置执行的各种处理通过过程控制器61的控制来实现的控制程序(软件)和处理条件数据等。而且，根据需要，通过利用来自用户界面部62的指示等从存储部63读出任意的处理程式，并通过过程控制器61对其进行执行，由此在过程控制器61的控制下，在等离子体处理装置上能够进行所期望的处理。控制程序或处理条件数据等的方案，可以利用收纳于通过计算机可读取的计算机存储介质(例如硬盘、CD、软磁盘、半导体存储器等)等中的状态的方案，或者也可以从其它装置经由例如专用线路随时传输并在线利用。
接着，说明利用上述结构的等离子体处理装置对半导体晶片W进行等离子体蚀刻的步骤。首先，打开闸阀24，通过未图示的输送机器人等将半导体晶片W经由未图示的加载闭锁真空室搬入处理腔室1内，载置于载置台2上。然后，使搬运机器人退避至处理腔室1外，关闭闸阀24。然后，利用排气系统20的真空泵，经由排气口19对处理腔室1内进行排气。
在处理腔室1内到达规定的真空度后，从处理气体供给系统15向处理腔室1内导入规定的处理气体，将处理腔室1内保持为规定的压力例如13.3Pa(100mTorr)，在该状态下从第一高频电源10a、第二高频电源10b向载置台2供给高频电力。此时，从直流电源12向静电卡盘6的电极6a施加规定的直流电压，半导体晶片W通过库仑力等向静电卡盘6吸附。
该情况下，通过如上述方式向作为下部电极的载置台2施加高频电力，在作为上部电极的喷淋头16和作为下部电极的载置台2之间形成有电场。另一方面，在作为上部电极的喷淋头16和作为下部电极的载置台2之间通过环形磁铁21形成有磁场，因此在半导体晶片W存在的处理空间中，由于电子的漂移而产生磁控管放电，通过由此形成的处理气体的等离子体的作用，对半导体晶片W实施规定的等离子体处理。
而且，当规定的等离子体处理结束时，停止高频电力的供给和处理气体的供给，按照与上述顺序相反的步骤，将半导体晶片W从处理腔室1内搬出。
然后，参照图2、图3，对本发明的半导体器件的制造方法的一个实施方式进行说明。图2示意性表示作为本实施方式的被处理基板的半导体晶片W的截面结构，表示本实施方式的工序，图3是表示本实施方式的工序的流程图。
如2(a)所示，半导体晶片W的最上部图案为规定形状，形成有作为掩模发挥功能的光致抗蚀剂膜200。该光致抗蚀剂膜200的厚度例如为5μm左右。在光致抗蚀剂膜200的下侧形成有作为绝缘膜的二氧化硅(SiO2)膜201a，在二氧化硅膜201a的下侧形成有作为导电膜的多晶硅膜(掺杂多晶硅膜)202a。
另外，在多晶硅膜202a的下侧形成有二氧化硅膜201b，在二氧化硅膜201b的下侧形成有多晶硅膜202b。这样，交替叠层有二氧化硅膜201和多晶硅膜202，构成叠层膜210。叠层膜210的叠层数量，例如二氧化硅膜201为32层，多晶硅膜202为32层，合计64层等。
此外，在本实施方式中，以叠层有二氧化硅(SiO2)膜和多晶硅膜(掺杂多晶硅膜)的叠层膜为例进行了说明，但作为叠层膜，能够适用于叠层有具有第一介电常数的第一膜和具有与第一介电常数不同的第二介电常数的第二膜的结构的叠层膜。更加具体地将，例如能够适用于：叠层二氧化硅膜和氮化硅膜而构成的叠层膜；叠层多晶硅膜和掺杂多晶硅膜而构成的叠层膜等。
从图2(a)所示的状态，首先，以光致抗蚀剂膜200为掩模，对二氧化硅膜201a进行等离子体蚀刻，使其成为图2(b)的状态(图3所示的工序301)。该等离子体蚀刻处理例如使用CF4+CHF3等处理气体的等离子体进行。
接着，进行用于除去由等离子体蚀刻产生的堆积物，特别是堆积在光致抗蚀剂膜200的侧壁部上的堆积物220的堆积物除去处理，使其成为图2(c)的状态(图3所示的工序302)。该堆积物除去处理例如使用O2+CF4等处理气体的等离子体进行。
接着，对光致抗蚀剂膜200的上表面进行改性的改性处理(固化)，在光致抗蚀剂膜200的上表面形成改性膜200a，使其成为图2(d)的状态(图3所述的工序303)。该改性处理(固化)通过将光致抗蚀剂膜200暴露在含氢的等离子体下进行。
接着，进行光致抗蚀剂膜200的修整(塑形)处理，扩大光致抗蚀剂膜200的开口面积。即，使光致抗蚀剂膜200的下侧的二氧化硅膜201a的局部露出，使其成为图2(e)的状态(图3所示的工序304)，该修整处理例如使用O2+N2等处理气体的等离子体进行。
接着，以光致抗蚀剂膜200和局部露出的二氧化硅膜201a为掩模，等离子体蚀刻二氧化硅膜201a的下侧的多晶硅膜202a，使其成为图2(f)的状态。(图3所示的工序305)。该等离子体蚀刻处理使用例如HBr+SF6+He等处理气体的等离子体进行。
通过上述的工序，形成第一级台阶形状。然后，将从上述二氧化硅膜201的等离子体蚀刻至多晶硅膜202的等离子体蚀刻的工序反复实施规定次数(图3所示的工序306)，形成规定级数的台阶状结构。
如上所述，在本实施方式中，在进行多晶硅膜202的等离子体蚀刻之前的工序中，进行光致抗蚀剂膜200的修整处理。这是因为，在刚刚进行了多晶硅膜202的等离子体蚀刻后，光致抗蚀剂膜200的侧壁等的堆积物的堆积量增大，不能容易地进行光致抗蚀剂膜200的修整。
例如当在进行了二氧化硅膜201的等离子体蚀刻之后，接着进行多晶硅膜202的等离子体蚀刻，然后进行光致抗蚀剂膜200的修整时，因向光致抗蚀剂膜200的侧壁等的多晶硅膜202的蚀刻导致的堆积的堆积物的堆积量增大，不能容易地进行光致抗蚀剂膜200的修整。
与此相对，如本实施方式的方式，通过在进行多晶硅膜202的等离子体蚀刻之前的工序中进行光致抗蚀剂膜200的修整处理，由此能够更加容易地以短时间进行大量的修整。
另外，当形成台阶状结构的下一个阶时，在多晶硅膜202的等离子体蚀刻之后，实施二氧化硅膜201的等离子体蚀刻和堆积物除去工序，所以同样能够更加容易地以短时间进行大量的修整。
另外，在本实施方式中，在修整处理前进行光致抗蚀剂膜200的上表面的改性处理，所以当修整处理时，能够控制光致抗蚀剂膜200的上表面被修整的量。所以，在修整处理中，光致抗蚀剂膜200的膜厚的减少(图2(e)所示的y)被抑制，光致抗蚀剂膜200的水平方向上的修整量(图2(e)所示的x)增多，能够减小修整比y/x。
作为实施例，使用图1所示的结构的等离子体处理装置，如图2所示，对交替叠层有作为绝缘膜的二氧化硅膜和作为导电膜的多晶硅膜的叠层膜，以下列处理条件进行处理，形成有台阶状结构。
(二氧化硅膜的蚀刻)
处理气体：CF4/CHF3＝175/25sccm
压力＝16.0Pa(120mTorr)
高频电力(高频率的高频/低频率的高频)：500W/200W
(堆积物除去)
处理气体：O2/CF4＝150/350sccm
压力：26.6Pa(200mTorr)
高频电力(高频率的高频/低频率的高频)：1500W/0W
(光致抗蚀剂膜的改性)
处理气体：H2/He＝300/500sccm
压力：2.66Pa(20mTorr)
高频电力(高频率的高频/低频率的高频)：300W/0W
(光致抗蚀剂膜的修整)
处理气体：O2/N2＝300/75sccm
压力：33.3Pa(250mTorr)
高频电力(高频率的高频/低频率的高频)：500W/0W
(多晶硅膜的蚀刻)
处理气体：HBr/SF6/He＝400/70/200sccm
压力：6.66Pa(50mTorr)
高频电力(高频率的高频/低频率的高频)：0W/500W
在多次反复实施上述工序后，当用电子显微镜放大观察半导体晶片W时，能够确认形成有形状良好的台阶状结构。
另外，上述修整工序中的修整比(y/x)为0.7左右。另一方面，作为比较例，对于在修整工序之前不进行光致抗蚀剂的改性的情况，测量修整比(y/x)，为1.6左右。所以，能够确认通过如本实施例的方式进行光致抗蚀剂的改性，能够大幅度改善修整比。此外，如上述方式，在光致抗蚀剂的改性中，作为处理气体使用H2/He的混合气体是因为当使用H2的单一气体进行光致抗蚀剂改性时，改性的效果过高，修整工序中的修整变得困难，通过增加He气体，能够抑制光致抗蚀剂的改性效果。
此外，在光致抗蚀剂的改性工序中能够使用的H2/He的流量比，在考虑改性效果和修整的操作容易度的基础上，能够在大概0～10％的范围内进行调整。另外，压力可以使用1.33～6.66Pa(10～50mT)的范围，压力越高，越能优化修整比，但与光致抗蚀剂层的侧壁的粗糙处于折衷选择(trade-off)的关系。进而，用于等离子体生成的高频电力的功率可以使用200～500W的范围，功率越高，越能优化修整比，但与光致抗蚀剂层的侧壁的粗糙处于折衷选择(trade-off)的关系。
另外，上述修整工序中的x方向上的修正量，当多次反复上述工序时，从第一次到第十次为300nm左右，大致固定。另一方面，在不进行堆积物除去的比较例中，第一次的x方向上的修正量为220nm左右，在第十次下降至180nm左右。所以，能够确认通过如本实施例的方式进行堆积物除去，能够增大x方向上的修正量，且当多次反复工序时，也能够获得稳定的x方向上的修整量。
在上述的光致抗蚀剂膜200的上表面的改性处理中，作为处理气体使用了H2气体和He气体的混合气体，但作为处理气体也能够使用H2气体、He气体和含硅气体(例如SiF4气体、SiCl4气体等)的混合气体。在使用这样的混合气体的情况下，除因H2气体的作用而发生的光致抗蚀剂的改性之外，还能够在光致抗蚀剂的表面形成硅酸盐碳(silicate carbon)等的涂层，由此能够减少修整比(y/x)。
图4的图表表示对SiF4气体流量与修整比的关系进行调查后的结果，其中纵轴为修整比(y/x)，横轴为SiF4气体流量。此外，该情况的光致抗蚀剂膜200的上表面的改性处理在以下条件下进行。
处理气体：H2/He/SiF4＝100/700/XXsccm
压力：20.0Pa(150mTorr)
高频电力(高频率的高频/低频率的高频)：300W/300W
如图4的图表所示，能够确认：当使SiF4气体的流量从0增加至20sccm时，修整比与SiF4的流量对应地降低。此外，为了获得使修整比降低的效果，需要流过某程度量的SiF4气体。另一方面，当过度增加SiF4气体流量时，虽然修整比降低，但光致抗蚀剂膜的修整速度也降低，用于获得希望的修整量的处理时间变长。因此，优选SiF4气体的流量对H2气体的流量比(SiF4气体流量/H2气体流量)在5～30％的范围内，进一步优选在10～20％的范围内。
另外，在上述实施方式和实施例中，对叠层膜210构成为包括作为绝缘膜的二氧化硅(SiO2)膜210a等和作为导电膜的多晶硅膜(掺杂多晶硅膜)202a等的情况进行了说明。但是，如上所述，也能够适用于介电常数不同的2种膜，例如叠层二氧化硅膜和氮化硅膜而构成的叠层膜、叠层多晶硅膜和掺杂多晶硅膜而构成的叠层膜等。
在该情况下，对于堆积物的除去、光致抗蚀剂上表面的改性、光致抗蚀剂的修整，能够与上述的实施例同样地进行。另外，对于蚀刻，在二氧化硅膜、多晶硅膜和掺杂多晶硅膜，也能够与上述的实施例同样地进行。对于氮化硅膜的蚀刻，例如能够使用CH2F2、CHF3、CF4、CH3F等的气体种类。更加具体地说，例如能够在
处理气体：CF4/CHF3＝25/175sccm
压力：16.0Pa(120mTorr)
高频电力(高频率的高频/低频率的高频)：500W/200W等的条件下进行氮化硅膜的蚀刻。
另外，本发明不限于上述实施方式和实施例，能够进行各种变形。例如，等离子体处理装置不限于图示的平行平板型的下部双频施加型，可以使用例如分别对上部电极和下部电极施加高频的类型的等离子体处理装置、或对下部电极施加单频的高频电力的类型的等离子体处理装置等各种离子体处理装置。

Claims (8)

1.一种半导体器件的制造方法，其在处理腔室内蚀刻基板形成台阶状结构，所述基板具有：多层膜，交替叠层有具有第一介电常数的第一膜和具有与第一介电常数不同的第二介电常数的第二膜；和位于所述多层膜的上层作为蚀刻掩模发挥作用的光致抗蚀剂层，所述半导体器件的制造方法的特征在于，包括：
第一工序，以所述光致抗蚀剂层为掩模，对暴露在所述处理腔室内的所述第一膜进行等离子体蚀刻，使层叠在被蚀刻的部分的所述第一膜之下的所述第二膜暴露在所述处理腔室内；
第二工序，将所述光致抗蚀剂层暴露于含氢等离子体；
第三工序，修整所述光致抗蚀剂层；和
第四工序，以通过所述第三工序修整过的光致抗蚀剂层和在所述第一工序中进行了等离子体蚀刻的所述第一膜为掩模，蚀刻暴露在所述处理腔室内的所述第二膜，使层叠在被蚀刻的部分的所述第二膜之下的所述第一膜暴露在所述处理腔室内，
通过反复进行所述第一工序至所述第四工序，使所述多层膜为台阶状结构。
2.如权利要求1所述的半导体器件的制造方法，其特征在于：
所述第一膜为绝缘膜，所述第二膜为导电膜。
3.如权利要求1所述的半导体器件的制造方法，其特征在于：
所述第一膜和所述第二膜为
二氧化硅膜和掺杂多晶硅膜、
二氧化硅膜和氮化硅膜、和
多晶硅膜和掺杂多晶硅膜中的任一者。
4.如权利要求1～3之任一项所述的半导体器件的制造方法，其特征在于：
在所述第一工序和所述第二工序之间，具备除去附着于所述光致抗蚀剂层上的堆积物的堆积物除去工序。
5.如权利要求1～3之任一项所述的半导体器件的制造方法，其特征在于：
在所述第二工序中使用氢气和氦气的混合气体的等离子体。
6.如权利要求1～3之任一项所述的半导体器件的制造方法，其特征在于：
在所述第二工序中使用氢气、氦气和含硅气体的混合气体的等离子体。
7.如权利要求5所述的半导体器件的制造方法，其特征在于：
在所述第二工序中，所述处理腔室内的压力调整为1.33～6.66Pa。
8.如权利要求1～3之任一项所述的半导体器件的制造方法，其特征在于：
所述第一膜和所述第二膜合计叠层64层以上。
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