TWI804573B - 基板處理之方法與系統 - Google Patents

基板處理之方法與系統 Download PDF

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TWI804573B
TWI804573B TW108104377A TW108104377A TWI804573B TW I804573 B TWI804573 B TW I804573B TW 108104377 A TW108104377 A TW 108104377A TW 108104377 A TW108104377 A TW 108104377A TW I804573 B TWI804573 B TW I804573B
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志方 劉
高明輝
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日商東京威力科創股份有限公司
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Abstract

呈現藉由多色圖案化技術之線切的方法及系統。在一實施例中，方法可包含提供基板。該方法亦可包含在基板上形成第一特徵部，該第一特徵部具有由第一材料形成的覆蓋物。此外，該方法可包含在基板上形成第二特徵部，該第二特徵部具有由第二材料形成的覆蓋物。在又進一步的實施例中，該方法可包含使用以第一蝕刻速率蝕刻第一材料及以第二蝕刻速率蝕刻第二材料的蝕刻製程選擇性地移除第二特徵部，其中第二蝕刻速率高於第一蝕刻速率。

Description

基板處理之方法與系統
本發明關於用於基板處理的系統及方法，且尤其關於藉由多色圖案化技術方法和系統的線切。
〔相關申請案〕本申請案係關於2018年2月7日申請之美國臨時專利申請案第62/627,572號並主張其優先權，其全部內容於此藉由參照納入本案揭示內容。
自對準多重圖案化(SAMP)技術已用於形成鰭式場效電晶體(FinFET)元件的構件等。尺寸收縮係發展積體電路處理的驅動力之一。藉由縮小大小尺寸，可獲得成本效益及元件性能提升。此可縮放性在製程流程中產生不可避免的複雜性，尤其是在圖案化技術上。SAMP技術已廣泛用於次30nm FinFET架構中，且其使用額外的間隔件蝕刻步驟以實現節距縮減要求。習知的SAMP流程具有幾個步驟，包含芯材蝕刻、間隔件沉積、間隔件蝕刻及芯材拉除。在此方法中，藉由間隔件沉積厚度及間隔件物理特徵(例如線邊緣粗糙度(LER)和線寬粗糙度(LWR))控制最終特徵部臨界尺寸(CD)。
在SAMP技術的一些應用中，可編輯某些線。舉例而言，圖1A-1E描繪用於習知線切方法的製程流程，其中將每第三條線移除。在習知的SAMP 方法之情形中，若干缺陷問題在線切製程期間出現，包含對剩餘線的損壞或欲切割之線的不完全移除。如圖1A-1E中所示，這些在次30nm方法下之缺陷問題的一原因係標準微影製程可能受限於邊緣放置誤差(EPE)，例如光阻圖案化與下方特徵部的未對準。
圖1A描繪在自對準四重圖案化(SAQP)製程之後接收到之基板的示例。在如此示例中，工件包含基板102，該基板102包含適用於微影製程基板的材料，例如Si、GaAs、玻璃等。為了此示例之目的，基板102可為矽。硬遮罩層104在基板102上形成。硬遮罩層104可為氧化物、氮化物等。間隔件106在硬遮罩層104的表面上形成。
在圖1B的步驟處，可使用例如深反應性離子蝕刻(DRIE)製程等蝕刻硬遮罩層104。由於硬遮罩蝕刻製程，可使基板102曝露。圖1C描繪進一步的蝕刻製程，其中基板102受蝕刻以在由硬遮罩層界定的圖案中形成特徵部。在基板蝕刻製程期間，可移除間隔件106。
在圖1D中所描繪的步驟處，可使用填充劑108填充特徵部，且可在其上形成微影堆疊。舉例而言，填充劑可為有機材料，例如旋塗碳(SOC)層或旋塗玻璃(SOG)層。微影堆疊可包含填充劑材料108及抗反射塗層110，例如SiARC、SiON等。微影堆疊亦可包含圖案化層112，其可由例如光阻之可圖案化材料形成。
圖1E中所描繪的線切製程說明關聯於習知方法的問題或議題。如圖所示，EPE問題可能導致線切製程與下方矽特徵部的未對準。舉例而言，欲切割之某些特徵部的部分可能如114處所示被保留，且欲保留的其他特徵部可能如116處所示在線切製程期間受到損壞。
呈現藉由多色圖案化技術之線切的方法及系統。在一實施例中，方法可包含提供基板。該方法亦可包含在基板上形成第一特徵部，該第一特徵部具有由第一材料形成的覆蓋物。此外，該方法可包含在基板上形成第二特徵部，該第二特徵部具有由第二材料形成的覆蓋物。在又進一步的實施例中，該方法可包含使用以第一蝕刻速率蝕刻第一材料及以第二蝕刻速率蝕刻第二材料的蝕刻製程選擇性地移除第二特徵部，其中第二蝕刻速率高於第一蝕刻速率。
102:基板
104:硬遮罩層
106:間隔件
108:填充劑/填充劑材料/填充劑層
110:抗反射塗層/抗反射層
112:圖案化層
200:系統
210:處理腔室
220:基板支架
221:靜電夾持系統
222:電極
225:晶圓
226:背側氣體供應系統
230:RF產生器
231:脈衝偏壓訊號控制器
232:阻抗匹配網路
240:氣體分配系統
245:處理區域
250:真空泵系統
255:來源控制器
270:上電極
272:RF產生器
274:阻抗匹配網路
290:氣體供應部
300:方法
302:步驟
304:步驟
306:步驟
308:步驟
402:第一間隔件材料層
404:間隔件芯材特徵部
406:特徵部
408:第二間隔件材料層
410:填充劑層
412:特徵部
414:部分
418:溝槽
420:剩餘特徵部
502:電子裝置
504:PCB
506:晶片封裝
結合在此說明書中並構成此說明書之一部分的隨附圖式，說明本發明的實施例，並連同以上提出之發明的一般性說明及以下提出之實施方式，用於描述本發明。
圖1A係描繪根據先前技術在習知線切製程中生產的工件之示例的示意橫剖面圖。
圖1B係描繪根據先前技術在習知線切製程中生產的工件之示例的示意橫剖面圖。
圖1C係描繪根據先前技術在習知線切製程中生產的工件之示例的示意橫剖面圖。
圖1D係描繪根據先前技術在習知線切製程中生產的工件之示例的示意橫剖面圖。
圖1E係描繪根據先前技術在習知線切製程中生產的工件之示例的示意橫剖面圖。
圖2係描繪配置成用於自對準多重圖案化方法及系統之原位間隔件再成形之電漿蝕刻系統之一實施例的示意方塊圖。
圖3係說明藉由多色圖案化技術之線切方法之一實施例的示意流程圖。
圖4A係描繪藉由多色圖案化技術之線切製程之一實施例的示意橫剖面圖。
圖4B係描繪藉由多色圖案化技術之線切製程之一實施例的示意橫剖面圖。
圖4C係描繪藉由多色圖案化技術之線切製程之一實施例的示意橫剖面圖。
圖4D係描繪藉由多色圖案化技術之線切製程之一實施例的示意橫剖面圖。
圖4E係描繪藉由多色圖案化技術之線切製程之一實施例的示意橫剖面圖。
圖4F係描繪藉由多色圖案化技術之線切製程之一實施例的示意橫剖面圖。
圖4G係描繪藉由多色圖案化技術之線切製程之一實施例的示意橫剖面圖。
圖4H係描繪藉由多色圖案化技術之線切製程之一實施例的示意橫剖面圖。
圖4I係描繪藉由多色圖案化技術之線切製程之一實施例的示意橫剖面圖。
圖4J係描繪藉由多色圖案化技術之線切製程之一實施例的示意橫剖面圖。
圖4K係描繪藉由多色圖案化技術之線切製程之一實施例的示意橫剖面圖。
圖5係描繪系統之一實施例的剖視圖，該系統具有藉由用於自對準多重圖案化之原位間隔件再成形之方法所形成的元件。
描述用於自對準多重圖案化之線切的方法及系統。然而，在相關技術領域中具有通常技術者將察知，諸多實施例可在無此等具體細節之其中一或更多者的情況下實施，或在具有其他替代者及/或額外的方法、材料、或元件的情況下實施。另一方面，眾所周知的結構、材料、或操作不再詳細顯示或描述，以避免模糊本發明之諸多實施例的實施態樣。
類似地，為了解釋之目的，闡述具體的數量、材料及構造以提供本發明的透徹理解。儘管如此，本發明可在無具體細節的情況下實施。此外，吾人應理解，圖式中顯示的諸多實施例係說明性的表示，且係未必按比例繪製。在所參照的圖式中，類似的數字似關於整篇說明書中類似的部件。
整份說明書提及「一個實施例」或「一實施例」或其變化，意味著關於該實施例所描述之特定的特徵、結構、材料、或特性包含在本發明的至少一個實施例中，但不表示上述特徵、結構、材料、或特性存在於每個實施例 中。因此，在整份說明書中各處出現例如「在一個實施例中」或「在一實施例中」之用語，未必指本發明的相同實施例。此外，在一或更多實施例中，特定的特徵、結構、材料、或特性可以任何適當的方式組合。諸多額外的層及/或結構可被包含在內，且/或所描述的特徵可在其他實施例中省略。
此外，應理解除非額外明確說明，否則「一」可表示「一或更多」。
諸多操作將以最有助於理解本發明的方式，以多個分立操作依次描述。然而，不應將所述之順序理解成暗示這些操作必定為順序相依。尤其，這些操作不需以敘述的順序執行。所述之操作可以不同於所述實施例的順序執行。在額外的實施例中，可執行諸多額外操作及/或可省略所述之操作。
如本文所使用，術語「基板」表示及包含材料形成於其上的基底材料或結構。應察知基板可包含單一材料、複數層不同材料、具有不同材料或不同結構之區域於其中的一或複數層等。這些材料可包含半導體、絕緣體、導體或其組合。舉例而言，基板可為半導體基板，在支撐結構上的基底半導體層，具有形成於其上之一或更多層、結構或區域的金屬電極或半導體基板。基板可為習知的矽基板或包含半導電性材料層的其他主體基板。如本文所使用，術語「主體基板」不僅表示及包含矽晶圓，亦表示及包含矽絕緣體(SOI)基板(例如矽藍寶石(SOS)基板及矽玻璃(SOG)基板)、在基底半導體基部上的矽磊晶層、及其他半導體或光電材料(例如：矽鍺、鍺、砷化鎵、氮化鎵、及磷化銦)。基板可經摻雜或未摻雜。
現參照圖式，其中類似的參考數字指定遍及若干視圖之相同或對應的部分。
圖2係用於自對準多重圖案化的線切之系統200的實施例。在又一實施例中，系統可配置成執行如參照圖3-4K所述之用於自對準多重圖案化的原位間隔件再成形。圖2中描繪配置成執行上述確定之製程條件的蝕刻及後熱處理系統200包含：處理腔室210；基板支架220，其上固定待處理的晶圓225；及真空泵系統250。晶圓225可為半導體基板、晶圓、平板顯示器、或液晶顯示器。處理腔室210可建構成在晶圓225的表面附近促進處理區域245的蝕刻。可離子化的氣體或處理氣體的混合物經由氣體分配系統240導入。對於處理氣體的給定流量而言，使用真空泵系統250調整製程壓力。
晶圓225可藉由夾持系統(例如機械夾持系統或電夾持系統(例如靜電夾持系統))(未顯示)固定至基板支架220。此外，基板支架220可包含加熱系統(未顯示)或冷卻系統(未顯示)，其係配置成調整及/或控制基板支架220及晶圓225的溫度。該加熱系統或冷卻系統可包含熱轉移流體的再循環流動，其在冷卻時自基板支架220接收熱並將熱轉移至熱交換器系統(未顯示)，或在加熱時自熱交換器系統將熱轉移至基板支架220。在其他實施例中，加熱/冷卻元件(例如電阻加熱元件或熱電加熱器/冷卻器)可被包含在基板支架220、以及處理腔室210的腔室壁和處理系統200內的任何其他構件中。
此外，熱轉移氣體可經由背側氣體供應系統226遞送至晶圓225的背側，以增進晶圓225與基板支架220間的氣體間隙熱傳導。當在升高或降低的溫度下需要晶圓225的溫度控制時，可利用如此系統。舉例而言，背側氣體供應系統可包含雙區氣體分配系統，其中氦氣間隙壓力可獨立地在晶圓225的中心與邊緣之間變化。
在顯示於圖2的實施例中，基板支架220可包含電極222，RF功率經由電極222耦合至處理區域245。舉例而言，可藉由將來自RF產生器230的RF功率經由選用性的阻抗匹配網路232傳送至基板支架220，而以RF電壓對基板支架220施以電偏壓。該RF電偏壓可用以加熱電子以形成及維持電漿。在此配置中，系統200可運作為反應性離子蝕刻(RIE)反應器，其中腔室及上部氣體噴射電極作為接地表面。
此外，RF電壓下之電極222的電偏壓可使用脈衝偏壓訊號控制器231脈衝輸送。舉例而言，自RF產生器230輸出的RF功率可在關閉狀態與開啟狀態之間脈衝輸送。或者，在複數頻率下將RF功率施加於基板支架電極。此外，阻抗匹配網路232可藉由減少反射的功率增進RF功率對處理腔室210內之電漿的傳送。匹配網路拓樸(例如L型、π型、T型等)及自動控制方法係為精於本項技術之人士所熟知。
氣體分配系統240可包含用於導入處理氣體混合物的噴淋頭設計。或者，氣體分配系統240可包含多區噴淋頭設計，該多區噴淋頭設計用於導入處理氣體混合物及調整晶圓225上方之處理氣體混合物的分布。舉例而言，多區噴淋頭設計可配置成：相對於流向晶圓225上方之實質上中心區域的處理氣體流或組成物的量，調整流向晶圓225上方之實質上周圍區域的處理氣體流或組成物。在如此實施例中，可以適當的組合分配氣體，以在處理腔室210之內形成高度均勻的電漿。
真空泵系統250可包含能夠高達約每秒8000公升(及更大)泵速度的渦輪分子真空泵(TMP)、及用於調節腔室壓力的閘閥。在用於乾電漿蝕刻的習知電漿處理裝置中，可使用每秒800至3000公升的TMP。對於一般小於約 50毫托的低壓處理而言，TMP係有用的。對於高壓處理(即大於約80毫托)而言，可使用機械升壓泵及乾粗抽泵。此外，用於監控腔室壓力的裝置(未顯示)可耦接至處理腔室210。
在一實施例中，來源控制器255可包含微處理器、記憶體、及可產生控制電壓的數位I/O埠，其足以傳輸及啟動對於處理系統200的輸入、以及監控來自電漿處理系統200的輸出。此外，來源控制器255可耦接至RF產生器230、脈衝偏壓訊號控制器231、阻抗匹配網路232、氣體分配系統240、氣體供應部290、真空泵系統250、以及基板加熱/冷卻系統(未顯示)、背側氣體供應系統226、及/或靜電夾持系統221，並可與以上元件交換資訊。舉例而言，儲存於記憶體中的程式可根據製程配方用以啟動對於處理系統200之前述元件的輸入，以在晶圓225上執行電漿輔助製程，例如電漿蝕刻製程或熱處理後製程。
此外，處理系統200可進一步包含上電極270，RF功率可從RF產生器272經由選用性的阻抗匹配網路274耦合至上電極270。在一實施例中，用於施加RF功率至上電極之的頻率可在約0.1MHz至約200MHz的範圍內。或者，本實施例可連接下列者而使用：感應耦合電漿(ICP)源；電容耦合電漿(CCP)源；輻射線槽孔天線(RLSA)源，其係配置成以GHz頻率範圍操作；電子迴旋共振(ECR)源，其係配置成以次GHz至GHz的範圍操作；及其他者。此外，用於施加功率至下電極之的頻率可在約0.1MHz至約80MHz的範圍內。此外，來源控制器255耦接至RF產生器272及阻抗匹配網路274，以控制對上電極270之RF功率的施加。上電極的設計及實施係為精於本項技術之人士所熟知。上電極270及氣體分配系統240可如圖所示設計成在相同的腔室組件之內。或者，上電極270 可包含多區電極設計，該多區電極設計用於調整耦合至晶圓225之上的電漿的RF功率分布。舉例而言，上電極270可區分為中心電極及邊緣電極。
依據應用，額外的裝置(例如感測器或計量裝置)可耦接至處理腔室210及來源控制器255，以收集即時資料及使用如此即時資料以在二或更多步驟中同時控制二或更多選定整合操作變數，該二或更多步驟涉及整合方案的沉積製程、RIE製程、拉除製程、輪廓重整製程、加熱處理製程、及/或圖案轉移製程。此外，相同的資料可用以確保達成包含下列者的整合目標：完成後熱處理、圖案化均勻性(均勻性)、結構的拉除(拉除)、結構的細窄化(細窄化)、結構的深寬比(深寬比)、線寬粗糙度、基板生產量、擁有成本等。
藉由調節所施加的功率(通常透過改變脈衝頻率及占空比)，可獲得與利用連續波(CW)產生的電漿特性明顯不同的電漿特性。因此，電極的RF功率調節可提供對時間平均離子通量及離子能量的控制。
圖3說明藉由多色圖案化技術之線切之方法300的一實施例。在一實施例中，方法300可包含提供基板，如步驟302所示。方法300亦可包含在基板內形成第一特徵部，該第一特徵部具有由第一材料形成的覆蓋物，如步驟304所示。此外，方法300可包含在基板內形成第二特徵部，該第二特徵部具有由第二材料形成的覆蓋物，如步驟306所示。方法300亦可包含使用以第一蝕刻速率蝕刻第一材料及以第二蝕刻速率蝕刻第二材料的蝕刻製程選擇性地移除第二材料，其中第二蝕刻速率高於第一蝕刻速率，如步驟308所示。
圖4A-4K描繪用於實施圖3之方法的實施例之製程流程的實施例。各圖表示可藉由製程流程中的處理步驟達成之實際結果的示例。如此製程流程 可用於製造半導體元件，例如MEMS元件。每一視圖係描繪可在例如晶圓225上形成的工件之一部分的橫剖面圖。
圖4A描繪其上可利用本實施例之工件的實施例。工件可包含例如基板102及硬遮罩層104。在一實施例中，可在硬遮罩層104上形成一或更多間隔件芯材特徵部404，且可在間隔件芯材特徵部404上形成第一間隔件材料層402。在一實施例中，第一間隔件材料層402可為氮化物材料。或者，第一間隔件材料層402可為氧化物材料。
在圖4B所描繪的處理步驟中，可回蝕第一間隔件材料層402以曝露間隔件芯材特徵部404。由於如此蝕刻製程，可形成一或更多特徵部406。在一實施例中，一或更多特徵部可為圍繞間隔件芯材特徵部404的間隔件。在諸多實施例中，使用電漿蝕刻氣體化學品執行蝕刻，取決於用於第一間隔件材料層402的材料，該電漿蝕刻氣體化學品可包含N2、O2、CO、CO2、H2、HBr、Cl2、CxHy、Ar、He、CxHyFz及CxFy的其中一或更多者。
在圖4C所描繪的處理步驟中，可在工件上形成第二間隔件材料層408。第二間隔件材料層408可不同於第一間隔件材料層402。更具體而言，若第一間隔件材料層402係氧化物材料，則第二間隔件材料層408可為氮化物材料，如TiN。或者，若第一間隔件材料層402係氮化物材料，則第二間隔件材料層408可為氧化物材料。無論針對第一間隔件材料層402選擇的材料為何，第二間隔件材料層408的材料可相對於第一間隔件材料層402為可選擇性地蝕刻。
在圖4D的處理步驟中，填充劑層410可沉積在工件的表面上。在一實施例中，填充劑層410可為氧化物材料。可在圖4E的步驟將填充劑層410回蝕至第二間隔件材料層408的表面。在替代的層中，可使用例如化學機械拋光 (CMP)製程移除填充劑層410的一部分。在圖4F的處理步驟中，可蝕去第二間隔件材料層408的一部分以形成特徵部412，該特徵部412的部分414可包含毗鄰硬遮罩層104設置的第二間隔件材料層408。在諸多實施例中，使用電漿蝕刻氣體化學品執行蝕刻，取決於用於第二間隔件材料層408的材料，該電漿蝕刻氣體化學品可包含N2、O2、CO、CO2、H2、HBr、Cl2、CxHy、Ar、He、CxHyFz及CxFy的其中一或更多者。
在圖4G的實施例中，可拉除間隔件芯材特徵部404。舉例而言，在一實施例中，間隔件芯材特徵部404可由矽、非晶矽、光阻或其組合形成。可使用選擇性地蝕刻間隔件芯材材料的蝕刻製程拉除間隔件芯材。
在圖4H的製程中，可在由特徵部406及特徵部412維持曝露的區域中蝕刻硬遮罩層104。在圖4I的製程中，可在由硬遮罩層104曝露的區域中蝕刻基板102。根據如此實施例，可在基板102的至少一部分內形成一或更多特徵部。
在圖4J的實施例中，製程包含形成填充劑層108。在一實施例中，填充劑層108可為旋塗有機物、旋塗碳或旋塗玻璃。抗反射層110亦可在填充劑層108上形成。圖案化層112亦可在抗反射層110上形成。在一實施例中，圖案化層112可包含具有在30nm至60nm範圍內之尺寸的特徵部。在一實施例中，圖案化層112可使毗鄰特徵部412的區域曝露。
在圖4K的處理步驟處，可拉除基板102的線特徵部，而在一或更多剩餘特徵部420之間留下溝槽418。在如此實施例中，用以形成溝槽418的蝕刻化學品配置成選擇性地蝕刻第二間隔件材料層408，同時以相對較慢的速率蝕刻第一間隔件材料層402，從而保留基板內在第一間隔件材料層402下方形成的特徵部。
表1中列出本文描述之諸多氣體的流率範圍。表1中的所有流率以每分鐘標準立方公分(sccm)測量。
Figure 108104377-A0305-02-0015-1
在一實施例中，表1中之氣體的腔室壓力範圍可為3mT~300mT。在一實施例中，由RF產生器272產生的高頻功率可為在0W~1500W的範圍內，而由電源230產生的低頻功率可為在0W~1000W的範圍內。在一實施例中，處理腔室210內的溫度可為在-10℃~110℃的範圍內。
此處描述的製程及方法之實施例可在商業製程中使用，以供製造商業產品中所包含之基於半導體的產品。舉例而言，圖5描繪包含印刷電路板(PCB)的電子裝置502。電子裝置502可為一些市售產品之一，例如包含電腦、電腦螢幕、電視機、音頻放大器、照相機、智慧型手機及個人數據助理、平板計算裝置、智慧型手錶、特殊應用處理設備、感測器裝置、醫療裝置等。在此技術領域具有通常知識者將察知，根據本發明實施例製造的裝置不限於任何特定領域。
電子裝置502可包含一或更多PCB 504，PCB 504包含一或更多基於半導體的電子元件，例如晶片封裝506。晶片封裝506可包含經分割之晶圓的晶片，其具有配置於其上的一或更多特徵部，例如根據圖3-4K中描述的製程製造的FinFET元件。晶片可包含例如基板102。晶片可被封裝在耐用封裝中，以供保護配置於其上的特徵部。晶片封裝506可進一步包含配置成對晶片上的某些接觸點提供外部通路的一或更多接觸銷。
有利的是，在晶片封裝506內之晶片上設置的特徵部之尺寸及密度可相對於使用其他技術製造的元件更小，因為鈍化處理及間隔件再成形處理的使用允許相對於先前方法之半導體元件的高解析度圖案化。
額外的優點及改良將輕易對在此技術領域具有通常技術者呈現。因此，本發明在其更廣實施態樣中不限於所顯示及描述的具體細節、代表性設備及方法、及說明性示例。因此，在不脫離本發明整體概念之範圍的情況下，可自如此細節作成變更。
300:方法
302:步驟
304:步驟
306:步驟
308:步驟

Claims (21)

  1. 一種基板處理的方法，該方法包含：提供基板；在該基板上形成芯材特徵部；在該基板上形成圍繞且接觸該芯材特徵部的第一材料之間隔件；在該芯材特徵部及該間隔件及該基板之一部分的各者上方形成第二材料之間隔件材料層；在該基板上形成與該間隔件間隔開的第二特徵部，該第二特徵部之一部分為該第二材料；及使用以第一蝕刻速率蝕刻該第一材料及以第二蝕刻速率蝕刻該第二材料的蝕刻製程，選擇性地移除包含係該第二材料的該部分之該第二特徵部，其中該第二蝕刻速率高於該第一蝕刻速率。
  2. 如申請專利範圍第1項之基板處理的方法，其中該第一材料包含氧化物材料。
  3. 如申請專利範圍第2項之基板處理的方法，其中該第二材料包含氮化物材料。
  4. 如申請專利範圍第1項之基板處理的方法，其中在形成該芯材特徵部之前，該方法更包含在該基板上形成硬遮罩層。
  5. 如申請專利範圍第4項之基板處理的方法，其中形成該芯材特徵部包含在該硬遮罩層上形成間隔件心軸。
  6. 如申請專利範圍第5項之基板處理的方法，其中形成該間隔件包含在該間隔件心軸及該硬遮罩層的曝露區域上形成一層該第一材料。
  7. 如申請專利範圍第6項之基板處理的方法，其中形成該間隔件包含回蝕該第一材料以曝露該硬遮罩層及該間隔件心軸的表面，而在毗鄰該間隔件心軸的該硬遮罩層上留下該間隔件。
  8. 如申請專利範圍第1項之基板處理的方法，其中形成該間隔件材料層之步驟形成凹部，並且其中形成該第二特徵部包含使用第二層該第一材料填充該凹部，該第二特徵部係由形成在該第二材料上之該第一材料所構成。
  9. 如申請專利範圍第8項之基板處理的方法，更包含移除該第二層該第一材料的一部分，以曝露在該間隔件心軸及該間隔件上之該間隔件材料層的表面。
  10. 如申請專利範圍第9項之基板處理的方法，更包含移除該間隔件材料層，以形成該第二特徵部，其中移除該間隔件材料層之步驟在該第一材料與該基板之間留下該第二材料之該部分。
  11. 如申請專利範圍第10項之基板處理的方法，更包含移除該間隔件與該第二特徵部之間之一或更多曝露區域內的該硬遮罩層，以曝露該基板的表面。
  12. 如申請專利範圍第11項之基板處理的方法，更包含移除該間隔件與該第二特徵部之間曝露的區域內之該基板的一部分。
  13. 如申請專利範圍第12項之基板處理的方法，更包含使用第三材料填充該基板之被移除的部分及該間隔件與該第二特徵部之間的空間。
  14. 如申請專利範圍第13項之基板處理的方法，更包含在該第三材料的表面上形成抗反射層。
  15. 如申請專利範圍第14項之基板處理的方法，更包含在該抗反射層的表面上形成圖案化層。
  16. 如申請專利範圍第15項之基板處理的方法，其中選擇性地移除該第二特徵部更包含在由該圖案化層維持曝露之該抗反射層的區域內蝕刻。
  17. 如申請專利範圍第16項之基板處理的方法，其中蝕刻該基板係使用包含選擇自由下列者組成之群組之電漿蝕刻氣體的電漿蝕刻氣體化學品執行：N2、O2、CO、CO2、H2、HBr、Cl2、CxHy、Ar、He、CxHyFz及CxFy，作成該選擇以選擇性地蝕刻該第二間隔件的材料且不蝕刻該第一間隔件的材料。
  18. 如申請專利範圍第1項之基板處理的方法，其中在形成該第二特徵部之後，該方法更包含自該基板移除該芯材特徵部，以在該基板上留下與該第二特徵部間隔開的該間隔件。
  19. 如申請專利範圍第18項之基板處理的方法，更包含移除該間隔件與該第二特徵部之間曝露的區域內之該基板的一部分，並且留下該第二材料之該第二特徵部之該部分。
  20. 一種基板處理的系統，該系統包含：離子蝕刻腔室，其係配置成：接收基板；在該基板之上形成芯材特徵部；在該基板上形成圍繞且接觸該芯材特徵部的第一材料之間隔件，其；在該芯材特徵部及該間隔件及該基板的一部分之各者上方形成第二材料之間隔件材料層；在該基板上形成與該間隔件間隔開的第二特徵部，該第二特徵部之一部分為該第二材料；及使用以第一蝕刻速率蝕刻該第一材料及以第二蝕刻速率蝕刻該第二材料的蝕刻製程選擇性地移除包含係該第二材料的該部分之該第二特徵部，其中該第二蝕刻速率高於該第一蝕刻速率。
  21. 一種基板處理方法，包含：提供其上具有硬遮罩層的基板；在該基板上形成第一特徵部，該第一特徵部具有由第一材料形成的覆蓋物； 在該基板上形成第二特徵部，該第二特徵部具有由第二材料形成的覆蓋物；及使用以第一蝕刻速率蝕刻該第一材料及以第二蝕刻速率蝕刻該第二材料的蝕刻製程，選擇性地移除該第二特徵部，其中該第二蝕刻速率高於該第一蝕刻速率，其中形成該第一特徵部包含在該硬遮罩層上形成間隔件心軸，形成該第一特徵部包含在該間隔件心軸及該硬遮罩層的曝露區域上形成一層該第一材料，形成該第一特徵部包含回蝕該第一材料以曝露該硬遮罩層及該間隔件心軸的表面，而在毗鄰該間隔件心軸的該硬遮罩層上留下第一間隔件，形成該第二特徵部包含在間隔件心軸、該第一間隔件、及該硬遮罩層上形成一層該第二材料，以及形成該第二特徵部包含使用第二層該第一材料填充在該層第二材料上方留下的凹部。
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