JP4427562B2 - パターン形成方法 - Google Patents
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- JP4427562B2 JP4427562B2 JP2007154484A JP2007154484A JP4427562B2 JP 4427562 B2 JP4427562 B2 JP 4427562B2 JP 2007154484 A JP2007154484 A JP 2007154484A JP 2007154484 A JP2007154484 A JP 2007154484A JP 4427562 B2 JP4427562 B2 JP 4427562B2
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 10
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- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
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- 238000000354 decomposition reaction Methods 0.000 description 2
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- 238000004519 manufacturing process Methods 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 125000006239 protecting group Chemical group 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3088—Process specially adapted to improve the resolution of the mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
Description
本発明の第1の実施形態に係るパターン形成方法を図2を用いて説明する。
本発明の第2の実施形態に係るパターン形成方法を図2及び図5を用いて説明する。
14…イオン注入層、15…RELACSパターン、16…BARC、
17…BARCのイオン注入層。
Claims (5)
- 被加工膜の上にパターン形成時の露光によって発生した酸を含んだレジストパターンを形成する工程と、
前記レジストパターンの上面にイオンを注入して前記レジストパターン中のイオンが注入された部分に存在する酸を失活させる工程と、
前記イオンの注入後に、前記レジストパターンを覆うように有機膜を形成する工程と、
前記有機膜を加熱することにより前記露光によって発生した酸を用いて前記有機膜を熱架橋させる工程と、
加熱後の前記有機膜を現像することにより、前記レジストパターンの側面に前記有機膜を熱架橋させた架橋樹脂膜を形成する工程と、
前記架橋樹脂膜の形成後に前記レジストパターンを除去する工程と、
前記架橋樹脂膜をマスクとして前記被加工膜を加工する工程と
を具備したことを特徴とするパターン形成方法。 - 被加工膜の上にパターン形成時の露光によって発生した酸を含んだレジストパターンを形成する工程と、
前記レジストパターンの一部の上面に選択的にイオンを注入して前記レジストパターン中のイオンが注入された部分に存在する酸を失活させる工程と、
前記イオンの注入後に、前記レジストパターンを覆うように有機膜を形成する工程と、
前記有機膜を加熱することにより前記露光によって発生した酸を用いて前記有機膜を熱架橋させる工程と、
加熱後の前記有機膜を現像することにより、イオン注入された前記レジストパターン部の側面とイオン注入されていない前記レジストパターン部の側面及び上面に前記有機膜を熱架橋させた架橋樹脂膜を形成する工程と、
前記架橋樹脂膜の形成後にイオン注入された前記レジストパターン部を除去する工程と、
前記架橋樹脂膜およびイオン注入されていないレジストパターンをマスクとして前記被加工膜を加工する工程と
を具備したことを特徴とするパターン形成方法。 - 前記レジストパターン又は前記架橋樹脂膜をスリミングする工程を更に含む
ことを特徴とする請求項1又は2に記載のパターン形成方法。 - 前記イオンはHe、Ne、Ar、Kr、N2の少なくとも一つを含むイオンである
ことを特徴とする請求項1又は2に記載のパターン形成方法。 - 前記レジストパターンを除去する工程は、アッシングによりレジストパターンを除去するものである
ことを特徴とする請求項1又は2に記載のパターン形成方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007154484A JP4427562B2 (ja) | 2007-06-11 | 2007-06-11 | パターン形成方法 |
US12/135,548 US20080305443A1 (en) | 2007-06-11 | 2008-06-09 | Pattern forming method using relacs process |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007154484A JP4427562B2 (ja) | 2007-06-11 | 2007-06-11 | パターン形成方法 |
Publications (2)
Publication Number | Publication Date |
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JP2008306144A JP2008306144A (ja) | 2008-12-18 |
JP4427562B2 true JP4427562B2 (ja) | 2010-03-10 |
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JP2007154484A Expired - Fee Related JP4427562B2 (ja) | 2007-06-11 | 2007-06-11 | パターン形成方法 |
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US (1) | US20080305443A1 (ja) |
JP (1) | JP4427562B2 (ja) |
Cited By (1)
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JP2003140362A (ja) * | 2001-11-02 | 2003-05-14 | Mitsubishi Electric Corp | レジストパターンの強化方法 |
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US6566280B1 (en) * | 2002-08-26 | 2003-05-20 | Intel Corporation | Forming polymer features on a substrate |
JP2004179254A (ja) * | 2002-11-25 | 2004-06-24 | Renesas Technology Corp | 半導体装置の製造方法 |
US6918624B2 (en) * | 2003-10-29 | 2005-07-19 | Ford Global Technologies, Llc | Vehicle tailgate with supplemental tailgate having a flip out step |
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