JP5768397B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP5768397B2 JP5768397B2 JP2011030987A JP2011030987A JP5768397B2 JP 5768397 B2 JP5768397 B2 JP 5768397B2 JP 2011030987 A JP2011030987 A JP 2011030987A JP 2011030987 A JP2011030987 A JP 2011030987A JP 5768397 B2 JP5768397 B2 JP 5768397B2
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- insulating film
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
- H10D64/01358—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being a Group III-V material
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
- H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
- H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
- H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
- H10D30/4755—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
- H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
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- Junction Field-Effect Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
図1は本発明の実施の形態1に係る半導体装置の製造方法を示すフローチャートである。本発明の実施の形態1に係る半導体装置の製造方法は図1に沿って説明する。まず、半導体層の表面に絶縁膜を形成する(ステップ10)。ステップ10は図2を参照して説明する。図2は半導体層32の表面に絶縁膜34を形成したことを示す図である。半導体層32は基板30の表面に形成する。基板30はSiCで形成し、半導体層32はGaN/AlGaNで形成する。そして、半導体層32の表面にSiNで絶縁膜34を形成する。
図11は本発明の実施の形態2に係る半導体装置の製造方法を示すフローチャートである。このフローチャートのうち、図1と同じ符号が付けられた工程は上述の通りであるため説明を省略する。
Claims (5)
- 半導体層の表面に絶縁膜を形成する工程と、
前記絶縁膜の表面に開口を有するレジストを形成する工程と、
前記レジストと架橋反応するパターンシュリンク剤を前記レジストに付着させ、前記レジストの内周に硬化層を形成する工程と、
前記レジスト及び前記硬化層をマスクとして前記絶縁膜をエッチングする工程と、
前記硬化層を除去する工程と、
前記半導体層、前記絶縁膜、及び前記レジストの表面に金属層を形成する工程と、
リフトオフ法により前記レジスト及び前記レジストの表面の前記金属層を除去する工程と、を備えたことを特徴とする半導体装置の製造方法。 - 前記レジストは感光により酸へ変化する材料で形成され、
前記硬化層を形成する工程の前に前記レジストを感光させ、
前記架橋反応は前記酸を触媒とし前記パターンシュリンク剤を加熱処理することによって起こり、
前記硬化層の除去は強アルカリ薬液で行うことを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記絶縁膜は異なる2種以上の膜が積層したものであることを特徴とする請求項1又は2に記載の半導体装置の製造方法。
- 前記絶縁膜は選択エッチング可能な2種以上の膜が積層したものであり、
前記金属層を形成する工程の前に、前記2種以上の膜の内の少なくとも1つの膜を他の膜よりも開口幅が広くなるように選択エッチングする工程と、を備えたことを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記硬化層を除去する工程は、前記レジストを残しつつ行うことを特徴とする請求項1〜4のいずれか1項に記載の半導体装置の製造方法。
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2011030987A JP5768397B2 (ja) | 2011-02-16 | 2011-02-16 | 半導体装置の製造方法 |
| TW100147697A TWI462161B (zh) | 2011-02-16 | 2011-12-21 | 半導體裝置之製造方法 |
| US13/334,213 US8524601B2 (en) | 2011-02-16 | 2011-12-22 | Method of manufacturing semiconductor device using Resolution Enhanced Lithography Assisted Chemical Shrinkage (RELACS) |
| DE102011090172.8A DE102011090172B4 (de) | 2011-02-16 | 2011-12-30 | Verfahren zum Herstellen einer Halbleitervorrichtung |
| CN201210041968.XA CN102646582B (zh) | 2011-02-16 | 2012-02-15 | 半导体装置的制造方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2011030987A JP5768397B2 (ja) | 2011-02-16 | 2011-02-16 | 半導体装置の製造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2012169539A JP2012169539A (ja) | 2012-09-06 |
| JP5768397B2 true JP5768397B2 (ja) | 2015-08-26 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2011030987A Active JP5768397B2 (ja) | 2011-02-16 | 2011-02-16 | 半導体装置の製造方法 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US8524601B2 (ja) |
| JP (1) | JP5768397B2 (ja) |
| CN (1) | CN102646582B (ja) |
| DE (1) | DE102011090172B4 (ja) |
| TW (1) | TWI462161B (ja) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9525052B2 (en) * | 2007-01-10 | 2016-12-20 | Infineon Technologies Americas Corp. | Active area shaping of III-nitride devices utilizing a field plate defined by a dielectric body |
| US8987784B2 (en) * | 2007-01-10 | 2015-03-24 | International Rectifier Corporation | Active area shaping of III-nitride devices utilizing multiple dielectric materials |
| US9318592B2 (en) * | 2007-01-10 | 2016-04-19 | Infineon Technologies Americas Corp. | Active area shaping of III-nitride devices utilizing a source-side field plate and a wider drain-side field plate |
| US8338861B2 (en) | 2007-01-10 | 2012-12-25 | International Rectifier Corporation | III-nitride semiconductor device with stepped gate trench and process for its manufacture |
| US8946778B2 (en) | 2007-01-10 | 2015-02-03 | International Rectifier Corporation | Active area shaping of III-nitride devices utilizing steps of source-side and drain-side field plates |
| US8946779B2 (en) * | 2013-02-26 | 2015-02-03 | Freescale Semiconductor, Inc. | MISHFET and Schottky device integration |
| DE102014103540B4 (de) | 2014-03-14 | 2020-02-20 | Infineon Technologies Austria Ag | Halbleiterbauelement und integrierte schaltung |
| CN105448704B (zh) * | 2014-09-30 | 2018-08-10 | 中芯国际集成电路制造(上海)有限公司 | 刻蚀方法 |
| CN104701154A (zh) * | 2015-03-11 | 2015-06-10 | 北京工业大学 | 一种使用化学收缩方法实现亚半微米t型栅的制备方法 |
| CN112335023B (zh) * | 2018-06-27 | 2024-07-09 | 三菱电机株式会社 | 半导体装置的制造方法 |
| JP7403083B2 (ja) * | 2019-08-28 | 2023-12-22 | パナソニックIpマネジメント株式会社 | 半導体装置、半導体装置の実装構造、及び半導体装置の製造方法 |
| JP7338482B2 (ja) * | 2020-01-14 | 2023-09-05 | 住友電気工業株式会社 | 半導体装置の製造方法 |
| JP7484479B2 (ja) * | 2020-06-19 | 2024-05-16 | 住友電気工業株式会社 | 半導体装置の製造方法 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08148508A (ja) | 1994-11-22 | 1996-06-07 | Fujitsu Ltd | 半導体装置の電極形成方法 |
| TW372337B (en) | 1997-03-31 | 1999-10-21 | Mitsubishi Electric Corp | Material for forming micropattern and manufacturing method of semiconductor using the material and semiconductor apparatus |
| US6270929B1 (en) * | 2000-07-20 | 2001-08-07 | Advanced Micro Devices, Inc. | Damascene T-gate using a relacs flow |
| ATE304220T1 (de) * | 2002-02-05 | 2005-09-15 | Bernd E Dr Maile | Verfahren zur herstellung einer t-förmigen elektrode |
| KR100475080B1 (ko) * | 2002-07-09 | 2005-03-10 | 삼성전자주식회사 | Si-콘테이닝 수용성 폴리머를 이용한 레지스트 패턴형성방법 및 반도체 소자의 제조방법 |
| WO2004100235A1 (ja) * | 2003-05-09 | 2004-11-18 | Fujitsu Limited | レジストの加工方法、半導体装置及びその製造方法 |
| JP4417677B2 (ja) | 2003-09-19 | 2010-02-17 | 株式会社東芝 | 電力用半導体装置 |
| KR100618851B1 (ko) * | 2004-04-08 | 2006-09-01 | 삼성전자주식회사 | 반도체 소자 제조용 마스크 패턴 및 그 형성 방법과 미세패턴 형성용 코팅 조성물 제조 방법 및 반도체 소자의제조 방법 |
| JP4197691B2 (ja) | 2005-06-21 | 2008-12-17 | 株式会社東芝 | 半導体装置の製造方法 |
| JP2007059711A (ja) * | 2005-08-25 | 2007-03-08 | Sumitomo Electric Ind Ltd | フィールドプレート構造の形成方法および半導体装置 |
| JP2008066587A (ja) * | 2006-09-08 | 2008-03-21 | Toshiba Corp | パターン形成方法 |
| KR20080061651A (ko) * | 2006-12-28 | 2008-07-03 | 주식회사 하이닉스반도체 | 반도체 소자의 형성방법 |
| JP5114947B2 (ja) * | 2006-12-28 | 2013-01-09 | 富士通株式会社 | 窒化物半導体装置とその製造方法 |
| JP4427562B2 (ja) * | 2007-06-11 | 2010-03-10 | 株式会社東芝 | パターン形成方法 |
| JP5058733B2 (ja) * | 2007-09-12 | 2012-10-24 | AzエレクトロニックマテリアルズIp株式会社 | ケイ素含有微細パターン形成用組成物を用いた微細パターン形成方法 |
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2011
- 2011-02-16 JP JP2011030987A patent/JP5768397B2/ja active Active
- 2011-12-21 TW TW100147697A patent/TWI462161B/zh active
- 2011-12-22 US US13/334,213 patent/US8524601B2/en active Active
- 2011-12-30 DE DE102011090172.8A patent/DE102011090172B4/de active Active
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2012
- 2012-02-15 CN CN201210041968.XA patent/CN102646582B/zh active Active
Also Published As
| Publication number | Publication date |
|---|---|
| JP2012169539A (ja) | 2012-09-06 |
| DE102011090172A1 (de) | 2012-08-16 |
| DE102011090172B4 (de) | 2017-12-21 |
| TW201236063A (en) | 2012-09-01 |
| US8524601B2 (en) | 2013-09-03 |
| CN102646582A (zh) | 2012-08-22 |
| CN102646582B (zh) | 2015-03-25 |
| TWI462161B (zh) | 2014-11-21 |
| US20120208365A1 (en) | 2012-08-16 |
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