CN109216163A - 半导体器件的制造方法 - Google Patents
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- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
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Abstract
本申请公开了一种半导体器件的制造方法,涉及半导体技术领域。该制造方法包括:在衬底上形成可刻蚀材料层;通过图案化处理以在可刻蚀材料层上形成多个开口来确定核的位置;对多个开口底部的衬底进行刻蚀,使得多个开口的底部深入衬底;沉积核的材料以填充多个开口;刻蚀核的材料,使得露出可刻蚀材料层;去除可刻蚀材料层,留下多个核;沉积隔离物;过刻蚀隔离物,使得露出多个核,并刻蚀掉部分衬底,衬底的刻蚀深度与开口深入衬底的深度相同;移除多个核。该方法能够解决间隔物之间空隙的距离偏差问题。
Description
技术领域
本申请涉及半导体技术领域,特别涉及一种半导体器件的制造方法。
背景技术
随着半导体技术的发展,对半导体器件制造工艺精细程度的要求越来越高。例如,工艺节点的大小已经缩小到了14nm甚至更小,可以采用自对准双重图案化工艺配合氟化氩193nm光刻工艺来制造半导体器件。
发明内容
本申请的发明人发现上述现有技术中存在如下问题:在形成隔离物时,隔离物之间的开口往往存在距离偏差,即各个开口的深浅不一致,从而导致刻蚀偏差或者过刻蚀中的刻蚀中止层损耗。针对上述问题中的至少一个问题,本发明人提出了解决方案。
本申请的一个目的是提供一种半导体器件制造的技术方案,能够解决间隔物之间空隙的距离偏差问题。
根据本申请的第一方面,提供了一种半导体器件的制造方法,包括:在衬底上形成可刻蚀材料层;通过图案化处理以在所述可刻蚀材料层上形成多个开口来确定核的位置;对所述多个开口底部的衬底进行刻蚀,使得所述多个开口的底部深入所述衬底;沉积核的材料以填充所述多个开口;刻蚀所述核的材料,使得露出所述可刻蚀材料层;去除所述可刻蚀材料层,留下多个核;沉积隔离物;过刻蚀所述隔离物,使得露出所述多个核,并刻蚀掉部分所述衬底,所述衬底的刻蚀深度与所述开口深入衬底的深度相同;移除所述多个核。
可选地,所述可刻蚀材料层包括:无定型碳层和低温氧化物层。
可选地,所述确定核的位置包括:在所述可刻蚀材料层上形成底部抗反射涂层;光刻所述底部抗反射涂层,以形成所述图案化所需的掩模图案;刻蚀所述可刻蚀材料层以形成所述多个开口。
可选地,通过回刻和灰化去除所述可刻蚀材料层,留下所述多个核。
可选地,所述回刻通过等离子刻蚀方法来实现。
可选地,所述核的材料为氧化物;通过FCVD(Flowable Chemical VaporDeposition,可流动化学气相沉积)方法来沉积所述氧化物。
可选地,所述隔离物为氧化物;通过ALD(Atomic Layer Deposition,原子层沉积)方法来沉积所述氧化物。
本申请的一个优点在于,通过在确定核的位置和刻蚀隔离物时,控制对衬底的过刻蚀量保持一致,保证了各个隔离物之间的开口深浅一致,从而解决了隔离物之间开口的距离偏差问题。
附图说明
构成说明书的一部分的附图描述了本申请的实施例,并且连同说明书一起用于解释本申请的原理。
参照附图,根据下面的详细描述,可以更加清楚地理解本申请,其中:
图1示出本申请的半导体器件的制造方法一个实施例的流程图。
图2a-2i示出根据本申请一个实施例的半导体器件的制造方法的各个阶段的示意图。
图3示出本申请的确定核的位置的方法一个实施例的流程图。
图4a-4c示出根据本申请一个实施例的确定核的位置的方法各个阶段的示意图。
具体实施方式
现在将参照附图来详细描述本申请的各种示例性实施例。应注意到:除非另外具体说明,否则在这些实施例中阐述的部件和步骤的相对布置、数字表达式和数值不限制本申请的范围。
同时,应当明白,为了便于描述,附图中所示出的各个部分的尺寸并不是按照实际的比例关系绘制的。
以下对至少一个示例性实施例的描述实际上仅仅是说明性的,决不作为对本申请及其应用或使用的任何限制。
对于相关领域普通技术人员已知的技术、方法和设备可能不作详细讨论,但在适当情况下,所述技术、方法和设备应当被视为授权说明书的一部分。
在这里示出和讨论的所有示例中,任何具体值应被解释为仅仅是示例性的,而不是作为限制。因此,示例性实施例的其它示例可以具有不同的值。
应注意到:相似的标号和字母在下面的附图中表示类似项,因此,一旦某一项在一个附图中被定义,则在随后的附图中不需要对其进行进一步讨论。
图1示出本申请的半导体器件的制造方法一个实施例的流程图。
如图1所示,步骤101,在衬底22上形成可刻蚀材料层21,如图2a所示。例如,可刻蚀材料层21可以是无定型碳层,衬底可以由氮化钛构成。
步骤102,通过图案化处理以在可刻蚀材料层21上形成多个开口23来确定核的位置,如图2b所示。
步骤103,对多个开口23底部的衬底22进行刻蚀,使得多个开口23'的底部深入衬底22,如图2c所示。
步骤104,沉积核的材料24以填充多个开口,如图2d所示。
在一个实施例中,通过FCVD方法来沉积核的材料24,核的材料24可以由氧化物构成。
步骤105,刻蚀核的材料24,使得露出可刻蚀材料层21,如图2e所示。
在一个实施例中,通过氧化物刻蚀处理,去除高于可刻蚀材料层21的核的材料24。
步骤106,去除可刻蚀材料层21,留下多个核25,如图2f所示。
在一个实施例中,通过回刻和灰化去除可刻蚀材料层21,留下多个核25。
步骤107,沉积隔离物26,如图2g所示。
在一个实施例中,通过ALD方法来沉积隔离物26,隔离物26可以为氧化物。
步骤108,过刻蚀隔离物26,使得露出多个核25,并刻蚀掉部分衬底22,衬底22的刻蚀深度27与开口深入衬底的深度28相同,如图2h所示。
在一个实施例中,通过等离子体刻蚀方法刻蚀隔离物26。
步骤109,移除多个核25,得到的半导体器件如图2i所示。
上述实施例中,间隔物的过刻蚀量是基于衬底刻蚀深度设定的,从而保证了间隔物之间开口的深浅一致,避免了由于隔离物之间开口的距离偏差造成的刻蚀偏差或者过刻蚀中的刻蚀中止层损耗。
图3示出本申请的确定核的位置的方法一个实施例的流程图。
如图3所示,步骤301,在衬底22上形成无定型碳层40和低温氧化物层41,如图4a所示。
步骤302,在无定型碳层40和低温氧化物层41上形成底部抗反射涂层42,如图4a所示。
步骤303,光刻底部抗反射涂层42,以形成图案化所需的掩模图案,如图4b所示。
步骤304,刻蚀低温氧化物层41和无定型碳层40以形成多个开口43来确定核的位置,如图4c所示。然后,可以通过刻蚀低温氧化物层41和无定型碳层40,使得开口43的底部深入衬底22,并耗光低温氧化物层41。
上述实施例中,通过对衬底的刻蚀来形成开口,确定了核的位置,并且开口的深度为后面过刻蚀隔离物时对衬底的刻蚀量提供了依据,从而保证了间隔物之间开口的深浅一致,避免了由于隔离物之间开口的距离偏差造成的刻蚀偏差或者过刻蚀中的刻蚀中止层损耗。
至此,已经详细描述了根据本申请的半导体器件的制造方法。为了避免遮蔽本申请的构思,没有描述本领域所公知的一些细节。本领域技术人员根据上面的描述,完全可以明白如何实施这里公开的技术方案。
可能以许多方式来实现本申请的方法和系统。例如,可通过软件、硬件、固件或者软件、硬件、固件的任何组合来实现本申请的方法和系统。用于所述方法的步骤的上述顺序仅是为了进行说明,本申请的方法的步骤不限于以上具体描述的顺序,除非以其它方式特别说明。此外,在一些实施例中,还可将本申请实施为记录在记录介质中的程序,这些程序包括用于实现根据本申请的方法的机器可读指令。因而,本申请还覆盖存储用于执行根据本申请的方法的程序的记录介质。
虽然已经通过示例对本申请的一些特定实施例进行了详细说明,但是本领域的技术人员应该理解,以上示例仅是为了进行说明,而不是为了限制本申请的范围。本领域的技术人员应该理解,可在不脱离本申请的范围和精神的情况下,对以上实施例进行修改。本申请的范围由所附权利要求来限定。
Claims (7)
1.一种半导体器件的制造方法,包括:
在衬底上形成可刻蚀材料层;
通过图案化处理以在所述可刻蚀材料层上形成多个开口来确定核的位置;
对所述多个开口底部的衬底进行刻蚀,使得所述多个开口的底部深入所述衬底;
沉积核的材料以填充所述多个开口;
刻蚀所述核的材料,使得露出所述可刻蚀材料层;
去除所述可刻蚀材料层,留下多个核;
沉积隔离物;
过刻蚀所述隔离物,使得露出所述多个核,并刻蚀掉部分所述衬底,所述衬底的刻蚀深度与所述开口深入衬底的深度相同;
移除所述多个核。
2.根据权利要求1所述的制造方法,其中,
所述可刻蚀材料层包括:无定型碳层和低温氧化物层。
3.根据权利要求1所述的制造方法,其中,所述确定核的位置包括:
在所述可刻蚀材料层上形成底部抗反射涂层;
光刻所述底部抗反射涂层,以形成所述图案化所需的掩模图案;
刻蚀所述可刻蚀材料层以形成所述多个开口。
4.根据权利要求1所述的制造方法,其中,
通过回刻和灰化去除所述可刻蚀材料层,留下所述多个核。
5.根据权利要求4所述的制造方法,其中,所述回刻通过等离子刻蚀方法来实现。
6.根据权利要求1-5所述的制造方法,其中,
所述核的材料为氧化物;
通过可流动化学气相沉积FCVD方法来沉积所述氧化物。
7.根据权利要求1-5所述的制造方法,其中,
所述隔离物为氧化物;
通过原子层沉积ALD方法来沉积所述氧化物。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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CN201710510897.6A CN109216163A (zh) | 2017-06-29 | 2017-06-29 | 半导体器件的制造方法 |
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CN112462470A (zh) * | 2020-10-27 | 2021-03-09 | 中国科学院微电子研究所 | 利用侧墙转移制作硅基光子器件的方法及硅基光子器件 |
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Citations (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6252934A (ja) * | 1985-08-31 | 1987-03-07 | Nippon Gakki Seizo Kk | 選択マスク形成法 |
US20060240361A1 (en) * | 2005-04-21 | 2006-10-26 | Ji-Young Lee | Method of forming small pitch pattern using double spacers |
JP4427562B2 (ja) * | 2007-06-11 | 2010-03-10 | 株式会社東芝 | パターン形成方法 |
CN102346368A (zh) * | 2010-07-23 | 2012-02-08 | 中芯国际集成电路制造(上海)有限公司 | 双重图形曝光掩模制造方法及双重图形曝光方法 |
CN102446703A (zh) * | 2010-10-14 | 2012-05-09 | 中芯国际集成电路制造(上海)有限公司 | 双重图形化方法 |
CN103928394A (zh) * | 2013-01-10 | 2014-07-16 | 中芯国际集成电路制造(上海)有限公司 | 金属互连结构的制作方法 |
CN104022022A (zh) * | 2013-02-28 | 2014-09-03 | 中芯国际集成电路制造(上海)有限公司 | 多重图形的形成方法 |
CN104124139A (zh) * | 2013-04-28 | 2014-10-29 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构的形成方法 |
CN104157564A (zh) * | 2013-05-15 | 2014-11-19 | 中芯国际集成电路制造(上海)有限公司 | 改善刻蚀后关键尺寸均匀性的方法 |
US20150056724A1 (en) * | 2013-08-20 | 2015-02-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit layout and method with double patterning |
CN104701158A (zh) * | 2013-12-05 | 2015-06-10 | 中芯国际集成电路制造(上海)有限公司 | 自对准双重图形的形成方法 |
US20150214094A1 (en) * | 2014-01-24 | 2015-07-30 | Christopher J. Jezewski | Methods for forming interconnect layers having tight pitch interconnect structures |
CN105470117A (zh) * | 2014-09-09 | 2016-04-06 | 中芯国际集成电路制造(上海)有限公司 | 一种基于双图案的半导体器件及其制造方法、电子装置 |
CN105977141A (zh) * | 2016-05-10 | 2016-09-28 | 上海格易电子有限公司 | 一种自对准双重图形化的方法 |
CN106229255A (zh) * | 2016-07-27 | 2016-12-14 | 上海华虹宏力半导体制造有限公司 | 优化自对准双重曝光显影工艺的方法以及半导体器件 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8852851B2 (en) * | 2006-07-10 | 2014-10-07 | Micron Technology, Inc. | Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same |
US9087699B2 (en) * | 2012-10-05 | 2015-07-21 | Micron Technology, Inc. | Methods of forming an array of openings in a substrate, and related methods of forming a semiconductor device structure |
US9728406B2 (en) * | 2014-08-08 | 2017-08-08 | Applied Materials, Inc. | Multi materials and selective removal enabled reverse tone process |
JP2018531506A (ja) * | 2015-09-24 | 2018-10-25 | 東京エレクトロン株式会社 | サブ解像度基板パターニングのためのエッチングマスクを形成する方法 |
US9842931B1 (en) * | 2016-06-09 | 2017-12-12 | International Business Machines Corporation | Self-aligned shallow trench isolation and doping for vertical fin transistors |
US10832908B2 (en) * | 2016-11-11 | 2020-11-10 | Lam Research Corporation | Self-aligned multi-patterning process flow with ALD gapfill spacer mask |
CN108321079B (zh) * | 2017-01-16 | 2021-02-02 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
WO2018156985A1 (en) * | 2017-02-23 | 2018-08-30 | Tokyo Electron Limited | Method of anisotropic extraction of silicon nitride mandrel for fabrication of self-aligned block structures |
US10396206B2 (en) * | 2017-07-07 | 2019-08-27 | Globalfoundries Inc. | Gate cut method |
-
2017
- 2017-06-29 CN CN201710510897.6A patent/CN109216163A/zh active Pending
-
2018
- 2018-06-29 US US16/023,200 patent/US10395927B2/en active Active
Patent Citations (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6252934A (ja) * | 1985-08-31 | 1987-03-07 | Nippon Gakki Seizo Kk | 選択マスク形成法 |
US20060240361A1 (en) * | 2005-04-21 | 2006-10-26 | Ji-Young Lee | Method of forming small pitch pattern using double spacers |
JP4427562B2 (ja) * | 2007-06-11 | 2010-03-10 | 株式会社東芝 | パターン形成方法 |
CN102346368A (zh) * | 2010-07-23 | 2012-02-08 | 中芯国际集成电路制造(上海)有限公司 | 双重图形曝光掩模制造方法及双重图形曝光方法 |
CN102446703A (zh) * | 2010-10-14 | 2012-05-09 | 中芯国际集成电路制造(上海)有限公司 | 双重图形化方法 |
CN103928394A (zh) * | 2013-01-10 | 2014-07-16 | 中芯国际集成电路制造(上海)有限公司 | 金属互连结构的制作方法 |
CN104022022A (zh) * | 2013-02-28 | 2014-09-03 | 中芯国际集成电路制造(上海)有限公司 | 多重图形的形成方法 |
CN104124139A (zh) * | 2013-04-28 | 2014-10-29 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构的形成方法 |
CN104157564A (zh) * | 2013-05-15 | 2014-11-19 | 中芯国际集成电路制造(上海)有限公司 | 改善刻蚀后关键尺寸均匀性的方法 |
US20150056724A1 (en) * | 2013-08-20 | 2015-02-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit layout and method with double patterning |
CN104701158A (zh) * | 2013-12-05 | 2015-06-10 | 中芯国际集成电路制造(上海)有限公司 | 自对准双重图形的形成方法 |
US20150214094A1 (en) * | 2014-01-24 | 2015-07-30 | Christopher J. Jezewski | Methods for forming interconnect layers having tight pitch interconnect structures |
CN105470117A (zh) * | 2014-09-09 | 2016-04-06 | 中芯国际集成电路制造(上海)有限公司 | 一种基于双图案的半导体器件及其制造方法、电子装置 |
CN105977141A (zh) * | 2016-05-10 | 2016-09-28 | 上海格易电子有限公司 | 一种自对准双重图形化的方法 |
CN106229255A (zh) * | 2016-07-27 | 2016-12-14 | 上海华虹宏力半导体制造有限公司 | 优化自对准双重曝光显影工艺的方法以及半导体器件 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112462470A (zh) * | 2020-10-27 | 2021-03-09 | 中国科学院微电子研究所 | 利用侧墙转移制作硅基光子器件的方法及硅基光子器件 |
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