TW202235649A - 填充間隙之方法與相關之系統及裝置 - Google Patents

填充間隙之方法與相關之系統及裝置 Download PDF

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TW202235649A
TW202235649A TW110142476A TW110142476A TW202235649A TW 202235649 A TW202235649 A TW 202235649A TW 110142476 A TW110142476 A TW 110142476A TW 110142476 A TW110142476 A TW 110142476A TW 202235649 A TW202235649 A TW 202235649A
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plasma
substrate
silicon
reaction chamber
silicon precursor
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TW110142476A
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劉澤鋮
金仙子
維爾傑米 波爾
姚佳立
蘭吉特 博魯德
巴布魯 穆克吉
蕾尼 亨里克斯 約瑟夫 維爾沃特
堤隆嘉
小林伸好
堀勝
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荷蘭商Ａｓｍ Ｉｐ私人控股有限公司
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Publication of TW202235649A publication Critical patent/TW202235649A/zh

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    • H01L21/02107—Forming insulating materials on a substrate
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    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02252—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by plasma treatment, e.g. plasma oxidation of the substrate
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    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02312—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour
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Abstract

揭示用於填充一基板中所包含之一間隙部件的方法及相關系統。該方法包括將一包括一或多個間隙部件之基板提供至一反應室中的步驟。該一或多個間隙部件包括一上部部分及一下部部分，該上部部分包括一上表面且該下部部分包括一下表面。該方法進一步包含一使該基板承受一電漿處理的步驟。因此，該上表面係受到抑制，並同時使該下表面實質上不受影響。接著，該方法包括將一含矽材料選擇性沉積於該下表面上的步驟。

Description

填充間隙之方法與相關之系統及裝置
本發明總體上係關於適於形成電子裝置之方法和系統。更具體而言，本發明係關於可用於在間隙、溝槽及類似物中沈積一材料的方法及系統。
半導體裝置之縮放已導致積體電路速度及密度之顯著改進。然而，隨著大規模積體裝置之佈線間距的小型化，由於現有沉積製程之限制，高深寬比之間隙或溝槽（例如，具有三或更高之深寬比的溝槽）的無孔洞填充變得愈來愈困難。因此，係需要有效在半導體基板（例如於上下文中之邏輯及/或記憶裝置）上填充高深寬比部件（例如諸如溝槽之類的間隙）之製程。利用含矽材料，諸如氧化矽，而有效填充高深寬比部件之製程係有需足以抵抗後續化學機械研磨（CMP）步驟及蝕刻製程的特別需求。
本節提出之任何討論，包括問題及解決方案的討論，僅為了提供本發明背景脈絡之目的而包括在本發明中。此類討論不應視為承認任何或全部資訊在完成本發明時為已知或以其他方式構成先前技術。
本發明之各種實施例係關於間隙填充方法、關於使用此類方法所形成之結構及裝置、及關於用於執行該等方法及/或用於形成該等結構及/或裝置之設備。本發明之各種實施例解決先前方法及系統之缺陷的方式係在以下更詳論述之。
本發明揭示一種用於填充一間隙部件的方法。該方法依給定順序包含一在一反應室中將一基板定位於一基板支座上的步驟。該基板包含一或多個間隙部件。該一或多個間隙部件包括一上部部分及一下部部分，該上部部分包括一上表面且該下部部分包括一下表面。該方法進一步包括一使該基板承受一電漿預處理的步驟。該電漿處理係導致該上表面的一抑制，並同時使該下表面實質上不受影響。該方法進一步包含一將一含矽材料選擇性沉積於該下表面上的步驟。該在該下表面上沉積一含矽材料之步驟包含一循環製程。該循環沉積製程包含複數個子循環。一子循環依給定順序包含：一將該基板暴露至一包含一胺基及二或更多個矽原子之矽前驅物的步驟。該基板係特別在一矽前驅物脈衝中暴露至該矽前驅物，以在該下表面上形成化學吸附矽前驅物。一子循環進一步包含一將該基板暴露至一矽前驅物後脈衝電漿處理的步驟，因此允許電漿中所包含之一或多種反應性物種與該下表面上之該化學吸附矽前驅物反應。
在一些實施例中，該胺基係選自NH 2、NHR i及NR iR ii，且R i及R ii中之至少一者為一C 1至C 4烷基。
在一些實施例中，該矽前驅物包含選自由一胺基矽烷、一矽烷胺及一環矽氧烷組成之列表的一化合物。
在一些實施例中，該矽前驅物包含一烷基胺基矽烷。
在一些實施例中，該矽前驅物包含選自SiR 1R 3R 4-SiR 2R 5R 6， SiR 1R 3R 4-SiR 5R 6-SiR 2R 7R 8及SiR 1R 3R 4-SiR 2R 5-SiR 6R 7R 8的一化合物，其中R 1及R 2係為NR 9R 10，且R 3、R 4、R 5、R 6、R 7、R 8、R 9及R 10係獨立選自H及一C 1至C 4烷基。
在一些實施例中，該矽前驅物包含選自R 1-SiH 2-SiH 3、R 1-SiH 2-SiH 2-SiH 2-R 2及R 1-SiH 2-SiHR 2-SiH 3的一化合物，其中R 1及R 2係獨立選自NH 2、NHR 9及NR 9R 10，以及R 9及R 10係獨立選自H及一C 1至C 4烷基。
在一些實施例中，R 3及R 4中之至少一者係為一C 1至C 4烷基。
在一些實施例中，該矽前驅物包含一矽烷胺。
在一些實施例中，該矽前驅物包含一可由一根據分子式(1)之化學結構表示的化合物
Figure 02_image001
(1) 其中R 11及R 12係獨立選自H及一C 1至C 4烷基。
在一些實施例中，該矽前驅物包含一包含至少一胺基的環矽氧烷。
在一些實施例中，該環矽氧烷進一步包含一或多個C 1至C 4烷基取代基。
在一些實施例中，該胺基係選自NH 2、NHR 13及NR 13R 14，且R 13及R 14係獨立選自H及一C 1至C 4烷基。
在一些實施例中，該電漿預處理包含使該基板承受一惰性氣體電漿。
在一些實施例中，該電漿預處理包含使該基板承受一含氮電漿。
在一些實施例中，該電漿預處理包含使該基板承受一第一電漿處理及使該基板承受一第二電漿處理。
在一些實施例中，該第一電漿處理包含在該反應室中生成一含氮電漿。
在一些實施例中，該含氮電漿係為一含N 2之電漿。
在一些實施例中，該第二電漿處理包含在該反應室中生成一含惰性氣體電漿。
在一些實施例中，該含惰性氣體電漿係為一含氬電漿。
在一些實施例中，該基板係維持在至少100°C至至多500°C的溫度。
在一些實施例中，該反應室係維持在至少1 Torr至至多20 Torr的壓力。
在一些實施例中，該方法包含執行複數個超循環。一超循環包含該使該基板承受一電漿預處理的步驟；及該將一含矽材料選擇性沉積至該下表面上的步驟。
在一些實施例中，該矽前驅物後脈衝電漿處理包含在該反應室中生成一含氧電漿，且該含矽材料包含氧化矽。
在一些實施例中，該含氧電漿係為一含O 2之電漿。
在一些實施例中，該將一材料選擇性沉積於該下表面上之步驟係以每子循環至少0.1 Å至每子循環至多10 Å 之生長速率進行。
本文進一步描述一種半導體處理設備。其包含一反應室，該反應室繼而包含一用於支持一基板的基板支座。該基板包含一或多個間隙部件。該半導體處理設備進一步包含一經建構且配置成在該反應室中加熱該基板的加熱器。該半導體處理設備進一步包含一經由一第一電漿氣體閥而與該反應室流體連通的第一電漿氣體源。該半導體處理設備進一步包含一經由一第二電漿氣體閥而與該反應室流體連接的第二電漿氣體源。該半導體處理設備進一步包含一經由一第三電漿氣體閥而與該反應室流體連接的第三電漿氣體源。該半導體處理設備進一步包含一電漿模組，其係包含一經建構且配置成在該反應室中生成一電漿的射頻功率源。該半導體處理設備進一步包含經由一或多個前驅物閥而與該反應室流體連接的一或多個矽前驅物源。該半導體處理設備進一步包含一經配置成使該設備執行一如本文所述之方法的控制器。
所屬技術領域中具有通常知識者從下列參考附圖之某些實施例的詳細描述將明白這些及其他實施例。本發明並未受限於任何所揭示具體實施例。
以下所提供之方法、結構、裝置及系統之示例性實施例的描述僅係示例性且僅係意欲用於說明之目的；下列描述並非意欲限制本發明或申請專利範圍之範疇。此外，列舉具有所陳述部件之多個實施例不意欲排除具有額外部件之其他實施例或納入所陳述部件之不同組合的其他實施例。例如，各種實施例係提出作為示例性實施例，並可列舉於附屬項中。除非另有註明，示例性實施例或其等之組件可組合或可彼此分開應用。
在本發明中，「氣體」可包括在常溫及常壓(NTP)下為氣體、汽化固體及/或汽化液體之材料，並可取決於上下文由單一氣體或氣體混合物構成。除了製程氣體以外的氣體（亦即，非通過氣體分配總成、多埠注入系統、其他氣體分配裝置或類似者所引入的氣體）可用於例如密封反應空間，且可包括諸如稀有氣體的密封氣體。如本文所使用之用語「稀有氣體」及「惰性氣體」可互換使用。在一些情況下，用語「前驅物」可指參與生成另一化合物之化學反應的化合物，且具體係指構成一薄膜矩陣或一薄膜的一主要骨架、或結合於一薄膜中作為其構成部分的化合物；用語「反應物」可與用語前驅物互換使用。
如本文所使用，用語「基板」可指能夠用以形成或於其上形成一裝置、一電路，或一薄膜之任何一或多個下伏材料。一基板可包括一塊材（諸如矽（例如單晶矽））、其他IV族材料（諸如鍺）或其他半導體材料（諸如II-VI族或III-V族半導體），並可包括上覆或下伏於該塊材的一或多個層。
此外，在本發明中，變數之任兩個數字可構成變數之可工作範圍，且所指示之任何範圍可包括或排除端點。額外地，所指示的變數之任何數值（不管該等數值是否以「約」來指示）可指精確值或近似值並包括等效值，且可指平均值、中間值、代表值、多數值或類似者。進一步地，在本發明中，於一些實施例中，用語「包括(including)」、「由……構成(constituted by)」及「具有(having)」係獨立地指「一般或廣泛地包含(typically or broadly comprising)」、「包含(comprising)」、「基本上由……組成(consisting essentially of)」或「由……組成(consisting of)」。在本發明中，於一些實施例中，任何已定義之意義不必然排除通常及慣用意義。
如本文所使用，用語「包含」係指包括某些部件，但其不排除存在其他部件，只要其不使申請專利範圍或實施例無法實施即可。在一些實施例中，用語「包含」包括「由……組成(consisting)」。如本文所使用，用語「由……組成」係指除了以下所述措辭的部件，無其他部件存在於裝置/方法/產品中。當用語「由……組成」用於指示化合物時，其係指化學化合物僅包含所列舉的組分。
如本文所用，用語「沖洗」係指使前驅物及/或活性物種自一反應室中被移除的一製程步驟。在一沖洗期間，可將一惰性或實質上惰性氣體提供至該反應室。額外地或替代地，該反應室可在一沖洗期間排空。
本文所述係為一種用於填充一間隙部件的方法。該間隙部件係包含在一基板中，並可位於該基板表面或附近。可選地，該基板可包含多個間隙部件，例如複數個間隙部件。一間隙部件包括一上部部分以及一下部部分，該上部部分包括一上表面且該下部部分包括一下表面。適合的基板包括半導體晶圓，例如矽晶圓。本發明方法可在製造各種半導體裝置期間使用，且特別適用於填充具有一高深寬比及一特定小寬度的間隙部件，例如具有一小於10 nm之寬度及一高於2或5或10或20的深寬比。該方法包括一在一反應室中將該基板定位在一基板支座上的步驟。該方法進一步包括一使該基板承受一電漿預處理的步驟。該電漿預處理係導致該上表面的一抑制，並同時使該下表面實質上不受影響。在該電漿預處理之後，該方法進一步包含一將一含矽材料選擇性沉積於該下表面上的步驟。可選地，一沖洗在該將材料選擇性沉積於該下表面上的步驟之前先進行。應理解，在該沖洗期間，沒有電漿生成於該反應室中。亦應理解，該在該下表面上選擇性沉積一含矽材料的步驟包含一循環製程，其包含可連續重複直至該下表面上已沉積一所需厚度之含矽材料為止的子步驟。例示性含矽材料係包括氧化矽及氧碳化矽。該循環製程係包括複數個循環，亦稱為子循環。一子循環依以下順序包含：一將該基板在一矽前驅物脈衝中暴露至一矽前驅物的步驟，及一將該基板暴露至一矽前驅物後脈衝電漿處理的步驟。可選地，將該基板暴露至該矽前驅物的步驟係在一沖洗前先進行。可選地，將該基板暴露至該矽前驅物的步驟係緊接著一沖洗。應理解，在該等沖洗期間，沒有電漿生成於該反應室中。該將該基板暴露至一矽前驅物的步驟係導致該矽前驅物於該下表面上的化學吸附。換言之，藉由將該基板暴露於該矽前驅物，相較於已電漿鈍化的上表面，更多的矽前驅物化學吸附至未鈍化的下表面上。該將該基板暴露至一矽前驅物後脈衝電漿處理的步驟係導致電漿中包含之一或多種反應性物種與在該將該基板暴露至一矽前驅物之步驟期間化學吸附於該下表面上的該矽前驅物之間的一反應。在一些實施例中，該方法包括利用該含矽材料完全填充該間隙部件。此可，例如藉由重複該循環製程直至該含矽材料填充整個間隙部件為止而完成。
有利地，此類方法係提供一非常短的循環時間。實際上，獲得一特定膜厚度所需的沉積時間可縮短50%或更多，因此可得到較高的產出量及對下伏層的較少製程誘發損傷。一製程誘發損傷的實例係為電漿誘發損傷。
在一些實施例中，該循環製程包含至少2個子循環至至多20000個子循環。例如，一循環沉積製程可包括2個子循環、3個子循環、5個子循環、10個子循環、20個子循環、30個子循環、60個子循環、100個子循環、200個子循環、500個子循環、1000個子循環、2000個子循環、5000個子循環、10000個子循環或更多。
在一些實施例中，該矽前驅物後脈衝電漿處理包含在該反應室中生成一含氧電漿，且該含矽材料包含氧化矽。在一些實施例中，該含氧電漿係為一含O 2之電漿。因此，如本文所述之方法可用於各種應用，例如為了淺溝槽隔離目的而用於無接縫SiO 2填充間隙部件。此類無縫淺溝槽隔離可有利地減少洩漏電流、蝕刻抗性及改善與化學機械研磨製程相關的彈性。此外，此類SiO 2膜可具有一極低碳含量。此外，此類SiO 2膜可具有一極低氮含量。
在一些實施例中，該矽前驅物後脈衝電漿處理包括將該基板暴露至一氧電漿，且O 2係使用作為一電漿氣體。在一些實施例中，O 2係以一至少100 sccm至至多10000 sccm的流速、或以一至少200 sccm至至多5000 sccm的流速或以一至少500 sccm至至多1000 sccm的流速而提供至該反應室。在一些實施例中，該氧電漿係藉由一RF產生器在至少50 W至至多200 W之電漿功率下操作生成。在一些實施例中，該氧電漿係在一氧電漿脈衝期間生成至少0.1秒至至多10秒、或至少0.2秒至至多5秒或至少0.5秒至至多2秒。在一些實施例中，將該基板暴露至一氧電漿後係緊接著進行一沖洗，且該沖洗持續至少0.2秒至至多10秒或至少1秒至至多5秒。應理解，在該沖洗期間，沒有電漿生成於該反應室中。
在一些實施例中，該在該下表面上選擇性沉積一材料的步驟係以至少0.1 Å/循環至至多10 Å/循環的一生長速率完成，例如至少0.2 Å/循環至至多3 Å/循環或至少0.3至至多 1 Å/循環的一生長速率。例如，該材料係以0.49 Å/循環的一生長速率沉積於該下表面上。在一些實施例中，該上表面上之生長速率係較在該上表面上慢至少2至至多20倍。在一些實施例中，該上表面上之生長速率係較在該上表面上慢至少2至至多5倍。在一些實施例中，該上表面上之生長速率係較在該上表面上慢至少5至至多10倍。在一些實施例中，該上表面上之生長速率係較在該上表面上慢至少10至至多20倍。在一些實施例中，該上表面上之生長速率係小於0.1 Å/循環。在一些實施例中，該上表面上之生長速率係為0 Å/循環。
意外地發現，使用特定矽前驅物可獲得一高生長速率及由下而上的生長。因此，在一些實施例中，該矽前驅物係包含一胺基及二或更多個矽原子。
在一些實施例中，該矽前驅物包含選自由一胺基矽烷、一矽烷胺及一環矽氧烷組成之列表的一化合物。例示性矽前驅物及其製備方法揭示於，例如WO2015048237A2、WO2015047914A1、US10192734B2中。
在一些實施例中，該胺基係選自NH 2、NHR i及NR iR ii。在一些實施例中，R i及R ii為烴基。在一些實施例中，R i及R ii相同。在一些實施例中，R i及R ii不同。在一些實施例中，R i及R ii係獨立選自一C 1至C 4烷基或烯基。在一些實施例中，R i及R ii中之至少一者為一C 1至C 4烷基。
在一些實施例中，該矽前驅物包含一烷基胺基矽烷。在一些實施例中，該矽前驅物係為一包含一或多個胺基之二矽烷或三矽烷。
在一些實施例中，該矽前驅物係選自SiR 1R 3R 4-SiR 2R 5R 6、SiR 1R 3R 4-SiR 5R 6-SiR 2R 7R 8及SiR 1R 3R 4-SiR 2R 5-SiR 6R 7R 8。應理解，R 1及R 2係為NR 9R 10，且R 3、R 4、R 5、R 6、R 7、R 8、R 9及R 10係獨立選自H及烴基。在一些實施例中，R 3、R 4、R 5、R 6、R 7、 R 8、R 9及R 10係獨立選自H、C 1至C 4烷基、C 1至C 4烯基及C 4至C 8芳基。在一些實施例中，R 3、R 4、R 5、R 6、R 7、R 8、R 9及R 10係獨立選自H及C 1至C 4烷基。在一些實施例中，R 3、R 4、R 5、R 6、R 7、R 8、R 9及R 10中之至少一者為H。在一些實施例中，R 3、R 4、 R 5、 R 6、R 7、R 8、R 9及R 10中之至少一者為甲基。在一些實施例中，R 3、R 4、R 5、R 6、R 7、R 8、R 9及R 10中之至少一者為乙基。在一些實施例中，R 3、R 4、R 5、R 6、R 7、R 8、R 9及R 10中之至少一者為丙基。在一些實施例中，R 3、R 4、R 5、R 6、R 7、R 8、R 9及R 10中之至少一者為異丙基。在一些實施例中，R 3、R 4、R 5、R 6、R 7、R 8、R 9及R 10全部為甲基。在一些實施例中，該矽前驅物包含二甲基胺基五甲基二矽烷。
在一些實施例中，該矽前驅物係選自R 1-SiH 2-SiH 3、R 1-SiH 2-SiH 2-SiH 2-R 2及R 1-SiH 2-SiHR 2-SiH 3，其中R 1及R 2係獨立選自NH 2、NHR 9及NR 9R 10，且其中R 9及R 10係獨立選自H及一C 1至C 4烴基。在一些實施例中，R 9及R 10係獨立選自H、C 1至C 4烷基、C 1至C 4烯基及C 4至C 8芳基。在一些實施例中，R 9及R 10係獨立選自H及一C 1至C 4烷基。在一些實施例中，R 9及R 10中之至少一者為H。在一些實施例中，R 9及R 10中之至少一者為甲基。在一些實施例中，R 9及R 10中之至少一者為乙基。在一些實施例中，R 9及R 10中之至少一者為丙基。在一些實施例中，R 9及R 10中之至少一者為異丙基。在一些實施例中，R 9及R 10為甲基。在一些實施例中，R 3及R 4中之至少一者為一C 1至C 4烷基。在一些實施例中，該矽前驅物包含選自二異丙基胺基二矽烷及二乙丁基胺基二矽烷的一烷基胺基矽烷。
在一些實施例中，該矽前驅物包含一矽烷胺。
在一些實施例中，該前驅物可由一根據分子式(i)之化學式表示
Figure 02_image003
(i)
其中R 11及R 12係獨立選自H及一C 1至C 4烷基。在一些實施例中，R 11及R 12中之至少一者為H。在一些實施例中，R 11及R 12中之至少一者為甲基。在一些實施例中，R 11及R 12中之至少一者為乙基。在一些實施例中，R 11及R 12中之至少一者為丙基。在一些實施例中，R 11及R 12中之至少一者為丁基。在一些實施例中，R 11及R 12中之至少一者為異丙基。在一些實施例中，R 11及R 12為異丙基。
在一些實施例中，該矽前驅物包含一包含至少一個胺基的環矽氧烷。在一些實施例中，該胺基係選自NH 2、NHR i及NR iR ii。在一些實施例中，R i及R ii為烴基。在一些實施例中，R i及R ii相同。在一些實施例中，R i及R ii不同。在一些實施例中，R i及R ii係獨立選自一C 1至C 4烷基或烯基。在一些實施例中，R i及R ii中之至少一者為一C 1至C 4烷基。在一些實施例中，該胺基係選自NH 2、NHR 13及NR 13R 14，且R 13及R 14係獨立選自H及一C 1至C 4烷基。
在一些實施例中，該環矽氧烷進一步包含一或多個C 1至C 4烷基取代基。在一些實施例中，該等C 1至C 4烷基取代基中之至少一者為甲基。在一些實施例中，該等C 1至C 4烷基取代基中之至少一者為乙基。在一些實施例中，該等C 1至C 4烷基取代基中之至少一者為丙基。在一些實施例中，該等C 1至C 4烷基取代基中之至少一者為丁基。一適合之矽氧烷係包括2-二乙基胺基-2,4,6,8-四甲基環四矽氧烷。
應理解，該電漿預處理之施加係導致該上表面的一抑制，並同時使該下表面實質上不受影響，或至少較該上表面受更少影響。換言之，該上表面對一可接續被提供至該反應室之前驅物的反應可適當地減少。仍有不同地陳述方式，使該基板承受該電漿預處理可導致在該間隙部件中的一抑制梯度。特別地，該抑制在該間隙之該上部部分中較在該間隙之下部部分中更強烈。換言之，該抑制從該間隙的該上部部分至該間隙的該下部部分逐漸降低。在本發明不受限於任何特定理論或操作模式的情形下，咸信該上表面之抑制係由於接近表面頂部之諸如羥基及胺基的反應性表面基團的消耗所造成，反之，咸信接近該下表面，亦即在溝槽底部附近，的反應性表面基團係較少或不受該電漿預處理的影響。
一使用不超過一種電漿的電漿預處理係有利地導致一短暫的循環時間。此外，當電漿僅維持短時間，例如至少5秒至至多15秒的時間時，可獲得具有諸如低洩漏、高崩潰電壓之有利特性的介電層，諸如SiO 2。當該介電層係沉積在一電晶體（例如一矽電晶體或一薄膜電晶體）中之一通道區域上或附近時，可在該電晶體之通道中有利地獲得一高電子遷移率。
在一些實施例中，該電漿預處理係導致一鈍化梯度，亦即一自該上表面至該下表面的逐漸改變鈍化強度。在此例子中，該將該基板暴露至一前驅物的步驟可導致自該下表面至該上表面之每個單位面積化學吸附前驅物之密度的一逐漸改變。該矽前驅物後脈衝電漿處理接著允許電漿中所包含之一或多種反應性物種與化學吸附前驅物反應，以形成一材料。由於相較於該上表面，更多前驅物化學吸附於該下表面上，故在該下表面上有較該上表面更多的材料形成。換言之，該材料以一由下而上方式選擇性地生長。
在一些實施例中，該電漿預處理包含使該基板承受一惰性氣體電漿。在一些實施例中，該惰性氣體電漿係為一氬電漿。
在一些實施例中，該電漿預處理包含使該基板承受一含氮電漿。在一些實施例中，該含氮電漿係為一N 2電漿。在一些實施例中，該含氮電漿係為一NH 3電漿。
在一些實施例中，該電漿預處理包含將該基板暴露至一H 2-N 2電漿。應理解，一H 2-N 2電漿係指一使用一包含H 2及N 2之電漿氣體的電漿。一H 2-N 2電漿可有利地用於使用一烷基胺基矽烷（諸如雙(二乙基胺基)矽烷）之以一含矽材料填充一間隙。
在一些實施例中，該電漿預處理包含使該基板承受一含氫電漿。在一些實施例，該含氫電漿係為一H 2電漿。
在一些實施例中，該電漿預處理包含使該基板承受一第一電漿處理及使該基板承受一第二電漿處理。應理解，該第一及該第二電漿處理係為不同，亦即不相同。可選地，該第一及該第二電漿處理係藉由一沖洗而分開。應理解，在一沖洗期間，沒有電漿生成於該反應室中。
在一些實施例中，該第一電漿處理包含在該反應室中生成一含氮電漿。在一些實施例中，該含氮電漿係為一含N 2之電漿。換言之，在一些實施例中，一包含N 2的電漿氣體係用於生成該含氮電漿。
在一些實施例中，該第二電漿處理包含在該反應室中生成一含惰性氣體電漿。在一些實施例中，該含惰性氣體電漿係為一含氬電漿。
在一些實施例中，該第一電漿處理包含在該反應室中生成一氮電漿，且該第二電漿處理包含在該反應室中生成一惰性氣體電漿。在此類實施例中，在該第一及該第二電漿處理後選擇性沉積之諸如氧化矽淺溝槽隔離的材料可有利地以低至可忽略C殘基及高品質膜為部件。此外，當該基板包含Si鰭片時，這些電漿處理有利地限制或避免該等矽鰭片的氧化。另外，在該氮電漿之後使用一惰性氣體電漿可有利地減少或消除該基板上含N表面基團（亦稱為氮殘基）的量。
在一些實施例中，該第一電漿處理包含將該基板暴露至一氮電漿，且該氮電漿係包含N 2。在一些實施例中，N 2係以至少200 sccm至至多2000 sccm的流速、或至少400 sccm至至多1200 sccm的流速或至少600 sccm至至多1000 sccm的流速而提供至該反應室。在一些實施例中，該氮電漿係藉由一RF產生器在至少100 W至至多1000 W，例如至少200 W至至多500 W，的一電漿功率下生成。在一些實施例中，該N 2電漿係生成持續至少5秒至至多50秒，例如持續至少10秒至至多20秒。在一些實施例中，該N 2電漿係生成持續至少0.01秒至至多50秒，例如持續至少0.2秒至至多20秒，例如持續至少0.5 秒至至多10秒，例如持續至少1秒至至多5秒。在一些實施例中，該N 2電漿係緊接著一維持至少1秒至至多5秒的沖洗。在一些實施例中，該N 2電漿係緊接著一維持至少0.1秒至至多10秒的沖洗。應理解，在該沖洗期間，沒有電漿生成於該反應室中。亦應瞭解，當該電漿氣體自一製程步驟改變至另一時，如當該基板先承受一第一電漿處理然後再承受一第二電漿處理時，至少1 秒的沖洗時間可特別有利。
在一些實施例中，該第二電漿處理包含將該基板暴露至一氬電漿，且該電漿氣體包含Ar。在一些實施例中，Ar係以至少1 slm至至多10 slm的流速或至少2 slm至至多5 lm的流速而提供至該反應室。在一些實施例中，該氬電漿係藉由一RF產生器在至少100 W至至多1000 W之電漿功率，例如至少200 至至多500 W之電漿功率下生成。在一些實施例中，該氬電漿的生成持續至少5秒至至多50秒，例如持續至少10秒至至多20秒。在一些實施例中，該氬電漿之後接著進行至少0.1秒至至多2秒，例如至少0.2秒至至多1秒的沖洗。應理解，在該沖洗期間，沒有電漿生成於該反應室中。需注意，上述數值是當使用一300 mm晶圓作為基板時所給出，且如果需要，該等數值可容易地適應不同的基板尺寸。
在一些實施例中，該基板係維持在至少100°C至至多500°C的溫度、或至少100°C至至多200°C的溫度、或至少200°C至至多300°C的溫度、或至少300°C至至多400°C的溫度或至少400°C至至多500°C的溫度。
在一些實施例中，該反應室係維持在至少0.1 Torr至至多200 Torr、或至少0.2 Torr至至多100 Torr、或至少0.5 Torr至至多50 Torr、或至少1 Torr至至多20 Torr或至少2 Torr至至多10 Torr之壓力，例如該反應室可維持在5 Torr的壓力。
在一些實施例中，該等矽前驅物脈衝係具有至少1秒至至多20 秒、或至少2秒至至多10秒或至少3秒至至多5 秒的持續時間。在一些實施例中，該等矽前驅物脈衝係具有至少0.1秒至至多20秒、或至少0.2秒至至多10秒、或至少0.5秒至至多5秒或至少1秒至至多2秒的持續時間。在一些實施例中，該等矽前驅物脈衝係緊接著沖洗，且該等沖洗具有至少0.2秒至至多20秒、或至少0.5秒至至多10秒或至少1秒至至多5秒的持續時間。應理解，在該沖洗期間，沒有電漿生成於該反應室中。
在一些實施例中，該方法包含連續執行複數個超循環。一超循環包含該使該基板承受一電漿預處理的步驟；及該將一含矽材料選擇性沉積至該下表面上的步驟。在一些實施例中，該方法包括執行該超循環至少5次至至多10000次、或至少10次至至多5000次、或至少20次至至多2000次、或至少50次至至多1000次或至少100次至至多500次。在一些實施例中，該方法包含執行該超循環至少5次至至多50次或至少10次至至多20次。在一些實施例中，連續超循環係藉由一沖洗而彼此分開。應理解，在該沖洗期間，沒有電漿生成於該反應室中。
本文進一步描述一種半導體處理設備。該設備包含一反應室、一加熱器、一第一電漿氣體源、一第二電漿氣體源、一電漿模組、一或多個前驅物源及一控制器。可選地，該設備進一步包含一第三電漿氣體源。該基板支座適當地允許支撐一包含一或多個間隙部件的基板。該加熱器係經建構且配置成在該反應室中加熱該基板。該第一電漿氣體源係經由一第一電漿氣體閥而與該反應室流體連通。該第一電漿氣體源可配置成，例如將一含氮氣體及/或一含惰性氣體提供至該反應室。該第二電漿氣體源係經由一第二電漿氣體閥而與該反應室流體連接。該第二電漿氣體源可配置成，例如將一含氧氣體提供至該反應室。當存在時，該第三電漿氣體源可經由一第三電漿氣體閥而與該反應室流體連接。該第三電漿氣體源可配置成，例如將一含氮氣體及/或一含惰性氣體提供至該反應室。該電漿模組包含一射頻功率源，其係經建構且配置成在該反應室中生成一電漿。該一或多個前驅物源係經由一或多個前驅物閥而與該反應室流體連接。適當地，該半導體處理設備可進一步包含一用於排放反應産物、載送氣體及未使用前驅物及共反應物的排氣。該控制器包含一處理器及一或多個記憶體模組，且經程式化或以其他方式配置而使該設備執行如本文所述的方法。
可選地，該系統係配置成藉由一載送氣體而將該等前驅物中之至少一者提供至該反應室。合適的載送氣體包括惰性氣體。換言之，在一些實施例中，該半導體處理系統係包含一氣體注入系統，其包含一使用一載送氣體而將該前驅物輸送至一或多個反應室的前驅物輸送系統。
本發明提供之方法可在任何適合之設備中執行，包括在如圖1所示之一半導體處理系統的一實施例中。圖1係為可用於本發明一些實施例中之一電漿增強型原子層沉積（PEALD）設備的一示意圖。在此圖式中，藉由在一反應室（3）之內部（11）（反應區）中平行且彼此面對地設置一對導電平板電極（2、4），並將來自一電源（25）之RF功率（例如，13.56 MHz及/或27 MHz）施加至一側且將另一側（12）電性接地，可在該等電極之間生成一電漿。當然，在一前驅物被提供至該反應室的步驟期間，或在連續製程步驟間的沖洗期間，該半導體處理設備不需要生成電漿，且也不需要在該等步驟或沖洗期間施加RF功率至該等電極中之任一者。一溫度調節器可設置於一下部台（2）中，亦即該下部電極中。一基板（1）係置放於其上，且其溫度係保持恆定在一給定溫度。該上部電極（4）亦可作為一噴灑板，且各種氣體，諸如一電漿氣體、一反應物氣體及/或，若存在的話，一稀釋氣體，以及一前驅物氣體，可分別經由一氣體管線（21）及一氣體管線（22）以及經由該噴灑板（4）而引入至該反應室（3）中。另外，在該反應室（3）中，係提供一具有一排氣管線（7）的圓管（13），且該反應室（3）之內部（11）中之氣體係經由該圓管而排出。另外，一轉移室（5）係設置於該反應室（3）下方且具備一氣體密封管線（24），以經由該轉移室（5）之內部（16）而將密封氣體引入至該反應室（3）之內部（11）中，其中係提供用於分開該反應區及該轉移區的一分離板（14）。
應注意，一晶圓可藉以轉移至或自該轉移室（5）的一閘閥係於此圖中省略。該轉移室亦設置有一排氣管線（6）。在一些實施例中，該氧化矽之沉積及表面處理係在相同的反應空間中執行，以使得所有步驟可連續地進行，不需要排空反應室、抽空反應室或將該基板暴露至大氣中的中間步驟。
圖2顯示一包含一間隙部件（210）之基板（200）的一示意圖。該間隙部件（210）包含一上部部分（211）及一下部部分（212）。該上部部分（211）包含一上表面，且該下部部分（212）包含一下表面。藉由使該基板（200）承受一第一電漿處理及一第二電漿處理，可使該上表面實質上受到抑制。換言之，相較於該下表面，該第一及該第二電漿處理可適當地使該上表面對一前驅物較不具反應性。
圖3顯示如本文所述之方法之實施例的一示意圖。該方法包含一將一基板定位於一基板支座上之步驟（311）。該基板包含一間隙部件。該基板係接著承受一如本文所述的電漿處理（312）。可選地，該反應室接著使用一電漿後沖洗（315）而進行沖洗。沖洗可，例如藉由一諸如一稀有氣體的實質上惰性氣體來完成。示例性惰性氣體包括He、Ne、Ar、Xe及Kr。該方法進一步包括一藉由本文所述之技術而在該間隙部件的該下表面上沉積一含矽材料的步驟（316）。可選地，該反應室係接著使用一沉積後沖洗（317）而進行沖洗。應理解，在該等沖洗期間，沒有電漿生成於該反應室中。自使該基板承受一電漿處理（312）至該在該間隙部件之該下表面上沉積一含矽材料之步驟（316）的步驟，係可選地重複（319）一或多次，藉此導致包含隨後之電漿處理及緊接著之一沉積步驟的複數個超循環。可選地，隨後之超循環係藉由一沖洗而分開。因此，一含矽材料係沉積於該間隙部件中。當一所需量的材料已沈積於該間隙中時，方法結束（318）。
圖4顯示如本文所述方法之一實施例的一示意圖。該方法包括一將一基板定位於一基板支架上的步驟（411）。該基板包含一間隙部件。該基板係接著承受一如本文所述的第一電漿處理（412）。可選地，該反應室係接著使用一電漿間沖洗（413）而進行沖洗。沖洗可，例如藉由一諸如一稀有氣體的實質上惰性氣體來完成。示例性惰性氣體包括He、Ne、Ar、Xe及Kr。該方法進一步包含一使該基板承受一如本文所述之第二電漿處理的步驟（414）。可選地，該反應室係接著使用一電漿後沖洗（415）而進行沖洗。該方法進一步包括一藉由如本文所述的技術而將一含矽材料沉積於該間隙部件之該下表面上的步驟（416）。可選地，該反應室係接著使用一沉積後沖洗（417）而進行沖洗。應理解，在該等沖洗期間，沒有電漿生成於該反應室中。自使該基板承受一第一電漿處理（412）至該在該間隙部件之該下表面上沉積一含矽材料之步驟的步驟，係可選地重複（419）一或多次，藉此導致包含隨後之第一及第二電漿處理及緊接之一沉積步驟的複數個超循環。因此，一含矽材料係沉積於該間隙部件中。當一所需量的含矽材料已沈積於該間隙中時，方法結束（418）。
圖5顯示用於在一基板中所包含之一間隙部件的下表面上選擇性沉積一含矽材料的方法之一部分之實施例的一示意圖。圖5中所示方法之部分係對應於圖3中所示之該在一下表面上沉積一含矽材料的步驟（316）及/或對應於圖4中所示之該在一下表面上沈積一含矽材料的步驟（416），且係在一使該基板承受一電漿處理的步驟之後、或在一使該基板承受一第一電漿處理及使該基板承受一第二電漿處理的步驟之後、或可選地在緊接於此類步驟的一沖洗之後開始（511）。該基板係暴露至如本文所述之化學吸附於該下表面上的一矽前驅物（512）。可選地，該反應室接著進行沖洗(513)。該方法接著包含一使該基板承受一第三電漿處理的步驟（514）。可選地，該反應室接著進行沖洗(515)。應理解，在該等沖洗期間，沒有電漿生成於該反應室中。自將該基板暴露至一矽前驅物（512）至該使該基板承受一第三電漿處理之步驟（514）的步驟，係可選地重複（517）一或多次，藉此導致複數個子循環。因此，一含矽材料係沉積於該間隙部件中。當一所需量之含矽材料已沈積於該間隙中時，方法結束（516）。
圖6顯示藉由如本文所述方法之一實施例而沉積於一間隙部件中之氧化矽的一穿透式電子顯微鏡（TEM）顯微照片。特別地是，係使用包含依序電漿預處理的複數個超循環及將氧化矽選擇性沉積於該下表面上的步驟。該等電漿預處理係包括一將該基板暴露至一氮電漿之步驟及將該基板暴露至一氬電漿之後續步驟。在該氮電漿期間，係使用一流速800 sccm之N 2，係使用一300 W之電漿功率（亦即射頻（RF）功率），該N 2電漿係維持8秒，且係使用一2秒之電漿間沖洗時間。在該氬電漿期間，係使用一流速3.7 slm之Ar，係使用一500 W之電漿功率（RF功率），該氬電漿係使用8秒，且係使用一5秒之電漿後沖洗時間。二異丙基胺基三矽烷胺係使用作為一矽前驅物。該矽前驅物後脈衝電漿處理係包含將該基板暴露至一O 2電漿。在該O 2電漿期間，係使用一800 sccm之O 2流速，且係使用一100 W之電漿功率（RF功率）。該O 2電漿係維持1秒。在該O 2電漿完成後，該反應室係進行沖洗2秒。上述之製程係重複100個超循環。該反應室維持在5 Torr的壓力，且該基板維持在300°C的溫度。藉由使用此類製程，在該等間隙部件之未鈍化下部部分處係獲得一每循環2.29 Å/循環的生長，以及一每循環0.93 Å/循環的生長。因此，於該間隙部件中由下而上的生長可獲得一出乎意料高的生長速率。
於圖6的製程中，在包含一矽前驅物-矽前驅物後脈衝電漿處理之每一個子循環之後，係使用一電漿預處理，亦即一電漿抑制。替代地，該電漿預處理可僅每若干個子循環重複，例如每3個子循環、每5個子循環、每10個子循環、每20個子循環或每50個子循環。此類之替代製程流程儘管係以頂部-底部選擇性作為代價，但可有利地提高生產量，降低電漿誘導損傷，例如Si或Ge氧化。
圖7顯示可用於實行如本文所述方法的一電漿增強型原子層沉積（PEALD）設備（700）之實施例的選定組件。該裝置（700）包含一氣體管線（710）、一旁通閥（720）、一旁通管線（730）、一反應器（740）及一排氣管線（750）。此類包含一旁通閥（720）的設備係可適當地增加在如本文所述方法的生產量。特別地是，該旁通閥（720）可用於容許連續氣體流動，即使在該反應室中不需要一特定製程氣體時亦然。因此，使用一旁通閥（720）可容許在處理多個晶圓期間避免使用氣體穩定步驟，且可使為了處理步驟而切換至不同氣體組成更為容易，進而提高生產量。
此外，該旁通閥係允許某些氣體的連續流動，且因避免了壓力脈衝槽線，因此可減少顆粒污染。再者，流動可以旁通模式開始，且可因此防止在開始時初始粒子爆裂至腔室（第一晶圓效應、預配方需求等）。
該氣體管線（710）可為運送本文所述氣體中之任一者的管線，諸如一前驅物氣體管線、或一惰性氣體管線、或一氮氣氣體管線、或一氧氣氣體管線。有利地，該設備（700）包含多個氣體管線，諸如一前驅物氣體管線、一惰性氣體管線、一氮氣氣體管線及一氧氣氣體管線。
因此，在一些實施例中，在該使該基板承受一電漿預處理之步驟期間，該矽前驅物係通過一矽前驅物旁通管道而轉移。
另外或替代地，在該將該基板暴露至一矽前驅物的步驟期間，一電漿氣體係通過一電漿氣體旁通管道而轉移。
在一些實施例中，在該沉積一含矽材料的步驟期間，於該電漿預處理期間所使用的電漿氣體係使用一旁通閥而轉移。
在一些實施例中，在該電漿預處理期間及在該將該基板暴露至一矽前驅物後脈衝電漿處理的步驟期間，該矽前驅物係使用一旁通閥而轉移。
在一些實施例中，在該使該基板承受一電漿預處理的步驟期間及在該將該基板暴露至一矽前驅物的步驟期間，於該將該基板暴露至一矽前驅物後脈衝電漿處理的步驟期間所使用的電漿氣體係通過一旁通閥而轉移。
本文所述之示例實施例並未限制本發明之範疇，由於此等實施例僅為本發明之實施例的示例，本發明之範疇係由文後申請專利範圍及其法定等同項所界定。任何等效實施例旨在本發明之範疇內。實際上，除本發明所示及所述者以外，所屬技術領域中具有通常知識者可由本說明書明白本揭露之各種修改，諸如所述元件之替代可用組合。此類修改及實施例亦意欲落在文後申請專利範圍的範疇內。
在本發明中，在條件及/或結構未指定之情況下，所屬技術領域中具有通常知識者鑒於本說明可容易地提供此類屬於常規實驗事項之條件及/或結構。
1:基板 2:下部台/導電平板電極 3:反應室 4:上電極/導電平板電極 5:轉移室 6:排氣管線 7:排氣管線 11:反應室的內部 12:電性接地側 13:圓管 14:分隔板 16:轉移室的內部 21:氣體管線 22:氣體管線 24:氣體密封管線 25:電源 200:基板 210:間隙部件 211:上部部分 212:下部部分 311:在一基板支座上定位一基板的步驟 312:使該基板承受一電漿處理的步驟 315:電漿後沖洗 316:在一下表面上沉積一材料的步驟 317:沉積後沖洗 318:方法結束 319:重複 411:在一基板支座上定位一基板的步驟 412:使該基板承受一第一電漿處理的步驟 413:電漿間沖洗 414:使該基板承受一第一電漿處理的步驟 415:電漿後沖洗 416:在一下表面上沈積一含矽材料的步驟 417:沈積後沖洗 418:方法結束 419:重複 511:方法開始 512:將一基板暴露至一矽前驅物的步驟 513:沖洗 514:將該基板暴露至一前驅物後暴露電漿處理的步驟 515:沖洗 516:方法結束 517:重複 700:設備 710:氣體管線 720:旁通閥 730:旁通管線 740:反應器 750:排氣管線
當結合下列闡釋性圖式考慮時，可藉由參考實施方式及申請專利範圍而有對本發明之實施例的更完整瞭解。 ［圖1］係為根據本發明至少一實施例之適於沉積一結構及/或執行一方法的一電漿增強原子層沉積（PEALD）設備之示意圖。 ［圖2］顯示一包含一間隙部件（210）之基板（200）的一示意圖。 ［圖3］顯示如本文所述之方法之實施例的一示意圖。 ［圖4］顯示如本文所述方法之一實施例的一示意圖。 ［圖5］顯示用於在一基板中所包含之一間隙部件的下表面上選擇性沉積一含矽材料的方法之一部分之實施例的一示意圖。 ［圖6］顯示藉由如本文所述方法之一實施例而沉積於一間隙部件中之氧化矽的一穿透式電子顯微鏡（TEM）顯微照片。 所有圖式係遵守以下編號：1–基板； 2–下部台/導電平板電極；3–反應室；4–上電極/導電平板電極；5–轉移室；6–排氣管線；11–反應室的內部；12–電性接地側；13–圓管；14–分隔板；16–轉移室的內部；7–排氣管線；21–氣體管線；22–氣體管線；24–氣體密封管線；25–電源；200–基板；210–間隙部件；211–上部部分；212–下部部分；311–在一基板支座上定位一基板的步驟；312–使該基板承受一電漿處理的步驟；315–電漿後沖洗；316–在一下表面上沉積一材料的步驟；317–沉積後沖洗；318–方法結束；319–重複；411–在一基板支座上定位一基板的步驟；412–使該基板承受一第一電漿處理的步驟；413–電漿間沖洗；414–使該基板承受一第一電漿處理的步驟；415–電漿後沖洗；416–在一下表面上沈積一含矽材料的步驟；417–沈積後沖洗；418–方法結束；419–重複；511–方法開始；512–將一基板暴露至一矽前驅物的步驟；513–沖洗；514–將該基板暴露至一前驅物後暴露電漿處理的步驟；515–沖洗；516–方法結束；517–重複。 將瞭解，圖式中之元件係為了簡明及清楚起見而繪示且不必然按比例繪製。舉例而言，圖式中之一些元件的尺寸可能相對於其他元件而特別放大，以幫助改善對所繪示本發明實施例的理解。
1:基板
2:下部台/導電平板電極
3:反應室
4:上電極/導電平板電極
5:轉移室
6:排氣管線
7:排氣管線
11:反應室的內部
12:電性接地側
13:圓管
14:分隔板
16:轉移室的內部
21:氣體管線
22:氣體管線
24:氣體密封管線
25:電源

Claims (20)

  1. 一種用於填充基板表面上之間隙部件之方法，該方法包括： - 一在一反應室中將一基板定位在一基板支座上的步驟，該基板包括一或多個間隙部件，該一或多個間隙部件包括一上部部分及一下部部分，該上部部分包括一上表面且該下部部分包括一下表面； - 一使該基板承受一電漿預處理的步驟，藉此抑制該上表面，並同時使該下表面實質上不受影響；及 - 一在該下表面上選擇性沉積一含矽材料的步驟； 其中該在該下表面上選擇性沉積一含矽材料的步驟係包括一循環製程，該循環製程包括複數個子循環，一子循環依給定順序包括： - 一使該基板在一矽前驅物脈衝中暴露至一矽前驅物的步驟，藉此在該下表面上形成化學吸附矽前驅物；及 - 一將該基板暴露至一矽前驅物後脈衝電漿處理的步驟，藉此允許電漿中包括之一或多種活性物種與該下表面上之該化學吸附矽前驅物反應； 其中該矽前驅物包括一胺基及二或多個矽原子。
  2. 如請求項1所述之方法，其中該胺基係選自NH 2、NHR i及NR iR ii，且R i及R ii中之至少一者係為一C 1至C 4烷基。
  3. 如請求項1或2所述之方法，其中該矽前驅物包括選自由一胺基矽烷、一矽烷胺及一環矽氧烷組成之列表的一化合物。
  4. 如請求項1所述之方法，其中該矽前驅物包括一烷基胺基矽烷。
  5. 如請求項1所述之方法，其中該矽前驅物包括選自SiR 1R 3R 4-SiR 2R 5R 6、SiR 1R 3R 4-SiR 5R 6-SiR 2R 7R 8及SiR 1R 3R 4-SiR 2R 5-SiR 6R 7R 8的一化合物，其中R 1及R 2係為NR 9R 10，且R 3、R 4、R 5、R 6、R 7、R 8、R 9及R 10係獨立選自H及一C 1至C 4烷基。
  6. 如請求項1或2所述之方法，其中該矽反應前驅物包括一矽烷胺。
  7. 如請求項6所述之方法，其中該矽前驅物包括一可由一根據分子式(1)之化學結構表示的化合物
    Figure 03_image001
    (1) 其中R 11及R 12係獨立選自H及一C 1至C 4烷基。
  8. 如請求項1所述之方法，其中該矽前驅物包括一包括至少一胺基的環矽氧烷。
  9. 如請求項1至8中任一項所述之方法，其中該電漿預處理包括使該基板承受一惰性氣體電漿。
  10. 如請求項1至8中任一項所述之方法，其中該電漿預處理包括使該基板承受一含氮電漿。
  11. 如請求項1至8中任一項所述之方法，其中該電漿預處理包括使該基板承受一含氮及氫電漿。
  12. 如請求項1至8中任一項所述之方法，其中該電漿預處理包括使該基板承受一第一電漿處理及使該基板承受一第二電漿處理。
  13. 如請求項12所述之方法，其中該第一電漿處理包括在該反應室中生成一含氮電漿。
  14. 如請求項13所述之方法，其中該含氮電漿係為一含N 2之電漿。
  15. 如請求項12至14中任一項所述之方法，其中該第二電漿處理包括在該反應室中生成一含惰性氣體電漿。
  16. 如請求項1至15中任一項所述之方法，其包括執行複數個超循環，一超循環包括： - 該使該基板承受一電漿預處理的步驟；及 - 該在該下表面上選擇性沉積一含矽材料的步驟。
  17. 如請求項1至16中任一項所述之方法，其中該矽前驅物後脈衝電漿處理包括在該反應室中生成一含氧電漿，且其中該含矽材料包括氧化矽。
  18. 如請求項1至17中任一項所述之方法，其中在該使該基板承受一電漿預處理的步驟期間，該矽前驅物係通過一矽前驅物旁通管道而轉移。
  19. 如請求項1至18中任一項所述之方法，其中在該將該基板暴露至一矽前驅物的步驟期間，一電漿氣體係通過一電漿氣體旁通管道而轉移。
  20. 一種半導體處理設備，其包括： - 一反應室，包括一基板支座，用於支撐一包括一或多個間隙部件的基板； - 一加熱器，經建構且配置成在該反應室中加熱該基板； - 一第一電漿氣體源，係經由一第一電漿氣體閥而與該反應室流體連通； - 一第二電漿氣體源，係經由一第二電漿氣體閥而與該反應室流體連接； - 一第三電漿氣體源，係經由一第三電漿氣體閥而與該反應室流體連接； - 一電漿模組，包括一射頻功率源，經建構且配置成在該反應室中生成一電漿； - 一或多個矽前驅物源，係經由一或多個前驅物閥而與該反應室流體連接；及 - 一控制器，經配置成使該設備執行一如請求項1至19中任一項所述之方法。
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KR20210127620A (ko) 2020-04-13 2021-10-22 에이에스엠 아이피 홀딩 비.브이. 질소 함유 탄소 막을 형성하는 방법 및 이를 수행하기 위한 시스템
KR20210128343A (ko) 2020-04-15 2021-10-26 에이에스엠 아이피 홀딩 비.브이. 크롬 나이트라이드 층을 형성하는 방법 및 크롬 나이트라이드 층을 포함하는 구조
US11821078B2 (en) 2020-04-15 2023-11-21 Asm Ip Holding B.V. Method for forming precoat film and method for forming silicon-containing film
US11996289B2 (en) 2020-04-16 2024-05-28 Asm Ip Holding B.V. Methods of forming structures including silicon germanium and silicon layers, devices formed using the methods, and systems for performing the methods
TW202140846A (zh) 2020-04-17 2021-11-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 注入器、及垂直熔爐
KR20210130646A (ko) 2020-04-21 2021-11-01 에이에스엠 아이피 홀딩 비.브이. 기판을 처리하기 위한 방법

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