CN102576729A - 用于基于氮化镓或其它氮化物的功率装置的含有锗的低欧姆触点 - Google Patents
用于基于氮化镓或其它氮化物的功率装置的含有锗的低欧姆触点 Download PDFInfo
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H01L29/2003—Nitride compounds
Abstract
本发明涉及一种设备,其包括衬底(120)、所述衬底上的III族氮化物层(102、104、106)及所述III族氮化物层上的电触点(108a、108b)。所述电触点包括具有多个导电材料层(110到116)的堆叠,且所述堆叠中的所述层中的至少一者包括锗。所述堆叠中的所述层可包括接触层(116),其中所述接触层包括铝铜。所述堆叠可包括钛或钛合金层、铝或铝合金层,以及锗或锗合金层。所述堆叠中的所述层中的至少一者可包括具有在约1%与约5%之间的锗含量的铝或钛合金。
Description
对相关申请案的交叉参考及优先权主张
本申请案根据35U.S.C.§119(e)主张2009年12月6日申请的第61/284,299号美国临时专利申请案的优先权,所述申请案特此以引用的方式并入本文中。
技术领域
本发明大体上涉及半导体装置。且更特定来说,本发明涉及用于基于氮化镓或其它氮化物的功率装置的含有锗的低欧姆触点。
背景技术
正研究各种III-V族化合物以用于高功率电子应用。这些化合物包括“III族氮化物”,例如氮化镓(GaN)、氮化铝镓(AlGaN)及氮化铝铟镓(AlInGaN)。这些化合物可用于形成用于高功率高电压应用中的高电子迁移率晶体管(HEMT)或其它装置。
高性能HEMT通常需要到晶体管的源极及漏极的较低且高度稳定的特定接触电阻。到HEMT的当前欧姆触点通常使用钛-铝-钛-金金属堆叠、钛-铝-钛钨-金金属堆叠或钛-铝-钼-金金属堆叠。钨(W)及钼(Mo)几乎是不溶于金中的,从而使它们成为用于分隔金(Au)与铝(Al)的优秀势垒。这可帮组防止形成金化铝(Al2Au)状态,其可引起表面粗化及高电阻率。钛(Ti)及铝通常用于欧姆触点的形成中,因为它们互相反应且与氮反应以形成具有低电阻率的氮化钛(TiN)及氮化钛铝(TiAlN)层。
近来,已使用硅(Si)来重掺杂氮化镓或氮化铝镓层以作为进一步降低特定接触电阻的方式。然而,此类型的实施方案通常需要非常高温度的退火(例如高于1200℃),以活化氮化镓或氮化铝镓层中的硅施主。具有低硅原子部分的铝硅合金也已用于降低触点的特定电阻。在退火期间,硅扩散到氮化镓或氮化铝镓层且掺杂这些层,从而降低它们的特定接触电阻。
发明内容
附图说明
为了更完整地理解本发明及其特征,现在参考结合附图进行的以下描述,在附图中:
图1说明根据本发明的具有用于III族氮化物装置的低欧姆触点的实例半导体结构;
图2A到2E说明根据本发明的用于形成具有用于III族氮化物装置的低欧姆触点的半导体结构的实例技术;且
图3说明根据本发明的用于形成具有用于III族氮化物装置的低欧姆触点的半导体结构的实例方法。
具体实施方式
下述的图1到3及本专利文件中的用于描述本发明的原理的各种实施例仅作为说明,且不应以任何限制本发明的范围的方式加以解释。所属领域的技术人员将理解,本发明的原理可在任何类型的经合适地布置的装置或系统中实施。
一般来说,本发明描述使用锗(Ge)及各种锗合金(例如铝锗(AlGe)及钛锗(TiGe))来改进用于高电子迁移率晶体管(HEMT)及其它III族氮化物功率装置的欧姆触点。“III族氮化物”指代使用氮及至少一种III族元素形成的化合物。实例III族元素包括铟、镓及铝。实例III族氮化物包括氮化镓(GaN)、氮化铝镓(AlGaN)、氮化铟铝(InAlN)、氮化铟铝镓(InAlGaN)、氮化铝(AlN)、氮化铟(InN)及氮化铟镓(InGaN)。在用于欧姆触点的层的堆叠中包含锗可帮助降低到III族氮化物HEMT或其它结构的接触电阻。本发明还描述铝铜(AlCu)接触层(而不是金)的使用,其可帮助避免金化铝相形成,且提供可与基于硅的CMOS电路相当的接触方案。
图1说明根据本发明的具有用于III族氮化物装置的低欧姆触点的实例半导体结构100。在此实例中,欧姆触点用于到III族氮化物功率晶体管(例如HEMT)的源极及漏极的电连接。
如图1中所展示,半导体结构100包括缓冲层102及一个或一个以上势垒层104到106。缓冲及势垒层102到106中的每一者可由任何合适材料形成。举例来说,缓冲层102可由氮化镓、氮化铝镓或其它III族氮化物材料形成。并且,隔板层104到106中的每一者可由氮化镓、氮化铝镓或其它III族氮化物材料形成,且不同的材料可用于不同的势垒层中。举例来说,势垒层104可表示氮化镓层,且势垒层106可表示氮化铝镓层。氮化铝镓缓冲层中的铝浓度可比氮化铝镓势垒层中的铝浓度小得多。层102到106中的每一者还可以任何合适方式形成。举例来说,层102到106中的每一者可表示使用金属有机物化学气相沉积(MOCVD)或分子束外延(MBE)技术形成的外延层。
一个或一个以上欧姆触点108a到108b形成于势垒层106上。在此实例中,欧姆触点108a到108b中的每一者由导电层110到116的堆叠来形成。一般来说,导电层110到114包括含有锗或一种或一种以上锗合金的至少一个层,且导电层116可包括铝铜合金来作为接触层。作为特定实例,导电层110到116可形成:
·钛-铝锗-钛-铝铜堆叠;
·铝锗-钛-铝-铝铜堆叠;
·锗-铝-钛-铝铜堆叠;
·钛-锗-铝-铝铜堆叠;
·钛锗铝-铝-铝铜堆叠;
·钛锗-铝-铝铜堆叠;或
·钛-铝锗-铝-铝铜堆叠。
这些仅作为实例而提供。此处可使用包括锗或某一形式的锗合金或化合物的各种各样堆叠。还注意,四个导电层的使用不是所需的。
在特定实施例中,铝铜接触层116中的铜含量可在约0.5%与约1.0%之间,且铝铜接触层的厚度可在约100nm与约150nm之间。并且,钛层的厚度可在约10nm与约20nm之间、锗层的厚度可在约5nm与约15nm之间,且钛锗铝层的厚度可在约10nm与约20nm之间。此外,钛锗层的厚度可在约10nm与约20nm之间,且铝层的厚度可在约50nm与约100nm之间。此外,任何铝或钛合金中的锗成分可在约1%与约5%之间。此外,基于铝锗的合金可用于n型触点,因为锗对于氮化镓或氮化铝镓是n型掺杂物。
铜的添加(例如小于约2%的原子量)在降低电迁移率及排放应力时可为有用的。锗与铜在顶层116上的反应可进一步降低接触电阻、增强热稳定性及减少潜在的氧化。
导电层110到116中的每一者可以任何合适方式形成。举例来说,导电层110到116可使用任何合适沉积技术(例如溅镀)来沉积在势垒层106上。导电层110到116可接着(例如)通过使用光掩模来蚀刻以形成欧姆触点108a到108b。然而,可使用任何其它合适技术来形成欧姆触点108a到108b。
栅极触点118也形成在势垒层106上。栅极触点118表示HEMT或其它III族氮化物装置的栅极。栅极触点118可使用任何合适的导电材料且以任何合适方式来形成。举例来说,栅极触点118可通过遮蔽欧姆触点108a到108b且沉积及蚀刻导材料以形成触点118来形成。
缓冲层102在此处可形成在其它层或结构上。举例来说,缓冲层102可形成在衬底120及一个或一个以上介入层122上。衬底120表示在其上形成其它层或结构的任何合适半导体结构。举例来说,衬底120可表示硅<111>、蓝宝石、碳化硅或其它半导体衬底。衬底120还可具有任何合适大小及形状,例如直径在三与十二英寸之间的晶片(但可使用其它大小)。介入层122可包括提供任何合适功能性的任何合适层。举例来说,介入层122可包括成核层及一个或一个以上热管理层。
在图1中,锗的使用可具有作为对一个或一个以上III族氮化物层的高掺杂物的巨大潜力,且因此可进一步降低接触电阻。从理论上来说,锗被预期为富含氮的氛围中的优秀施主,且其在氮化镓中的溶度可超过1E21/cm3,只要氮化铝镓中的铝摩尔分数低于30%即可。
虽然图1说明具有用于III族氮化物装置的低欧姆触点的半导体结构100的一个实例,但可对图1做出各种改变。举例来说,虽然上文描述特定材料及制造工艺,但可使用任何其它材料及制造工艺来形成半导体结构100的各种层或其它结构。并且,虽然已描述特定大小或尺寸,但半导体结构100中的每一层或其它组件可具有任何合适大小、形状及尺寸。
图2A到2E说明根据本发明的用于形成具有用于III族氮化物装置的低欧姆触点的半导体结构的实例技术。如图2A中所展示,一个或一个以上介入层122形成在衬底120上。介入层122可包括任何数目的层,各自由任何合适材料形成。举例来说,介入层122可包括由一种或一种以上III族氮化物材料形成的热应力管理层。作为特定实例,热应力管理层可使用具有不同镓浓度的氮化铝镓层的组合来形成。可将低温氮化铝层插入到所述热应力管理层中。也可使用热应力管理层的其它配置,例如包括氮化铝/氮化铝镓的超晶格结构(多个薄层,每一者的厚度为几纳米)的配置。热应力管理层最少可具有两个层,且那些层可重复两次、三次或三次以上。取决于所形成的材料,介入层122还可使用任何合适技术来形成。实例技术可包括物理气相沉积(PVD)、化学气相沉积(CVD)、等离子体增强CVD(PECVD)、MOCVD或MBE。
如图2B中所展示,缓冲层102及一个或一个以上势垒层104到106形成在所述结构上。所述缓冲及势垒层102到106中的每一者可由任何合适材料且以任何合适方式来形成。举例来说,所述缓冲及势垒层102到106中的每一者可由一个或一个以上外延III族氮化物层来形成。
如图2C中所展示,多个导电层110到116形成在势垒层106上。导电层110到114中的每一者可由任何合适材料形成,且层110到114中的至少一者包括锗。并且,导电层116可由铝铜形成。
在一些实施例中,层110到116可使用沉积,通过在室温(RT)与约300℃之间的温度下进行溅镀来形成。所述制造工艺可包括使用氩(Ar+)离子的预沉积蚀刻来减少或消除表面污染物(例如碳及有机物残留)以及获得良好的金属附着。合金化可用于且可实施于快速热退火系统中,例如在约三十秒到一分钟的周期内在氮氛围中在约700℃与约1000℃之间的温度下。在特定实施例中,可使用两步骤退火工艺。第一步骤可在较低温度(例如低于约750℃)下实施,以将锗层扩散到一个或一个以上氮化镓或氮化铝镓层中。第二步骤可为高温退火(例如至多达约900℃,持续约三十秒),以形成对到氮化镓或氮化铝镓的欧姆触点负责的氮化铝钛共晶体。锗在氮化镓/氮化铝镓层中的扩散可重沉积这些层,且进一步降低接触电阻。
如图2D中所展示,导电层110到116经蚀刻或以其它方式经处理以形成欧姆触点108a到108b。欧姆触点108a到108b中的每一者可具有任何合适大小及形状,且不同的欧姆触点108a到108b可具有不同的大小或形状。欧姆触点108a到108b可以任何合适方式形成。举例来说,光致抗蚀剂材料层可沉积在导电层110到116上,且经图案化以产生穿过所述光致抗蚀剂材料的开口。可接着执行蚀刻,以穿过光致抗蚀剂材料中的开口来蚀刻导电层110到116。
如图2E中所展示,栅极触点118形成在导电层110到116上。栅极触点118可使用任何合适的导电材料且以任何合适方式来形成。举例来说,欧姆触点108a到108b可使用掩模来覆盖,且导电材料可沉积在欧姆触点108a到108b之间,且经蚀刻以形成栅极触点118。
在此工艺期间的某一点处,层102到106中的一者或一者以上可经进一步经处理以形成用于HEMT或其它III族氮化物装置中的结构。举例来说,可执行植入、扩散或其它处理操作以形成层102到106中的一者或一者以上中的晶体管的经掺杂的源极及漏极区。可执行其它或额外处理步骤以形成用于其它或额外III族氮化物装置的结构。
虽然图2A到2E说明用于形成具有用于III族氮化物装置的低欧姆触点的半导体结构的技术的一个实例,但可对图2A到2E做出各种改变。举例来说,虽然上文描述特定材料及处理技术,但所述结构中的每一层或其它组件可由任何合适材料且以任何合适方式来形成。
图3说明根据本发明的用于形成具有用于III族氮化物装置的低欧姆接触的半导体结构的实例方法300。如图3中所展示,在步骤302处,在衬底上形成一个或一个以上III族氮化物层。举例来说,这可包括在衬底102上形成成核层、热应力管理层、缓冲层及势垒层。然而,取决于实施方案,可省略这些层中的一者或一者以上。在此步骤期间,至少一种III族氮化物材料可用于至少一个层中,例如在一个或一个以上III族氮化物外延层中。在步骤304处,处理一个或一个以上III族氮化物层。举例来说,这可包括沉积至少一个III族氮化物层的部分以形成晶体管的源极及漏极区。然而,此处可执行任何其它或额外处理步骤。
在步骤306处,在一个或一个以上III族氮化物层上形成导电堆叠。举例来说,这可包括在所述势垒层上沉积不同的导电层110到116,例如具有铝或钛的导电层。导电层110到114中的至少一者包括锗,且接触层116可包括铝铜。在步骤308处,处理导电堆叠以形成用于一种或一种以上III族氮化物装置的一个或一个以上欧姆触点。举例来说,这可包括蚀刻所述导电堆叠以形成欧姆触点108a到108b。欧姆触点108a到108b可与一种或一种以上III族氮化物装置的晶体管或其它结构的源极及漏极区形成电接触。
此时,在步骤310处,可完成一个或一个以上III族氮化物装置的形成。举例来说,这可包括在势垒层上形成栅极触点118。这可完成一个或一个以上III族氮化物HEMT或其它结构的形成。
虽然图3说明用于形成具有用于III族氮化物装置的低欧姆触点的半导体结构的方法300的一个实例,但是可对图3做出各种改变。举例来说,虽然展示为一系列的步骤,但是图3中的各个步骤可重叠、并行地发生或以不同的顺序发生。
陈述已用于此专利文献中的某些词及短语的定义可为有利的。术语“包括”及“包含”,以及其派生词,表示没有限制的包括。术语“或”是包括性的,表示及/或。
虽然本发明已描述了某些实施例及大体相关的方法,但是对这些实施例及方法的更改及排列对所属领域的技术人员来说将是显而易见的。因此,对实例实施例的以上描述不限定或限制本发明。在不脱离如所附权利要求书限定的本发明的精神及范围的情况下,其它概念、代替及更改也是可能的。
Claims (20)
1.一种设备,其包含:
衬底;
III族氮化物层,其位于所述衬底上;及
电触点,其位于所述III族氮化物层上,所述电触点包含具有多个导电材料层的堆叠,所述堆叠中的所述层中的至少一者包含锗。
2.根据权利要求1所述的设备,其中所述堆叠中的所述层包括接触层,所述接触层包含铝铜。
3.根据权利要求2所述的设备,其中:
所述接触层具有在约0.5%与约1.0%之间的铜含量,且
所述接触层具有在约100nm与约150nm之间的厚度。
4.根据权利要求1所述的设备,其中所述堆叠包含:
钛或钛合金层;
铝或铝合金层;及
锗或锗合金层。
5.根据权利要求1所述的设备,其中所述堆叠中的所述层中的至少一者包含具有在约1%与约5%之间的锗含量的铝或钛合金。
6.根据权利要求1所述的设备,其中所述III族氮化物层包含缓冲层及至少一个势垒层,所述缓冲及势垒层包含III族氮化物外延层。
7.根据权利要求1所述的设备,其中:
所述电触点包含多个电触点中的一者;且
所述设备进一步包含所述电触点之间的栅极触点。
8.一种系统,其包含:
半导体结构,其包含衬底及所述衬底上的III族氮化物层;
III族氮化物集成电路装置,其在所述III族氮化物层中或上;及
多个电触点,其与所述III族氮化物集成电路装置电连接,每一电触点包含具有多个导电材料层的堆叠,所述堆叠中的所述层中的至少一者包含锗。
9.根据权利要求8所述的系统,其中所述III族氮化物集成电路装置包含III族氮化物高电子迁移率晶体管HEMT。
10.根据权利要求8所述的系统,其中所述堆叠中的所述层包括接触层,所述接触层包含铝铜。
11.根据权利要求10所述的系统,其中:
所述接触层具有在约0.5%与1.0%之间的铜含量;且
所述接触层具有在约100nm与约150nm之间的厚度。
12.根据权利要求8所述的系统,其中所述堆叠包含:
钛或钛合金层;
铝或铝合金层;及
锗或锗合金层。
13.根据权利要求8所述的系统,其中所述堆叠中的所述层中的至少一者包含具有在约1%与约5%之间的锗含量的铝或钛合金。
14.根据权利要求8所述的系统,其中所述III族氮化物层包含缓冲层及至少一个势垒层,所述缓冲及势垒层包含III族氮化物外延层。
15.根据权利要求8所述的系统,其中所述III族氮化物集成电路装置进一步包含所述电触点之间的栅极触点。
16.一种方法,其包含:
在衬底上形成III族氮化物层;及
在所述III族氮化物层上形成电触点,所述电触点包含具有多个导电材料层的堆叠,所述堆叠中的所述层中的至少一者包含锗。
17.根据权利要求16所述的方法,其进一步包含:
使用所述III族氮化物层形成III族氮化物集成电路装置,所述电触点与所述III族氮化物集成电路装置电连接。
18.根据权利要求16所述的方法,其中所述堆叠中的所述层包括接触层,所述接触层包含铝铜。
19.根据权利要求18所述的方法,其中:
所述接触层具有在约0.5%与1.0%之间的铜含量;且
所述接触层具有在约100nm与约150nm之间的厚度。
20.根据权利要求16所述的方法,其中所述堆叠中的所述层中的至少一者包含具有在约1%与约5%之间的锗含量的铝或钛合金。
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Also Published As
Publication number | Publication date |
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WO2011084270A2 (en) | 2011-07-14 |
TW201131762A (en) | 2011-09-16 |
WO2011084270A3 (en) | 2011-09-29 |
US20110140173A1 (en) | 2011-06-16 |
JP2013514662A (ja) | 2013-04-25 |
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