CN117525112A - 高电子迁移率晶体管及其制作方法 - Google Patents

高电子迁移率晶体管及其制作方法 Download PDF

Info

Publication number
CN117525112A
CN117525112A CN202210979121.XA CN202210979121A CN117525112A CN 117525112 A CN117525112 A CN 117525112A CN 202210979121 A CN202210979121 A CN 202210979121A CN 117525112 A CN117525112 A CN 117525112A
Authority
CN
China
Prior art keywords
carbon concentration
buffer layer
layer
electron mobility
high electron
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202210979121.XA
Other languages
English (en)
Inventor
郭俊良
陈彦兴
陈彦纶
沈睿纮
杨宗穆
王俞仁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
United Microelectronics Corp
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Publication of CN117525112A publication Critical patent/CN117525112A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/207—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds further characterised by the doping material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1066—Gate region of field-effect devices with PN junction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

本发明公开一种高电子迁移率晶体管及其制作方法，其中该制作高电子迁移率晶体管(high electron mobility transistor,HEMT)的方法为，主要先形成一缓冲层于基底上，形成一阻障层于该缓冲层上，形成一P型半导体层于该阻障层上，形成一栅极电极于该P型半导体层上，再形成一源极电极以及一漏极电极于该栅极电极两侧。其中缓冲层又细部包含一下半部具有第一碳浓度以及一上半部包含第二碳浓度，第二碳浓度小于第一碳浓度，且下半部厚度小于该上半部厚度。

Description

高电子迁移率晶体管及其制作方法
技术领域
本发明涉及一种高电子迁移率晶体管及其制作方法。
背景技术
以氮化镓基材料(GaN-based materials)为基础的高电子迁移率晶体管具有于电子、机械以及化学等特性上的众多优点，例如宽能隙、高击穿电压、高电子迁移率、大弹性模数(elastic modulus)、高压电与压阻系数(high piezoelectric and piezoresistivecoefficients)等与化学钝性。上述优点使氮化镓基材料可用于如高亮度发光二极管、功率开关元件、调节器、电池保护器、面板显示驱动器、通信元件等应用的元件的制作。
发明内容
本发明一实施例揭露一种制作高电子迁移率晶体管(high electron mobilitytransistor,HEMT)的方法，其主要先形成一缓冲层于基底上，形成一阻障层于该缓冲层上，形成一P型半导体层于该阻障层上，形成一栅极电极于该P型半导体层上，再形成一源极电极以及一漏极电极于该栅极电极两侧。其中缓冲层又细部包含一下半部具有第一碳浓度以及一上半部包含第二碳浓度，第二碳浓度小于第一碳浓度，且下半部厚度小于该上半部厚度。
本发明另一实施例揭露一种高电子迁移率晶体管，其主要包含一缓冲层设于基底上，一阻障层设于该缓冲层上以及一阻障层设于缓冲层上，一P型半导体层设于阻障层上，一栅极电极设于P型半导体层上以及一源极电极与一漏极电极设于栅极电极两侧。其中缓冲层又细部包含一下半部具有第一碳浓度以及一上半部包含第二碳浓度，第二碳浓度小于第一碳浓度，且下半部厚度小于该上半部厚度。
附图说明
图1至图3为本发明一实施例制作高电子迁移率晶体管的方法示意图。
符号说明
12:基底
14:超晶格堆叠层
16:缓冲层
18:下半部
20:上半部
22:沟道区
24:阻障层
26:P型半导体层
28:保护层
30:栅极电极
32:源极电极
34:漏极电极
具体实施方式
请参照图1至图3，图1至图3为本发明一实施例制作高电子迁移率晶体管的方法示意图，其中图1与图3分别为本发明一实施例制作高电子迁移率晶体管的剖面示意图而图2则为图1中缓冲层与相对碳含量的放大示意图。如图1至图2所示，首先提供一基底12，例如一由硅、碳化硅或氧化铝(或可称蓝宝石)所构成的基底，其中基底12可为单层基底、多层基底、梯度基底或上述的组合。依据本发明其他实施例基底12又可包含一硅覆绝缘(silicon-on-insulator,SOI)基底。
然后于基底12表面形成一选择性核晶层(nucleation layer)(图未示)、一超晶格堆叠层14以及一缓冲层16。在一实施例中，核晶层可包含氮化铝(AlN)，超晶格堆叠层14可由氮化铝(AlN)与氮化铝镓(AlxGa1-xN)交替堆叠而成的复合层，而缓冲层16则包含III-V族半导体例如氮化镓，其厚度可藉于0.5微米至10微米之间。在一实施例中，可利用分子束外延制作工艺(molecular-beam epitaxy,MBE)、有机金属气相沉积(metal organicchemical vapor deposition,MOCVD)制作工艺、化学气相沉积(chemical vapordeposition,CVD)制作工艺、氢化物气相外延(hydride vapor phase epitaxy,HVPE)制作工艺或上述组合于基底12上形成超晶格堆叠层14与缓冲层16。
如图2所示，缓冲层16由下至上包含一下半部18、一上半部20以及最顶部一沟道区22，其中下半部18、上半部20以及沟道区22本质上均由氮化镓所构成，但下半部18与上半部20均掺杂有较高浓度的碳原子而沟道区22则可掺杂有较低浓度的碳原子或无任何掺杂(undoped)，且下半部18厚度较佳略小于上半部20厚度。
需注意的是，本实施例中下半部18的碳浓度较佳不同于或更具体而言较佳大于上半部20的碳浓度，而沟道区22的碳浓度则分别小于下半部18与上半部20的碳浓度。从细部来看，下半部18包含第一碳浓度，上半部20包含第二碳浓度，沟道区22包含第三碳浓度，其中沟道区22的第三碳浓度较佳小于上半部20的第二碳浓度以及下半部18的第一碳浓度且上半部20的第二碳浓度又较佳小于下半部18的第一碳浓度，或反过来看第一碳浓度较佳大于第二碳浓度且第一碳浓度与第二碳浓度又分别大于第三碳浓度。依据本发明一实施例，第一碳浓度较佳介于5.0×1018原子/立方厘米至1.0×1019原子/立方厘米，第二碳浓度较佳介于1.0×1018原子/立方厘米至4.0×1018原子/立方厘米，第三碳浓度则较佳介于1.0×1016原子/立方厘米至1.0×1017原子/立方厘米。
随后如图3所示，形成一阻障层24于缓冲层16表面。在本实施例中阻障层24较佳包含III-V族半导体例如N型氮化铝镓(AlxGa1-xN)，其中0<x<1，阻障层24较佳包含一由外延成长制作工艺所形成的外延层，且阻障层24可包含硅或锗的掺质。如同上述形成缓冲层16的方式，可利用分子束外延制作工艺(molecular-beam epitaxy,MBE)、有机金属气相沉积(metal organic chemical vapor deposition,MOCVD)制作工艺、化学气相沉积(chemicalvapor deposition,CVD)制作工艺、氢化物气相外延(hydride vapor phase epitaxy,HVPE)制作工艺或上述组合于缓冲层16上形成阻障层24。
然后先形成一图案化的P型半导体层26于阻障层16上，形成一保护层28于阻障层24及P型半导体层26上，再形成一栅极电极30于P型半导体层26上以及源极电极32与漏极电极34于栅极电极30两侧，其中P型半导体层26与栅极电极30可一同构成一栅极结构。在一实施例中，P型半导体层26较佳包含P型氮化镓，且可利用分子束外延制作工艺(molecular-beam epitaxy,MBE)、有机金属气相沉积(metal organic chemical vapor deposition,MOCVD)制作工艺、化学气相沉积(chemical vapor deposition,CVD)制作工艺、氢化物气相外延(hydride vapor phase epitaxy,HVPE)制作工艺或上述组合于阻障层24表面形成P型半导体层26，再利用光刻及蚀刻制作工艺去除部分P型半导体层26形成图案化的P型半导体层26。接着，可进行另一光刻及蚀刻制作工艺去除P型半导体层26上的部分保护层28形成凹槽(图未示)，形成一栅极电极30于凹槽内，去除P型半导体层26两侧的部分保护层28甚至部分阻障层24形成二凹槽，再分别形成源极电极32与漏极电极34于栅极电极30两侧。
在本实施例中，栅极电极30、源极电极32以及漏极电极34较佳由金属所构成，其中栅极电极30较佳由萧特基金属所构成而源极电极32与漏极电极34较佳由欧姆接触金属所构成。依据本发明一实施例，栅极电极30、源极电极32及漏极电极34可各自包含金、银、铂、钛、铝、钨、钯或其组合。在一些实施例中，可利用电镀制作工艺、溅镀制作工艺、电阻加热蒸镀制作工艺、电子束蒸镀制作工艺、物理气相沉积(physical vapor deposition,PVD)制作工艺、化学气相沉积制作工艺(chemical vapor deposition,CVD)制作工艺、或上述组合于上述凹槽内形成导电材料，然后再利用单次或多次蚀刻将电极材料图案化以形成栅极电极30、源极电极32以及漏极电极34。至此即完成本发明一实施例的一高电子迁移率晶体管的制作。
一般而言，由于缓冲层16与阻障层24的材料能带间隙(band gap)不同之故，缓冲层16与阻障层24的界面处数较佳形成异质结(heterojunction)。异质结处的能带弯曲，导带(conduction band)弯曲深处形成势阱(potential well)，将压电效应(piezoelectricity)所产生的电子约束于势阱中产生一沟道区并形成二维电子气(two-dimensional electron gas,2DEG)，进而形成导通电流。
然而现行缓冲层的设计中，对应前述实施例上半部20的缓冲层虽与本发明一样是由掺杂碳原子的氮化镓所构成但对应前述实施例下半部18的缓冲层则通常是由无掺杂(undoped)的氮化镓所构成，其中无掺杂的氮化镓缓冲层由于较低的势阱容易使沟道区的电子注入(inject)至深层或下半部18的缓冲层内造成放电(discharge)现象，进而降低2DEG并使阻值提升。
为了解决此问题本发明主要调整缓冲层中下半部18与上半部20中的碳浓度，特别是将下半部18的碳浓度调整至高于上半部20的碳浓度，使上半部20至下半部18的碳浓度产生一阶梯式的成长，如此即可抑制势阱产生，避免载流子进入下层或下半部20的缓冲层中进而降低放电现象。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (20)

1.一种制作高电子迁移率晶体管(high electron mobility transistor,HEMT)的方法，其特征在于，包含：
形成缓冲层于基底上，该缓冲层包含：
下半部，包含第一碳浓度；
上半部，包含第二碳浓度；以及
形成阻障层于该缓冲层上。
2.如权利要求1所述的方法，还包含：
形成沟道区于该上半部以及该阻障层之间；
形成P型半导体层于该阻障层上；
形成栅极电极于该P型半导体层上；以及
形成源极电极以及漏极电极于该栅极电极两侧。
3.如权利要求2所述的方法，其中该沟道区包含第三碳浓度。
4.如权利要求3所述的方法，其中该第三碳浓度小于该第二碳浓度。
5.如权利要求3所述的方法，其中该第三碳浓度小于该第一碳浓度。
6.如权利要求1所述的方法，其中该第二碳浓度小于该第一碳浓度。
7.如权利要求1所述的方法，其中该下半部厚度小于该上半部厚度。
8.如权利要求1所述的方法，其中该缓冲层包含氮化镓(GaN)。
9.如权利要求1所述的方法，其中该阻障层包含氮化铝镓(AlxGa1-xN)。
10.如权利要求2所述的方法，其中该P型半导体层包含P型氮化镓。
11.一种高电子迁移率晶体管(high electron mobility transistor,HEMT)，其特征在于，包含：
缓冲层，设于基底上，该缓冲层包含：
下半部，包含第一碳浓度；
上半部，包含第二碳浓度；以及
阻障层，设于该缓冲层上。
12.如权利要求11所述的高电子迁移率晶体管，还包含：
沟道区，设于该上半部以及该阻障层之间；
P型半导体层，设于该阻障层上；
栅极电极，设于该P型半导体层上；以及
源极电极以及漏极电极，设于该栅极电极两侧。
13.如权利要求12所述的高电子迁移率晶体管，其中该沟道区包含第三碳浓度。
14.如权利要求13所述的高电子迁移率晶体管，其中该第三碳浓度小于该第二碳浓度。
15.如权利要求13所述的高电子迁移率晶体管，其中该第三碳浓度小于该第一碳浓度。
16.如权利要求11所述的高电子迁移率晶体管，其中该第二碳浓度小于该第一碳浓度。
17.如权利要求11所述的高电子迁移率晶体管，其中该下半部厚度小于该上半部厚度。
18.如权利要求11所述的高电子迁移率晶体管，其中该缓冲层包含氮化镓(GaN)。
19.如权利要求11所述的高电子迁移率晶体管，其中该阻障层包含氮化铝镓(AlxGa1- xN)。
20.如权利要求12所述的高电子迁移率晶体管，其中该P型半导体层包含P型氮化镓。
CN202210979121.XA 2022-07-27 2022-08-16 高电子迁移率晶体管及其制作方法 Pending CN117525112A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW111128095A TW202406146A (zh) 2022-07-27 2022-07-27 高電子遷移率電晶體及其製作方法
TW111128095 2022-07-27

Publications (1)

Publication Number Publication Date
CN117525112A true CN117525112A (zh) 2024-02-06

Family

ID=83508493

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210979121.XA Pending CN117525112A (zh) 2022-07-27 2022-08-16 高电子迁移率晶体管及其制作方法

Country Status (4)

Country Link
US (1) US20240038844A1 (zh)
EP (1) EP4312277A1 (zh)
CN (1) CN117525112A (zh)
TW (1) TW202406146A (zh)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6692334B2 (ja) * 2017-09-20 2020-05-13 株式会社東芝 半導体基板及び半導体装置

Also Published As

Publication number Publication date
EP4312277A1 (en) 2024-01-31
US20240038844A1 (en) 2024-02-01
TW202406146A (zh) 2024-02-01

Similar Documents

Publication Publication Date Title
JP5722852B2 (ja) 不純物濃度を選択的に減少させたｉｉｉ−ｖ族デバイス構造
JPWO2011118098A1 (ja) 電界効果トランジスタ、電界効果トランジスタの製造方法、および電子装置
CN102569378A (zh) 化合物半导体器件及其制造方法
JPWO2011118099A1 (ja) 電界効果トランジスタ、電界効果トランジスタの製造方法、および電子装置
JP6649208B2 (ja) 半導体装置
JP2010171416A (ja) 半導体装置、半導体装置の製造方法および半導体装置のリーク電流低減方法
CN112820773B (zh) 一种高电子迁移率晶体管
US11784221B2 (en) Semiconductor device and manufacturing method therefor
KR101172857B1 (ko) 인헨스먼트 노멀리 오프 질화물 반도체 소자 및 그 제조방법
CN111524958B (zh) 一种高电子迁移率晶体管
EP4213216A1 (en) High electron mobility transistor and methods for fabricating the same
US20220216325A1 (en) High electron mobility transistor and method for fabricating the same
US11843046B2 (en) High electron mobility transistor (HEMT)
US20210202730A1 (en) Semiconductor device and manufacturing method therefor
CN116153993A (zh) 半导体结构及其形成方法
CN117525112A (zh) 高电子迁移率晶体管及其制作方法
CN116487259A (zh) 高电子迁移率晶体管及其制作方法
US20230352557A1 (en) Semiconductor device and manufacturing method thereof
US11967642B2 (en) Semiconductor structure, high electron mobility transistor and fabrication method thereof
WO2024104033A1 (zh) 半导体器件以及制造半导体器件的方法
JP2012227228A (ja) 半導体デバイスおよび半導体デバイスの製造方法
CN117198877A (zh) 高电子迁移率晶体管及其制作方法
CN117855042A (zh) 高电子迁移率晶体管及其制作方法
CN117524871A (zh) 高电子迁移率晶体管及其制作方法
CN115513276A (zh) 半导体结构及高电子迁移率晶体管

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination