CN100431110C - 低介电氮化硅膜的形成方法和半导体器件及其制造工艺 - Google Patents

低介电氮化硅膜的形成方法和半导体器件及其制造工艺 Download PDF

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CN100431110C
CN100431110C CNB018140505A CN01814050A CN100431110C CN 100431110 C CN100431110 C CN 100431110C CN B018140505 A CNB018140505 A CN B018140505A CN 01814050 A CN01814050 A CN 01814050A CN 100431110 C CN100431110 C CN 100431110C
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interlayer dielectric
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郑基市
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Abstract

一种形成氮化硅膜的方法包括用具有有机硅氮烷键的有机Si化合物作为气体源的CVD工艺。该CVD工艺是在有机Si源中的有机硅氮烷键保持在氮化硅膜中的条件下进行的。

Description

低介电氮化硅膜的形成方法和半导体器件及其制造工艺
技术领域
本发明一般涉及半导体器件，特别涉及具有低介电性能绝缘膜的半导体器件及其制造工艺。
随着器件微型化技术的发展，近年来的前沿半导体集成电路中包括巨大数量的半导体器件元件。在这种大规模半导体集成电路中，没有充分使用单个互连层，用于互连其中的半导体器件元件，因此通常提供多层互连结构，其中多个互连层互相堆叠，并且层间绝缘膜置于其间，用于互连半导体器件元件。
特别是，采用双镶嵌(dual damascene)工艺对形成多层互连结构进行广泛的研究。在双镶嵌工艺中，预先在层间绝缘膜中形成互连凹槽和接触孔，并用导电材料填充如此形成的互连凹槽和接触孔。在这种双镶嵌工艺中，设置在多层互连结构中作为刻蚀停止膜同时作为金属扩散阻挡层的绝缘膜的作用非常重要。
背景技术
在双镶嵌工艺技术中有各种修改，图11A-11F表示采用双镶嵌工艺形成多层互连结构的典型常规方法。
参见图11A，Si衬底10被CVD-SiO2膜等的层间绝缘膜11覆盖，并在层间绝缘膜11上形成互连图形12A。Si衬底10上承载各种半导体器件元件，如MOS晶体管(图中未示出)。
互连图形12A被埋置在形成在层间绝缘膜11上的相邻层间绝缘膜12B中以形成互连层12，其中互连层12被刻蚀停止膜13如SiN膜覆盖。刻蚀停止膜13还被相邻层间绝缘膜14覆盖。
在图11A的步骤中，利用光刻工艺在层间绝缘膜14上形成光刻胶图形18，以使光刻胶图形18具有对应要形成的接触孔的开口18A，利用干刻蚀工艺同时采用光刻胶图形18作掩模，去掉层间绝缘膜14。作为干刻蚀工艺的结果，在层间绝缘膜14中形成对应要形成的接触孔的开口14A。
接着，在图11B的步骤中，去掉光刻胶图形18并在图11C的步骤中在图11B的结构上形成光刻胶膜19，以便填充接触孔14A。通过利用光刻工艺构图如此形成的光刻胶膜19，在光刻胶膜19中形成对应要形成的互连图形的光刻胶开口19A。
然后，在图11D的步骤中，利用干刻蚀同时采用光刻胶膜19作掩模，构图在光刻胶开口19A上露出的层间绝缘膜14的露出部分。随后，去掉光刻胶膜19。作为这种构图工艺的结果，在层间绝缘膜14中形成除了接触孔14A之外对应所希望的互连凹槽的开口14B。
接下来，在图11E的步骤中，通过利用RIE工艺的干刻蚀工艺去掉刻蚀停止膜13，并露出互连图形12A。
接着，在图11F的步骤中，用Al或Cu的导电膜填充互连凹槽14B和开口14A。通过对如此获得的结构施加化学机械抛光(CMP)工艺，获得通过接触孔14A与互连图形12A电连接的互连图形20。
通过重复前述工艺步骤，可以形成第三和第四互连图形。
在用在半导体器件中的这种多层互连结构中，采用低介电性能绝缘膜用于层间绝缘膜12和14以便减少多层互连结构的杂散电容是非常重要的。通过减少杂散电容，提高了半导体器件的工作速度。因此已经做了很多尝试，采用低介电性能材料用于层间绝缘膜12或14，如掺杂F的SiO2膜(SiOF膜)、有机Si绝缘膜(SiOCH膜)等。特别是，通过采用有机Si绝缘膜，可以实现3.0或更小的比介电常数。
在利用双镶嵌工艺形成多层互连结构的这种工艺中，刻蚀停止膜13的作用非常重要，如前面注意到的。通常，呈现相对于层间绝缘膜14的大刻蚀选择性的SiN膜广泛地用于该目的。在双镶嵌工艺的技术中，刻蚀停止膜不仅必须具有大刻蚀选择性而且还用做阻挡构成互连图形的金属如Cu的有效阻挡层。此外，刻蚀停止膜必须具有相对于互连图形以及层间绝缘膜的优异粘接性。另外，刻蚀停止膜必须具有抵抗等离子体灰化工艺或湿刻蚀工艺的优异性能。都知道SiN膜用做有效的扩散阻挡层。
通常，很容易利用等离子体CVD工艺形成SiN膜。另一方面，如此形成的SiN膜具有7-8的大介电常数，因此采用SiN刻蚀停止膜13可基本上取消在多层互连结构中采用低介电性能绝缘膜作为层间绝缘膜12和14而实现的杂散电容减少的效果。
发明内容
相应地，本发明的一般目的是提供一种新的可使用的半导体器件及其制造方法，其中消除了前述问题。
本发明的另一和更特殊的目的是提供一种低介电性能氮化物膜及其制造方法。
本发明的又一目的是提供采用低介电性能氮化硅膜形成多层互连结构的方法。
本发明的再一目的是提供具有低介电性能氮化硅膜的半导体器件。
本发明的另一目的是提供形成氮化硅膜的方法，包括以下步骤：
在反应室中引入衬底；向所述处理室中引入其中具有有机硅氮烷键的有机Si化合物，作为气体源；向所述气体源输送能量；和利用CVD工艺，从所述气体源在所述衬底的表面上淀积含有Si、N、C和H作为基本构成元素的SiNCH膜，在向所述气体源输送能量时分配到所述气体源的气体分子的能量在所述硅氮烷键的结合能以下，所述SiNCH膜的比介电常数在3.5以上5.5以下。
根据本发明，通过采用其中含有有机硅氮烷键的有机Si化合物作为源料的CVD工艺，可以形成低密度SiNCH膜(含有Si、N、C和H作为基本或主要构成元素的膜)。如此形成的低密度SiNCH膜的特征在于低介电常数并具有相对于下层的优异粘接性。低密度SiNCH膜还用做阻挡金属原子如Cu的有效扩散阻挡层。低密度SiNCH膜呈现抵抗等离子体灰化工艺、干刻蚀或湿刻蚀工艺的优异性能。
在本发明中，优选有机Si化合物具有(SiR1)nNR2、(SiR1NR2)n或(SiR1(NR2)1.5)n的结构式，其中n是1或更大的整数，R1和R2每个都可以是氢或选自烷基如甲基、环烃基如苯酚基或乙烯基的基。优选如此进行CVD工艺，以便Si化合物中的硅氮烷键基本上保持在SiNCH膜中。通过采用具有(SiR1)nNR2、(SiR1NR2)n或(SiR1(NR2)1.5)n结构式的化合物(R1和R2每个都可以是氢或选自烷基如甲基、环烃基如苯酚基或乙烯基的基，n是1或更大的整数)，在CVD工艺期间源化合物中的有机硅氮烷键被保持在SiNCH膜中，并且SiNCH膜呈现减少的密度。
优选，用于淀积SiNCH膜的CVD工艺包括有机Si化合物的等离子体聚合反应工艺。还优选等离子体聚合反应工艺是在有机Si化合物中的硅氮烷键基本上被保持在SiNCH膜中的等离子体功率下进行的。为此，有效地减小了SiNCH膜的比介电常数(specific dielectricconstant)。在通过有机Si化合物的热聚合反应工艺进行淀积SiNCH膜的步骤的情况下，必须设定温度，以使有机Si化合物中的有机硅氮烷键基本上被保持在淀积的SiNCH膜中。
在本发明中，可以通过替换工艺淀积SiNCH膜，在该工艺中，给前述有机Si化合物添加含有N的附加气体源如N2或NH3，形成附加气体源的等离子体，并给反应室输送等离子体。根据这种工艺，只给有机源化合物提供小等离子体功率，并有机Si化合物中的有机硅氮烷键保持在氮化硅膜中。
在本发明中，还可以形成含有氧的SiONCH体系的硅氮氧化物膜，其中氧可以从源材料或附加源材料中释放出来。当膜中的氧含量为40％或更低时，硅氮氧化物膜呈现与前述氮化硅膜相似的性能。
本发明的另一目的是提供制造半导体器件的方法，包括以下步骤：
在衬底上形成刻蚀停止膜；
在所述刻蚀停止膜上淀积层间绝缘膜；
构图所述层间绝缘膜以形成开口；
刻蚀所述层间绝缘膜以在所述层间绝缘膜中形成对应所述开口的凹部；和
通过刻蚀工艺，选择地从所述开口刻蚀所述刻蚀停止膜，
淀积所述刻蚀停止膜的所述步骤包括以下步骤：
向处理装置的反应室中引入所述衬底；
向所述反应室中输送其中含有有机硅氮烷键的有机Si化合物，作为气体源；和
利用CVD工艺，在所述处理室中在所述衬底表面上由所述有机Si化合物淀积SiNCH膜，作为所述刻蚀停止膜。
根据本发明，在利用双镶嵌工艺形成多层互连结构时，利用CVD工艺由其中含有有机硅氮烷键的有机Si化合物的源材料形成的SiNCH膜用做氮化硅刻蚀停止膜。如此形成氮化硅膜中保持源材料中的有机硅氮烷键，其中有机硅氮烷键中包括烃基。因此，如此形成的氮化硅膜的特征在于低密度并具有低介电常数特性。通过采用这种低介电性能氮化硅膜作为刻蚀停止膜，基本上减少了多层互连结构的杂散电容，并相应地提高了半导体器件的工作速度。如此形成的低介电性能氮化硅膜具有优异耐刻蚀性的附加优点，因此低介电性能氮化硅膜可用做在双镶嵌工艺期间在干刻蚀工艺中的有效刻蚀停止膜或硬掩模。
在本发明中，还优选有机Si化合物具有(SiR1)nNR2、(SiR1NR2)n或(SiR1(NR2)1.5)n的结构式，其中n是1或更大的整数，R1和R2每个都可以是氢或选自烷基如甲基、环烃基如苯酚基、或乙烯基的基。还优选进行CVD工艺，以便有机Si化合物中的硅氮烷键基本上保持在SiNCH膜中。通过采用具有(SiR1)nNR2、(SiR1NR2)n或(SiR1(NR2)1.5)n结构式的化合物，(R1和R2是氢或选自烷基如甲基、环烃基如苯酚基、或乙烯基的基，n是1或更大的整数)，在CVD工艺期间源化合物中的有机硅氮烷键可以保持在SiNCH膜中，并且SiNCH膜呈现减小的密度。
优选，用于淀积SiNCH膜的CVD工艺包括有机Si化合物的等离子体聚合反应工艺。还优选在其中有机Si化合物中的有机硅氮烷键基本上保持在SiNCH膜中的等离子体功率下进行等离子体聚合反应工艺。因此，有效地减小了SiNCH膜的密度和比介电常数。在通过有机Si化合物的热聚合反应工艺进行淀积SiNCH膜的步骤的情况下，需要设定温度，以使有机Si化合物中的有机硅氮烷键基本上保持在被淀积的SiNCH膜中。
在本发明中，还可以通过以下替换工艺淀积SiNCH膜：给前述有机Si化合物添加含有N的附加气体源如N2或NH3，形成附加气体源的等离子体，并且该将等离子体输送给反应室。根据这个工艺，只需要给有机源化合物提供小等离子体功率，并且有机Si化合物中的有机硅氮烷结构保持在氮化硅膜中。
在本发明中，还可以施加在层间绝缘膜上淀积导体层的工艺，以便经过开口填充凹部，并利用化学机械抛光工艺去掉位于层间绝缘膜上面的部分导体层。因此，优选导体层由Cu形成。由于氮化硅膜用做抵抗Cu的有效扩散阻挡层，因此这种结构可以有效地抑制Cu从Cu层扩散到相邻层间绝缘膜。此外，如此形成的氮化硅刻蚀停止膜具有优异的泄漏特性。
通过采用有机绝缘膜或掺杂F的SiO2膜作为层间绝缘膜，减小了层间绝缘膜的电容并减少了多层互连结构的总杂散电容。通过形成前述凹部以便包括互连凹槽或接触孔，可以形成各种复杂的互连图形。
本发明的另一目的是提供SiNCH体系的氮化硅膜，所述氮化硅膜中含有表示为CnHm的任意原子集团，所述原子集团与Si原子键合，其中n是1以上的整数，m是比0大的整数。
根据本发明，氮化硅膜中含有有机硅氮烷键，而有机硅氮烷键中又含有烃基。本发明的氮化硅膜具有低膜密度特性和低介电常数的相关特性。该原子集团可以是烷基、环烃基或乙烯基的任何一个。本发明的氮化硅膜具有优异粘接性和抵抗各种工艺如等离子体灰化工艺、干刻蚀工艺或湿刻蚀工艺的特性的有利特征。该氮化硅膜还用做有效扩散阻挡层并且其特征在于小漏电流。
本发明的再一目的是提供半导体器件，包括：
衬底；和形成在所述衬底上的多层互连结构，
所述多层互连结构包括刻蚀停止膜、形成在所述刻蚀停止膜上的层间绝缘膜、形成在所述层间绝缘膜中的互连凹槽、形成在所述层间绝缘膜中并对应所述互连凹槽的接触孔、和填充所述互连凹槽和所述接触孔的导体层，其中所述刻蚀停止膜包括SiNCH膜并且其中含有表示为CnHm的任意原子集团，所述原子集团与Si原子键合。
根据本发明，氮化硅膜中含有有机硅氮烷键，而有机硅氮烷键中又含有烃基。结果是，减小了氮化硅膜的密度并相应减小了介电常数。因此，减小了多层互连结构的杂散电容并提高了半导体器件的工作速度。对于原子集团，可采用氢、烷基、环烃基、或乙烯基的任何一种。本发明的氮化硅膜呈现优异的粘接性和抵抗等离子体灰化工艺、干刻蚀工艺或湿刻蚀工艺的特性。此外，本发明的氮化硅膜用做阻止金属元素扩散的有效扩散阻挡层。另外，本发明的氮化硅膜具有减小的漏电流的有利特征。
在结合附图阅读了下面的详细说明之后将使本发明的其它目的和附加特点更显然。
附图说明
图1是表示用在本发明第一实施例中的等离子体CVD装置的结构的示意图；
图2A和2B是表示用在本发明第一实施例中的有机硅氮烷键的例子的示意图；
图3A和3B是表示在本发明第一实施例中获得的氮化硅膜结构的例子的示意图；
图4A-4F是表示根据本发明第二实施例的半导体器件的制造工艺的示意图；
图5A-5E是表示根据本发明第三实施例的半导体器件的制造工艺的示意图；
图6A-6E是表示根据本发明第四实施例的半导体器件的制造工艺的示意图；
图7A-7E是表示根据本发明第五实施例的半导体器件的制造工艺的示意图；
图8A-8E是表示根据本发明第六实施例的半导体器件的制造工艺的示意图；
图9是表示根据本发明第七实施例的半导体器件的结构的示意图；
图10是表示第七实施例的半导体器件的制造工艺的示意图；
图11A-11F是表示常规半导体器件的制造工艺的示意图。
具体实施方式
(第一实施例)
图1表示用在本发明第一实施例中的等离子体CVD装置30的结构。
参见图1，等离子体CVD装置30包括由泵31C经过排气口31A和收集器(trap)31B抽真空的反应室31，其中反应室31中安装用于固定待处理衬底32A的工作台32。
在处理室31中，提供面对工作台32的簇射头(showerhead)33，其中从容器34给簇射头33输送液态有机Si源。更具体地说，容器34被He气体加压，并且其中的液态有机Si源作为第一气体源经过液体质量流控制器34A和喷雾器34B并与从管道34C输送的Ar载体气体一起输送给簇射头33。
此外，经过管道35给簇射头33输送作为第二气体源的NH3气体或N2气体，并且通过从射频电源36给其输送450KHz-60MHz的射频功率，在第一和第二气体源中进行等离子体激发。
通过形成等离子体，随着从簇射头33释放源材料，在反应室31中进行等离子体聚合反应，并且如此输送的源材料进行等离子体激发。作为等离子体激发的结果，在衬底32A的表面上淀积氮化硅膜。
在图1的结构中，应该注意到泵31C连接到洗涤器单元31D，泵31C的废气被洗涤器单元31D处理之后释放到环境中。
图2A和2B表示保持在源容器34中的示意有机Si源材料的结构式，其中图2A表示其中1，1，3，3，5，5，7，7-辛甲基环四硅氮烷(octamethylcyclotetrasilazane)用做有机Si源的情况。在图2A中，R1是甲基，R2是氢。因此，有机Si源具有Si4C8H28N4的结构式。另一方面，在图2B的例子中，六甲基二硅氮烷(Si2C6H19N)用做有机Si源。应该注意这些只是含有有机硅氮烷键的有机Si源的示意例子，硅氮烷键是用于其中含有Si-N-Si键的化合物一般术语。硅氮烷键是通过给Si-N-Si键添加烷基如甲基或乙基、或环烃基如苯基、或乙烯基获得的。
有机硅氮烷化合物的例子概括示于下列表I中。
表I
 三甲基硅氮烷(Triethylsilazane)  SiC6H17N
 三丙基硅氮烷(Tripropylsilazane)  SiC9H23N
 三苯基硅氮烷(Triphenylsilazane)  SiC18H17N
  二硅氮烷(Disilazane)   Si2H7N
  四甲基二硅氮烷(Tetramethyldisilazane)   Si2C4H15N
  六甲基二硅氮烷(Hexamethyldisilazane)   Si2C6H19N
  六乙基二硅氮烷(Hexaethyldisilazane)   Si2C12H31N
  六苯基二硅氮烷(Hexaphenyldisilazane)   Si2C36H31N
  Heotamethyldisilazane   Si2C7H21N
  二丙基-四甲基二硅氮烷(Dipropyl-tetramethyldisilzne)   Si2C10H27N
  二(正)丁基-四甲基二硅氮烷(Di-n-butyl-tetranethyldisilazane)   Si2C12H31N
  二(正)辛基-四甲基二硅氮烷(Di-n-octyl-tetramethyldisilazane)   Si2C20H47N
  三乙基-三甲基环三硅氮烷(Triethyl-trimethylcyclotrlsilazane)   Si3C9H27N3
  六甲基环三硅氮烷(Hexamethylcyclotrisilazane)   Si3C6H21N3
  六乙基环三硅氮烷(Hexaethylcyclotrisilazane)   Si3C12H33N3
  六苯基环三硅氮烷(Hexaphenylcyclotrisilazane)   Si3C36H33N3
  辛甲基环四硅氮烷(Octamethylcyclotetrasilazane)   Si4C8H28N4
  辛乙基环四硅氮烷(Octaethylcyclotetrasilazane)   Si4C16H44N4
  四乙基-四甲基环四硅氮烷(Tetraethyl-tetramethylcyclotetrasilazane)   Si4C12H36N4
  氰基丙基甲基环硅氮烷(Cyanopropylmethylcyclosilazane)   SiC5H10N2
  四苯基二甲基二硅氮烷(Tetraphenyldimethyldisilazane)   Si2C26H27N
  二苯基-四甲基二硅氮烷(Diphenyl-tetramethyldisilazane)   Si2C16H23N
  三乙烯基-三甲基环三硅氮烷(Trivinyl-trimethylcyclotrisilazane)   Si3C9H21N3
  四乙烯基-四甲基环四硅氮烷(Tetravinyl-tetramethylcyclotetrasilazane)   Si4C12H28N4
  二乙烯基-四甲基二硅氮烷(Divinyl-tetramethyldisilazane)   Si2C8H19N
参见图2A和2B，前述有机Si源含有具有甲基Me的有机硅氮烷键并具有由通式(SiR1)nR2或(SiR1NR2)n表示的成分，其中n是1或更大的整数，而R1和R2具有CmH2m+1(m是大于零的整数)的通式，并且可以是氢原子、烷基、环烃基如苯基或乙烯基的任何一种。
采用上述有机Si源作为源，在图1的CVD设备30中同时采用Si晶片做衬底32A在8英寸Si晶片上淀积氮化硅膜。氮化硅膜的淀积是在200-400℃的衬底温度下同时以27MHz的频率输送100-1000W的等离子体功率进行的。详细的条件概括列于表II中。
表II
  衬底温度   200-400℃
  等离子体功率   100-1000W/27MHz
  处理室压力   13.3Pa(100毫乇)
  有机Si源流速   0.1cc/min
  NH3流速   50SCCM
  Ar流速   200SCCM
  喷雾器温度   80-120℃
如此获得的氮化硅膜实际上是SiNCH膜并具有3.5-5.5的比介电常数。
应该注意到，鉴于普通等离子体SiN膜具有约7-8的比介电常数，该氮化硅膜的比介电常数的值已经下降到一半。通过在前述淀积工艺中利用100-300W的小等离子体功率，从簇射头33输送的汽化的有机Si化合物在反应室31中不完全分解，并且有机源中的有机硅氮烷键基本上保持在如此淀积在Si晶片上的氮化硅膜中。由于有机硅氮烷键的存在导致淀积的SiN膜的密度下降，还引起淀积的SiN膜的比介电常数减小。
图3A示出了利用FT-IR法观察到的如此形成的氮化硅膜的结构。
参见图3A，可以看到如此形成的氮化硅膜中保持从图2A和2B的有机硅氮烷键得到的Si-CH3或CH3的烃结构，而氮化硅膜中的烃结构减小了密度，由此减小了氮化硅膜的比介电常数。
图3A还示出了在与采用1000W的等离子体功率相比采用100W的等离子体功率时，对应Si-CH3键的峰值的相对高度相对于对应SiN键的峰值而增加。这个结果清楚地显示了与利用1000W等离子体功率形成的氮化硅膜相比利用100W的等离子体功率形成的氮化硅膜含有增加浓度的Si-CH3键。因此，推断出比介电常数的所希望的减小是由于淀积的氮化硅膜中的膜密度的减小造成的。
图3B显示了如此形成的氮化硅膜的示意结构。
参见图3B，该氮化硅膜除了常用的Si-N结构之外还包括一起形成网络结构的Si-CH3键、N-H键、Si-H键等。具有这种网络结构的氮化硅膜可以由有机硅氮烷键源同时适当选择例如等离子体功率等条件而形成。
应该注意到如此获得的SiNCH膜呈现相对于下层膜的优异粘接性。此外，SiNCH膜呈现抵抗等离子体灰化、干刻蚀和湿刻蚀的优异特性。因此，本发明的SiNCH膜可以成功地用在多层互连结构中。
应该注意到表II中只是示出了典型例子，还可以通过在50-2000W范围内调整等离子体功率、在从室温到500℃的范围内调整衬底温度、在1.33-1.33kPa(10毫乇-10乇)范围内调整处理压力、或在0.001-10cc/min范围内调整液态有机Si源的输送速度来形成本发明的SiNCH膜。
此外，还可以通过热解CVD工艺形成SiNCH膜。例如，这种热解CVD工艺可以在图2的等离子体CVD设备30中进行而不用激发射频电源36。
在这种情况下，衬底温度设定得比在等离子体CVD工艺中采用的衬底温度高。然而，衬底温度应该不超过600℃。否则，包含在有机Si源中的有机硅氮烷键不会保持在SiNCH膜中。
[第二实施例]
图4A-4F表示根据本发明第二实施例的具有多层互连结构的半导体器件的制造工艺，其中对应前述部件的那些部件利用相同的参考标记表示并省略其说明。
图4A对应前述图11A的步骤，并且形成相同的叠层结构，除了在表II条件下利用图2的等离子体CVD设备由图2A的有机Si源形成的SiNCH膜代替刻蚀停止膜13用于刻蚀停止膜之外。
在图4B的步骤中，采用光刻胶图形18作掩模，对层间绝缘膜14进行干刻蚀，并在层间绝缘膜14中形成对应光刻胶开口18A的开口。形成开口之后，去掉光刻胶图形18。
接着，在图4C的步骤中，重新在图4B的结构上形成光刻胶膜19，其中然后利用光刻构图工艺对光刻胶膜19进行构图以形成光刻胶开口19A，其对应要在多层互连结构中形成的互连图形。
接着，在图4D的步骤中，采用光刻胶膜19做掩模的同时，在由光刻胶开口19A露出的部分中利用干刻蚀工艺刻蚀掉层间绝缘膜14，之后去掉光刻胶膜19本身。作为前述干刻蚀工艺和光刻胶去除工艺的结果，在开口14A的底部露出SiNCH膜23。
随后，在图4E的步骤中，对如此获得的结构进行干刻蚀工艺，并在SiNCH膜23中对应开口14A形成开口14B。
此外，在图4F的步骤中，利用Ta、TaN、Ta/TaN、TiN、WN等的阻挡金属层(未示出)覆盖由开口14B形成的互连凹槽和由开口14A形成接触孔，然后用导体层如Cu层填充。通过利用CMP工艺去除覆盖层间绝缘膜14的导体层，获得在接触孔14A与下层互连图形14B接触的导体图形20，如图4F所示。
对于层间绝缘膜14，可以采用无机低介电性能绝缘膜，如掺杂F的SiO2膜、HSQ膜如SiOH膜或多孔绝缘膜。或者，可以采用低介电性能有机绝缘膜如有机SOG膜或芳香族低介电性能有机绝缘膜用于层间绝缘膜14。当然，可以采用常规CVD-SiO2膜或SOG膜用于层间绝缘膜14。通过采用低介电性能无机或有机绝缘膜用于多层互连结构中的层间绝缘膜14，可以减小多层互连结构的总介电常数并提高半导体器件的工作速度。
应该注意到本例的SiNCH膜23具有各种特性，如优异的粘接性、优异的抗干刻蚀性、作为阻挡Cu的扩散阻挡层的优异性能、低漏电流等，适合用在高速半导体器件的多层互连结构中。
[第三实施例]
图5A-5E是表示根据本发明第三实施例的半导体器件的制造工艺的示意图，其中对应前述部件的那些部件用相同的参考标记表示，并省略其说明。
参见图5A，该步骤基本上与前述图4A的步骤相同，除了还提供层间绝缘膜16和SiNCH膜25和27之外。
更具体地说，图5A的叠层结构除了形成在Si衬底10层上的间绝缘膜11和形成在层间绝缘膜11上的互连层12之外还包括SiNCH膜23、层间绝缘膜14、SiNCH膜25、层间绝缘膜16和SiNCH膜27，以便膜23-27连续堆叠在一起，并且在如此形成的叠层结构上提供具有光刻胶开口18A的光刻胶图形。与前述实施例相同，光刻胶开口18A要形成在多层互连结构中的对应接触孔。
接着，在图5B的步骤中，采用光刻胶图形18作掩模，对SiNCH膜27进行干刻蚀工艺，并在其中对应光刻胶开口18A形成开口(未示出)。
如此形成的开口露出下层层间绝缘膜16的一部分，并且对层间绝缘膜16的露出部分进行干刻蚀工艺。结果是，在层间绝缘膜16中对应光刻胶开口18A形成开口，以便露出一部分下层SiNCH膜25。通过对如此形成的SiNCH膜25进行干刻蚀工艺，对应光刻胶开口18A形成露出下层层间绝缘膜14的开口。
此外，通过对如此露出的层间绝缘膜14进行干刻蚀工艺，在层间绝缘膜14中对应光刻胶开口18A形成开口14A。如此形成的开口14A连续通过SiNCH膜27、层间绝缘膜16、SiNCH膜25和层间绝缘膜14延伸，并在其底部露出SiNCH膜23。
接下来，在图5C的步骤中，除去光刻胶膜18，并利用旋涂工艺在图5B的结构上形成另一光刻胶膜19，以便光刻胶膜19填充开口14A，并且在图5D的步骤中对光刻胶膜19进行光刻构图工艺。结果是，在光刻胶膜19中形成光刻胶开口19A，其对应要形成在多层互连结构中的互连凹槽。
接着，在图5E的步骤中，采用光刻胶膜19作掩模，在由光刻胶开口19A露出的部分中对SiNCH膜27进行干刻蚀工艺，在SiNCH膜27中对应光刻胶开口19A形成开口，以便该开口露出下层层间绝缘膜16中。然后对如此露出的层间绝缘膜16进行干刻蚀工艺，直到露出下层SiNCH膜25为止。结果是，在层间绝缘膜16中形成开口16A，其对应要在多层互连结构中对应光刻胶开口19A形成的互连凹槽。之后，除去光刻胶开口19A。
应该注意到用于形成开口18A的干刻蚀工艺由于露出SiNCH膜25而停止。然后通过除去露出的SiNCH膜27、25和23并用导体层如Cu层填充开口16A和14A，获得前面参照图4F说明的多层互连结构。
在本例中，还可以采用任何低介电性能无机绝缘膜如掺杂F的SiO2膜、HSQ膜如SiOH膜或多孔膜，或者低介电性能有机绝缘膜，如有机SOG膜或芳香族有机绝缘膜用于层间绝缘膜14和16。在本例的多层互连结构中，总介电常数减少了，并提高了半导体器件的工作速度。
在本例中，SiNCH膜23、25和27的特征在于低的比介电常数、优异粘接性、优异抗干刻蚀特性、作为Cu的扩散阻挡层的优异性能、和低漏电流。因此，本发明的SiNCH膜用在高速半导体器件的多层互连结构中是很理想的。
[第四实施例]
图6A-6E表示根据本发明第四实施例的半导体器件的制造工艺，其中对应前述部件的那些部件用相同的参考标记表示并省略其说明。
参见图6A，该步骤基本上与图5A的步骤相同，并在Si衬底10上形成层叠体，其中利用其上承载互连图形12的层间绝缘膜11覆盖Si衬底10。此外，SiNCH膜23、层间绝缘膜14、SiNCH膜25、层间绝缘膜16和SiNCH膜27连续堆叠在互连层12上。在本例中，在多层互连结构上提供光刻胶图形28，其中光刻胶图形28包括光刻胶开口28A，其对应要形成在多层互连结构中的互连图形。
在图6B的步骤中，采用光刻胶图形28作掩模，对SiNCH膜27进行干刻蚀工艺，在SiNCH膜27中对应光刻胶开口28A形成开口，以便如此形成的开口暴露出在SiNCH膜27下面形成的层间绝缘膜16。对如此露出的层间绝缘膜16进行干刻蚀工艺，并在对应光刻胶开口28A的层间绝缘膜16中形成对应要形成的互连凹槽的开口16A，以便露出下层SiNCH膜25。
接着，在图6C的步骤中除去光刻胶膜28，并在图6B的结构上重新形成光刻胶膜29，以便光刻胶膜29填充开口16A。此外，在图6D的步骤中利用光刻工艺对光刻胶膜29构图，以便在光刻胶膜29中形成光刻胶开口29A，其对应要形成在多层互连结构中的接触孔。
接下来，在图6E的步骤中，采用光刻胶图形29作掩模，对由光刻胶开口29A露出的一部分SiNCH膜25进行干刻蚀工艺，并在SiNCH膜25中对应光刻胶开口29A形成开口，以便露出下层层间绝缘膜14。之后，除去光刻胶图形29，并采用SiNCH膜27和25作硬掩模对层间绝缘膜14进行干刻蚀工艺。结果是，在层间绝缘膜14中对应光刻胶开口29A形成开口14A，并对应要形成在多层互连结构中的接触孔。
用于形成开口14A的干刻蚀工艺由于露出SiNCH膜23而停止。之后，除去露出的SiNCH膜27、25和23，并用导体层如Cu层填充开口16A和14A。结果是，获得参照图6F说明的多层互连结构。
在本例中，还可以采用任何无机低介电性能绝缘膜如掺杂F的SiO2膜、HSQ膜如SiOH膜或多孔膜，或者有机低介电性能绝缘膜，如有机SOG膜或芳香族有机绝缘膜。结果是，本例的多层互连结构具有总介电常数减少了和半导体器件的工作速度基本上提高了的优点。
在本例中，SiNCH膜23、25和27的特征在于低的比介电常数、优异粘接性、优异抗干刻蚀特性、作为Cu的扩散阻挡层的优异性能和低漏电流。因此，本发明的SiNCH膜用在高速半导体器件的多层互连结构中是很理想的。
[第五实施例]
图7A-7E表示根据本发明第五实施例的半导体器件的制造工艺，其中对应前述部件的那些部件用相同的参考标记表示并省略其说明。
参见图7A，与前述实施例相同，在Si衬底10上形成叠层结构，其中Si衬底10上承载层间绝缘膜11，层间绝缘膜12上承载互连层12。在互连层12上，连续堆叠SiNCH膜23、层间绝缘膜14和SiNCH膜25，其中SiNCH膜25上承载光刻胶图形41，该光刻胶图形具有对应要形成在多层互连结构中的接触孔的光刻胶开口41A。
光刻胶开口41A露出SiNCH膜25，因此对SiNCH膜25进行干刻蚀工艺。结果是，在SiNCH膜25中对应光刻胶开口41A形成开口25A。
接着，在图7B的步骤中，在SiNCH膜25上淀积层间绝缘膜16，以便填充开口25A，接着在层间绝缘膜16上淀积SiNCH膜27。
然后，在图7C的步骤中，在SiNCH膜27上施加光刻胶膜42，其中利用光刻工艺在图7D的步骤中对光刻胶膜42进行构图，以便在光刻胶膜42中对应要形成在多层互连结构中的互连图形形成开口42A。
接下来，在图7E的步骤中，采用光刻胶膜42作掩模，对在开口42A露出的SiNCH膜27的露出部分进行干刻蚀工艺，直到露出下层层间绝缘膜16为止。
接着，对层间绝缘膜16进行干刻蚀工艺，并且在层间绝缘膜16中对应前述光刻胶开口42A形成开口16A，其还对应要形成的互连凹槽。应该注意层间绝缘膜16的干刻蚀工艺由于在其中形成SiNCH膜25的部分中露出SiNCH膜25而停止，而在其中在膜25中形成开口25A的部分中，干刻蚀工艺通过开口25A进行到下层层间绝缘膜14内部，并在层间绝缘膜14中对应前述开口25A并因此对应要形成在多层互连结构中的接触孔形成开口14A。
用于形成开口14A的干刻蚀工艺由于露出SiNCH膜23而停止。随后，除去露出的SiNCH膜27、25和23并用Cu等的导体层填充开口16A和14A。结果是，获得参照图4F说明的多层互连结构。
在本例中，还可以采用任何无机低介电性能绝缘膜如掺杂F的SiO2膜、HSQ膜如SiOH膜或多孔膜，或者有机低介电性能绝缘膜，如有机SOG膜或芳香族有机绝缘膜用于层间绝缘膜14和16。由此，减小了该多层互连结构的总介电常数并提高了半导体器件的工作速度。
在本例中，SiNCH膜23、25和27具有各种优选的特性，如低的比介电常数、优异粘接性、优异抗干刻蚀特性、作为Cu的扩散阻挡层的优异性能和低漏电流，因此，本发明的SiNCH膜用在高速半导体器件的多层互连结构中是很理想的。
[第六实施例]
图8A-8E是表示根据本发明第六实施例的具有多层互连结构的半导体器件的制造工艺的示意图，该制造工艺采用了所谓的成组硬掩模，其中对应前述部件的那些部件用相同的参考标记表示并省略其说明。
在本例中，依次堆叠SiNCH膜23、层间绝缘膜14、SiNCH膜25、层间绝缘膜16和SiNCH膜27，与前述实施例一样。此外，利用等离子体CVD工艺或旋涂工艺在SiNCH膜27上形成SiO2膜43，用包括对应要形成在多层互连结构中的接触孔的光刻胶开口18A的光刻胶膜18覆盖如此形成的SiO2膜43。SiNCH膜27和SiO2膜43一起形成成组掩模。
在图8A的步骤中，采用光刻胶膜18作掩模，对SiO2膜进行干刻蚀工艺，并在SiO2膜43中对应光刻胶开口18A形成开口，以便露出位于SiO2膜43下面的SiNCH膜27。此外，对如此露出的SiNCH膜27进行干刻蚀工艺，并在SiNCH膜27中对应光刻胶开口18A形成开口27A，以便露出层间绝缘膜16，如图8B所示。
在图8B的步骤中，在SiO2膜43上形成具有对应要形成在多层互连结构中的互连凹槽的光刻胶开口19A的光刻胶膜19，以便露出SiO2膜43，其中在图8C中用光刻胶膜19作掩模并利用干刻蚀工艺去掉如此露出的SiO2膜43。因此，应该注意到SiNCH膜27用做开蚀停止层，结果是，在SiO2膜43中对应光刻胶开口19A形成开口43A，以便露出SiNCH膜27。
在图8C的步骤中，层间绝缘膜16的干刻蚀和在开口27A中的SiO2膜43的干刻蚀工艺同时进行，结果是，在多层互连结构16中形成对应开口17A的开口16A。在该步骤中，SiNCH膜27用做硬掩模。在开口16A中，露出SiNCH膜25。
接着，在图8D的步骤中，利用干刻蚀工艺去掉在开口43A露出的SiNCH膜27和在开口16A露出的SiNCH膜25，在开口43A露出层间绝缘膜16。同样，在开口16A露出层间绝缘膜14。
接下来，在图8E的步骤中，用干刻蚀工艺去掉在开口43A露出的层间绝缘膜16的露出部分和在开口16A露出的层间绝缘膜14的露出部分，并在层间绝缘膜16中对应光刻胶开口19A并由此对应要形成的互连凹槽形成开口16B。同样，在层间绝缘膜14中对应光刻胶开口18A并由此对应要形成的接触孔形成开口14A。
此外，在图8E的步骤中去掉露出的SiNCH膜27、25和23，并用Cu导电层填充开口16A和14A。由此，获得参照图4F说明的多层互连结构。
在本例中，SiNCH膜23、25和27还具有低比介电常数、优异粘接性、优异抗干刻蚀特性、作为Cu的扩散阻挡层的优异特性、和低漏电流的有利特征。因此，本发明的SiNCH膜用在高速半导体器件的多层互连结构中是很理想的。
[第七实施例]
图9表示根据本发明第七实施例的半导体器件50的结构。
参见图9，该半导体器件包括承载有源器件(未示出)的Si衬底51，其中Si衬底51承载覆盖有源器件的绝缘膜52。在绝缘膜52上，形成第一层互连图形53A，在绝缘膜52上形成层间绝缘膜53以覆盖互连图形53A。此外，层间绝缘膜53上承载第二层互连图形54A，并在层间绝缘膜53上形成互连图形54以覆盖第二层互连图形54A。用氮化硅钝化膜55覆盖层间绝缘膜54的表面。
图10表示形成氮化硅钝化膜55的工艺。
参见图10，在形成层间绝缘膜54时，在步骤1中将半导体器件50引入到旋涂器单元中。由此，在层间绝缘膜54的表面上对应钝化膜55形成有机硅氮烷化合物的旋涂膜，例如成分为(SiH2NH)n(其中n是1或更大的整数)的化合物膜。在步骤1中，在100℃或以下的温度下对如此形成的旋涂膜进行烘焙工艺，用于去掉溶剂，结果是获得稳定的氮化硅膜。
另一方面，在图10的步骤1中获得的氮化硅膜必然含有氧，因此本发明的工艺进行到步骤2，其中将半导体器件50安装到等离子体处理装置如图2的等离子体CVD装置中。在那里，利用含有NH3、N2、H2等的等离子气体处理氮化硅膜的表面，并且该膜中的氧部分地被氮代替。由此，在聚合反应在旋涂膜55中完成之前，本例进行了步骤2的等离子体处理。
作为这种等离子体处理的结果，氮化硅膜55被转换成具有表示为SiNCH或SiONCH的化学式的膜。如此获得的膜具有优异的抗温度特性和抗化学物质的特性。
通常，通过在步骤1之后在N2气氛中进行热处理，可以获得氮氧化物膜。然而，用于转换该膜的工艺需要400℃或更高的高温。此外，尽管使用这种高温，膜质量的转换也不充分。
在本发明中，应该注意到步骤2的等离子体处理是在完成旋涂膜55中的聚合反应之前进行的。因此，可以在低温实现有效表面改性反应。应该注意到，可以采用NH3和SiH4作为等离子体气体在350℃或以下的衬底温度下同时采用100-1000W的等离子体功率进行这种等离子体处理。优选，设定等离子体处理的进行，以便减少膜55中的OH基，并增加N键的比例。
在本例中，应该注意到步骤1的烘焙工艺是在100℃或以下的温度下进行的，因此在聚合反应在旋涂膜55中完成之前进行步骤2的工艺。此外，优选采用单个晶片处理装置，以便连续进行步骤1和步骤2。
应该注意到步骤2的工艺不限于等离子体处理，还可以是在含有N或H的气氛中进行的热处理。例如，可以在含有NH3或N2和H2的气氛中在400℃或更高的温度下进行步骤2的热处理。
此外，本发明不限于上述实施例，在不脱离本发明的范围的情况下还可以做出各种改变和修改。
工业实用性
根据本发明，通过在CVD源中的有机硅氮烷键保持在膜中的条件下进行其中含有有机硅氮烷键的有机Si化合物的CVD工艺，可以获得SiNCH体系的氮化硅膜。如此形成的氮化硅膜的特征在于低密度和低比介电常数。此外，如此获得氮化硅膜具有优异的粘接性和抗刻蚀性的有利特征并作为抵抗金属元素如Cu等的有效扩散阻挡层的特性。通过采用本发明的氮化硅膜可以形成具有小杂散电容的多层互连结构。

Claims (22)

1、一种形成氮化硅膜的方法，包括以下步骤：
将衬底引入反应室中；
将其中具有有机硅氮烷键的有机Si化合物输送到所述处理室中，作为气体源；
向所述气体源输送能量；和
利用CVD工艺，在所述衬底的表面上利用所述气体源淀积含有Si、N、C和H作为基本构成元素的SiNCH膜，
其中，在向所述气体源输送能量时分配到所述气体源的气体分子的能量在所述硅氮烷键的结合能以下，
所述SiNCH膜的比介电常数在3.5以上5.5以下。
2、根据权利要求1的方法，其中所述有机Si化合物具有(SiR1)nNR2、(SiR1NR2)n或(SiR1(NR2)1.5)n的任何的结构式，其中n是大于等于1的整数，R1和R3选自氢、烷基、环烃基或乙烯基的任一种。
3、根据权利要求1的方法，其中所述SiNCH膜包括Si-C键和Si-N键。
4、根据权利要求1的方法，其中淀积所述SiNCH膜的所述步骤包括所述有机Si化合物的等离子体聚合工艺。
5、根据权利要求4的方法，其中所述等离子体聚合工艺是在100～1000W的等离子体功率下进行的。
6、根据权利要求1的方法，其中淀积SiNCH膜的所述步骤是通过所述有机Si化合物的热聚合工艺进行的。
7、根据权利要求6的方法，其中所述热聚合工艺是在室温～600℃的温度下进行的。
8、根据权利要求1的方法，还包括给所述有机Si化合物输送含有N的附加气体源的步骤，其中淀积所述SiNCH膜的所述步骤包括形成所述附加气体源的等离子体的步骤，和将所述等离子体输送到所述反应室中的步骤。
9、一种制造半导体器件的方法，包括以下步骤：
在衬底上形成刻蚀停止膜；
在所述刻蚀停止膜上淀积层间绝缘膜；
构图所述层间绝缘膜以形成开口；
刻蚀所述层间绝缘膜，以便在所述层间绝缘膜中对应所述开口形成凹部；和
利用刻蚀工艺从所述开口选择刻蚀所述刻蚀停止膜，
淀积所述刻蚀停止膜的所述步骤包括：
将所述衬底引入到处理装置的反应室内；
给所述反应室内输送其中含有有机硅氮烷键的有机Si化合物；和
在所述处理室中，利用CVD工艺在所述衬底的表面上由所述有机Si化合物淀积SiNCH膜，作为所述刻蚀停止膜。
10、根据权利要求9的方法，其中所述有机Si化合物具有(SiR1)nNR2、(SiR1NR2)n或(SiR1(NR2)1.5)n的结构式，其中n是大于等于1的整数，R1和R2各是选自氢、烷基、环烃基或乙烯基的任一种。
11、根据权利要求9的方法，其中淀积所述SiNCH膜的所述步骤是如此进行的，使得所述有机Si化合物中的所有硅氮烷键保持在所述SiNCH膜中。
12、根据权利要求9的方法，其中淀积所述SiNCH膜的所述步骤包括所述有机Si化合物的等离子体聚合工艺。
13、根据权利要求12的方法，其中所述等离子体聚合工艺是在100～1000W的等离子体功率下进行的。
14、根据权利要求9的方法，其中淀积SiNCH膜的所述步骤包括所述有机Si化合物的热聚合工艺。
15、根据权利要求14的方法，其中所述热聚合工艺是在室温～600℃的温度下进行的。
16、根据权利要求9的方法，还包括除了所述有机Si化合物之外还给所述反应室输送含有N的附加气体源的步骤，其中形成所述SiNCH膜的所述步骤包括形成所述附加气体源的等离子体的步骤，和将所述等离子体输送到所述反应室中的步骤。
17、根据权利要求9的方法，还包括在所述层间绝缘膜上淀积导体层的步骤，以便经过所述开口填充所述凹部，并利用化学机械抛光工艺去掉位于所述层间绝缘膜上面的一部分所述导体层的步骤。
18、根据权利要求17的方法，其中所述导体层包括Cu层。
19、根据权利要求9的方法，其中所述层间绝缘膜包括有机绝缘膜或无机绝缘膜。
20、根据权利要求9的方法，其中所述层间绝缘膜包括有机硅氧化物膜或掺杂F的SiO2膜。
21、根据权利要求9的方法，其中所述凹部包括互连凹槽和接触孔。
22、一种半导体器件，包括：
衬底；和
形成在所述衬底上的多层互连结构，
所述多层互连结构包括刻蚀停止膜、形成在所述刻蚀停止膜上的层间绝缘膜、形成在所述层间绝缘膜中的互连凹槽、形成在所述层间绝缘膜中并对应所述互连凹槽的接触孔、和填充所述互连凹槽和所述接触孔的导体图形，
其中所述刻蚀停止膜包括SiNCH膜并且其中含有由CnHm表示的任意原子集团，所述任意原子集团键合到Si原子上，其中n是1以上的整数，m是比0大的整数；
其中所述SiNCH膜中含有环硅氮烷键。
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US20030162412A1 (en) 2003-08-28
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TW554442B (en) 2003-09-21
EP1316108B1 (en) 2007-04-18
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WO2002017374A1 (en) 2002-02-28
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EP1316108A1 (en) 2003-06-04
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