TW202246575A - 用於填充間隙之方法以及相關半導體處理設備 - Google Patents

用於填充間隙之方法以及相關半導體處理設備 Download PDF

Info

Publication number
TW202246575A
TW202246575A TW111111215A TW111111215A TW202246575A TW 202246575 A TW202246575 A TW 202246575A TW 111111215 A TW111111215 A TW 111111215A TW 111111215 A TW111111215 A TW 111111215A TW 202246575 A TW202246575 A TW 202246575A
Authority
TW
Taiwan
Prior art keywords
substrate
metal
plasma
distal surface
reaction chamber
Prior art date
Application number
TW111111215A
Other languages
English (en)
Inventor
堤摩西 布朗卡特
Original Assignee
荷蘭商Ａｓｍ Ｉｐ私人控股有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 filed Critical 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司
Publication of TW202246575A publication Critical patent/TW202246575A/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32431—Constructional details of the reactor
    • H01J37/3244—Gas supply means
    • H01J37/32449—Gas control, e.g. control of the gas flow
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H01L21/28562—Selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32082—Radio frequency generated discharge
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/04—Coating on selected surface areas, e.g. using masks
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/04—Coating on selected surface areas, e.g. using masks
    • C23C16/045—Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/34—Nitrides
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • C23C16/45523—Pulsed gas flow or change of composition over time
    • C23C16/45525—Atomic layer deposition [ALD]
    • C23C16/45527—Atomic layer deposition [ALD] characterized by the ALD cycle, e.g. different flows or temperatures during half-reactions, unusual pulsing sequence, use of precursor mixtures or auxiliary reactants or activations
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • C23C16/45523—Pulsed gas flow or change of composition over time
    • C23C16/45525—Atomic layer deposition [ALD]
    • C23C16/45527—Atomic layer deposition [ALD] characterized by the ALD cycle, e.g. different flows or temperatures during half-reactions, unusual pulsing sequence, use of precursor mixtures or auxiliary reactants or activations
    • C23C16/45536—Use of plasma, radiation or electromagnetic fields
    • C23C16/45538—Plasma being used continuously during the ALD cycle
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • C23C16/45523—Pulsed gas flow or change of composition over time
    • C23C16/45525—Atomic layer deposition [ALD]
    • C23C16/45553—Atomic layer deposition [ALD] characterized by the use of precursors specially adapted for ALD
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/50—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
    • C23C16/505—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using radio frequency discharges
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32431—Constructional details of the reactor
    • H01J37/3244—Gas supply means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02312—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour
    • H01L21/02315—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28568—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising transition metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/06—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
    • C23C16/08—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metal halides
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/06—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
    • C23C16/18—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metallo-organic compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
    • H01J2237/32—Processing objects by plasma generation
    • H01J2237/33—Processing objects by plasma generation characterised by the type of processing
    • H01J2237/332—Coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
    • H01L29/4958—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo with a multiple layer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Analytical Chemistry (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Inorganic Chemistry (AREA)
  • Composite Materials (AREA)
  • Ceramic Engineering (AREA)
  • Electromagnetism (AREA)
  • Chemical Vapour Deposition (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

揭示用於填充被包含在一基材中之一間隙特徵的方法及相關系統。方法包含將一包含一或多個間隙特徵之基材提供至一反應室中的一步驟。一或多個間隙特徵包含一近端部分及一遠端部分，近端部分包含一近端表面且遠端部分包含一遠端表面。方法進一步包含使基材經受一電漿處理的一步驟。因此，近端表面被抑制，同時留下遠端表面實質上不受影響。然後，方法包含在遠端表面上選擇性地沉積一含金屬及氮的材料之一步驟。

Description

用於填充間隙之方法以及相關系統及裝置
本揭露大致上係關於適於形成電子裝置之方法和系統。更特定而言，本揭露係關於可用於在間隙、溝槽、及類似者中沉積材料的方法及系統。
半導體裝置之縮放已引發積體電路之速度及密度之顯著改善。然而，隨著大規模積體裝置之佈線間距之小型化，由於現有沉積製程之限制，高深寬比間隙或溝槽（例如，具有三或更高之深寬比之溝槽）之無空隙填充變得愈來愈困難。因此，係有對於高效在半導體基材（例如在邏輯及/或記憶體裝置的上下文中）上填充高深寬比特徵（例如間隙，諸如溝槽）之製程。對於用足以抵抗後續化學機械研磨(CMP)步驟及蝕刻製程的傳導性材料（諸如過渡金屬氮化物）來高效填充高深寬比特徵之製程，係有特別的需求。
本節提出之任何討論，包括問題及解決方案的討論，僅為了提供本揭露背景脈絡之目的而包括在本揭露中。此類討論不應視為承認資訊之任何或全部在完成本發明時為已知或以其他方式構成先前技術。
本揭露之各種實施例係關於間隙填充方法、關於使用此類方法所形成之結構及裝置、以及用於進行方法及/或用於形成結構及/或裝置之設備。本揭露之各種實施例中應對先前方法及系統之缺陷的方式將於下文更詳細討論。
本文中描述一種用於填充一間隙特徵之方法。方法依給定順序包含：在一反應室中將一基材定位在一基材支撐件上之一步驟；使基材經受一電漿處理之一步驟；及，在遠端表面上選擇性地沉積一金屬氮化物之一步驟。基材包含一基材表面。基材表面包含一或多個間隙特徵。一或多個間隙特徵包含一近端部分及一遠端部分，近端部分包含一近端表面且遠端部分包含一遠端表面。電漿處理導致相對於遠端表面選擇性地抑制近端表面。
在一些實施例中，執行複數個超循環。一超循環包含使基材經受一電漿處理之步驟，及在遠端表面上選擇性地沉積一金屬氮化物之步驟。
在一些實施例中，電漿預處理包含使基材暴露至一氮電漿。
在一些實施例中，在遠端表面上選擇性地沉積金屬氮化物的步驟包含一循環製程。循環製程包含複數個子循環。一子循環依給定順序包含：將基材暴露至一金屬前驅物之一步驟；及，使基材暴露至一氮反應物之一步驟。使基材暴露至一金屬前驅物的步驟導致在遠端表面上形成化學吸附金屬前驅物。使基材暴露至一氮反應物之步驟致使氮反應物與化學吸附金屬前驅物起反應。因此，一金屬氮化物形成於遠端表面上。
在一些實施例中，使基材暴露至一金屬前驅物之步驟及使基材暴露至一氮反應物之步驟係由一子循環內沖洗來分開。
在一些實施例中，後續子循環係由一子循環間沖洗來分開。
在一些實施例中，金屬包含一過渡金屬。
在一些實施例中，過渡金屬包含鈦。
在一些實施例中，金屬前驅物包含一或多個烷基胺配位子。
在一些實施例中，金屬前驅物具有M(NR 2) n之一通式，其中M係一金屬，R係一直鏈或支鏈C1至C4烷基，且n係從至少2到至多5之一整數。
在一些實施例中，R係甲基。
在一些實施例中，n係4。
在一些實施例中，金屬前驅物包含一金屬鹵化物。
在一些實施例中，金屬鹵化物包含一氯化物。
在一些實施例中，金屬鹵化物包含TiCl 4。
在一些實施例中，氮反應物包含NH 3。
在一些實施例中，基材維持在至少50 ⁰C到至多300 ⁰C之一溫度。
在一些實施例中，在遠端表面上選擇性地沉積一材料之步驟係以每子循環至少0.01 Å至每子循環至多1.0 Å之一生長速率完成。
在一些實施例中，使基材經受一電漿處理之步驟及在遠端表面上選擇性地沉積一金屬氮化物之步驟係由一電漿後沖洗來分開。
本文中進一步描述一種半導體處理設備。半導體處理設備包含一反應室、一加熱器、一電漿氣體源、一電漿模組、一金屬前驅物源、一氮反應物源、及一控制器。反應室包含一基材支撐件用於支撐一基材。基材包含一或多個間隙特徵。加熱器經建構且配置以在反應室中加熱基材。電漿氣體源經由一電漿閥與反應室流體連通。電漿模組包含一射頻功率源，射頻功率源經建構且配置以在反應室中生成一電漿。金屬前驅物源經由一或多個金屬前驅物閥與反應室流體連接。氮反應物源經由一或多個氮反應物閥與反應室流體連接。控制器經組態用於致使設備進行如本文中所描述之一方法。
所屬技術領域中具有通常知識者從下列參考附圖之某些實施例的詳細描述將明白此等及其他實施例。本發明並未受限於任何所揭示特定實施例。
下文所提供之方法、結構、裝置及系統之例示性實施例的描述僅係例示性且僅係意欲用於闡釋之目的；下列描述並非意欲限制本揭露或申請專利範圍之範疇。此外，列舉具有所陳述特徵之多個實施例不意欲排除具有額外特徵之其他實施例或納入所陳述特徵之不同組合的其他實施例。例如，各種實施例係提出作為例示性實施例，並可列舉於附屬項中。除非另有註明，例示性實施例或其等之組件（組分）可組合或可彼此分開應用。
在本揭露中，「氣體(gas)」可包括在常溫及常壓(NTP)下為氣體、汽化固體及/或汽化液體之材料，並取決於上下文可由單一氣體或一氣體混合物構成。除了製程氣體以外的氣體（亦即不穿行通過氣體分配總成、多埠口注入系統、其他氣體分配裝置、或類似者所引入的氣體）可用於例如密封反應空間，並可包括一密封氣體，諸如一稀有氣體。如本文中所使用之用語「稀有氣體(rare gas)」及「鈍氣(noble gas)」可互換使用。在一些情況下，用語「前驅物(precursor)」可指參與產生另一化合物之化學反應的化合物，且特定而言指構成一膜基質或膜之主要骨架、或納入於一膜中作為其構成部分的化合物；用語「反應物(reactant)」可與用語前驅物互換使用。
如本文中所使用，用語「基材(substrate)」可指可用以形成或在其上可形成裝置、電路、或膜之任何（多個）下伏材料。基材可包括塊材，諸如矽（例如單晶矽）、其他IV族材料（諸如鍺）、或其他半導體材料（諸如II-VI族或III-V族半導體），並可包括上覆或下伏於塊材的一或多層。
在一些實施例中，「金屬」係指作為元素固體而形成金屬性材料之元素。在一些實施例中，「金屬」包括作為元素固體而形成半導體材料之元素。
進一步言，在本揭露中，變量之任兩個數字可構成變量之可工作範圍，且所指示之任何範圍可包括或排除端點。額外地，所指示的變數之任何數值（不管些數值是否冠以「約」來指示）可指精確值或近似值並包括等效值，且可指平均值、中間值、代表值、多數值、或類似者。進一步言，在本揭露中，於一些實施例中，用語「包括(including)」、「由……構成(constituted by)」、及「具有(having)」獨立地指「典型或廣泛地包含(typically or broadly comprising)」、「包含(comprising)」、「基本上由……所組成(consisting essentially of)」或「由……所組成(consisting of)」。在本揭露中，於一些實施例中，任何已定義之意義不必然排除通常及慣用意義。
如本文中所使用，用語「包含(comprising)」係指包括某些特徵，但其不排除存在其他特徵，只要其不使申請專利範圍或實施例無法工作即可。在一些實施例中，用語「包含(comprising)」包括「由……所組成(consisting)」。如本文所使用，用語「由……所組成(consisting)」指示除了跟隨所述措辭的特徵，無其他特徵存在於設備/方法/產品中。當用語「由……所組成(consisting)」用於指一化學化合物時，其指示化學化合物僅含有所列出的組分。
如本文中所使用，用語「沖洗(purge)」係指從反應室中移除前驅物及/或反應性物種的一製程步驟。在一沖洗期間，可將一惰性或實質上惰性氣體提供至反應室。額外地或替代地，反應室可在一沖洗期間排空。
本文中描述一種用於填充一間隙特徵之方法。間隙特徵係包含在基材中，並可位於基材表面處或在基材表面附近。可選地，基材可包含多個間隙特徵，例如複數個間隙特徵。間隙特徵包含近端部分及遠端部分，近端部分包含近端表面且遠端部分包含遠端表面。合適基材包括半導體晶圓，例如矽晶圓。本文方法可在製造各種半導體裝置期間使用，且對於填充具有一高深寬比及一特別小的寬度的間隙特徵係特別有用的，例如具有小於10 nm之寬度及高於2、或5、或10、或20的深寬比。此類間隙可藉由如本文中所描述之方法有利地填充，而不形成任何接縫或空隙。
方法包含將基材定位於基材支撐件上之步驟。基材支撐件位於反應室中。基材包含一或多個間隙特徵。間隙特徵包含近端部分及遠端部分，近端部分包含近端表面且遠端部分包含遠端表面。應理解，間隙特徵之近端部分係指間隙特徵最靠近基材之表面的彼部分，且間隙特徵之遠端部分係指間隙特徵之距基材之表面離最遠之部分。方法進一步包含使基材經受電漿處理之步驟，及在遠端表面上選擇性地沉積金屬氮化物之步驟。可選地，在使基材經受電漿處理之步驟與在遠端表面上選擇性地沉積金屬氮化物之步驟之間進行沖洗。應理解，在沖洗期間反應室中無電漿生成。
應理解，前述步驟依下列順序施行：將基材定位於基材支撐件上、使基材經受電漿處理、及在遠端表面上選擇性地沉積金屬氮化物。
使基材經受電漿處理之步驟導致相對於遠端表面之對近端表面的選擇性抑制。換言之，電漿處理導致相對於遠端表面之近端表面上活性表面位點的減少。換言之，相較於遠端表面，電漿處理使前驅物在近端表面上更不容易吸收。因此，當後續沉積金屬氮化物時，金屬氮化物相對於近端表面選擇性地沉積於遠端表面上。換言之，遠端表面上之金屬氮化物的生長速率高於近端表面上之金屬氮化物的生長速率。例如，電漿處理可優先地在近端表面上去活化反應性表面位點，同時留下遠端表面上的類似表面位點相對不受影響。必然地，且當在遠端表面上選擇性地生長金屬氮化物包含使基材暴露至金屬前驅物時，金屬前驅物優先地在遠端表面上化學吸附，而非近端表面。然後當基材暴露至氮反應物時，金屬氮化物優先地形成於遠端表面上。
在一些實施例中，方法包含用金屬氮化物整個填充間隙特徵。此之完成可例如藉由重複如本文中所描述的循環製程直至整個間隙特徵被可轉換層填充為止。
在一些實施例中，電漿預處理包含使基材暴露至一氮電漿。在一些實施例中，N 2用作電漿氣體，同時使基材暴露至氮電漿。在一些實施例中，含氮電漿係NH 3電漿。應理解，N 2電漿係指一電漿，其中電漿氣體包含N 2。應理解，NH 3電漿係指一電漿，其中電漿氣體包含NH 3。應理解，其他電漿係類推地定義。
在一些實施例中，電漿預處理包含使基材經受鈍氣電漿。在一些實施例中，鈍氣電漿係氬電漿。在一些實施例中，諸如Ar電漿之鈍氣電漿可用於活化或抑制某些表面。在一些實施例中，諸如Ar電漿之鈍氣電漿可用於移除表面封端，諸如-OH及-NH表面封端中之至少一者。應理解，氮電漿係指其中使用含氮氣體作為電漿氣體的電漿。類似地，鈍氣電漿係指其中使用包含鈍氣之氣體作為電漿氣體的電漿。類似地，氬電漿係指其中使用包含氬的氣體作為電漿氣體的電漿。應理解，其他電漿係類推地定義。
應理解，電漿預處理之應用導致近端表面的抑制，而留下遠端表面實質上不受影響，或至少所受影響少於近端表面。換言之，可合適地使得近端表面對於後續可被提供至反應室的金屬前驅物的反應性較少。再以不同方式陳述，使基材經受電漿預處理可在間隙特徵中導致抑制梯度。特定言之，抑制在間隙之近端部分強於間隙之遠端部分。換言之，抑制從間隙之近端部分至間隙之遠端部分逐漸減少。在本發明不受限於任何特定理論或操作模式的情形下，咸信近端表面之抑制係由基材表面附近的反應性表面基團的空乏所致使，反之，咸信遠端表面附近間隙中較深處（亦即在溝槽底部附近）的反應性表面基團係較少或不受電漿預處理的影響。
在一些實施例中，電漿預處理導致從近端表面朝向遠端表面的一鈍化梯度，亦即鈍化強度的逐漸改變。在此一情況下，將基材暴露至前驅物的步驟可導致每單位面積的化學吸附前驅物密度從遠端表面至上表面的逐漸改變。後續使基材暴露至氮反應物，然後允許含氮物種與經化學吸附前驅物起反應以形成金屬氮化物。由於相較於上表面，更多前驅物被化學吸附至遠端表面上，故在遠端表面上有相較於上表面更多的金屬氮化物形成。換言之，金屬氮化物以由下而上的方式生長。
在一些實施例中，方法包含執行複數個超循環。一超循環包含使基材經受電漿處理的步驟，及在遠端表面上選擇性地沉積金屬氮化物的步驟。超循環之量可經合適地選定，使得在如本文中所描述之方法結束時，已在遠端表面上沉積所欲厚度的金屬氮化物。在一些實施例中，方法包含執行超循環達至少5次到至多10000次、或從至少10次到至多5000次、或從至少20次到至多2000次、或從至少50次到至多1000次、或從至少100次到至多500次。在一些實施例中，方法包含執行超循環從至少5次到至多50次、或從至少10次到至多20次。在一些實施例中，接續的超循環彼此係藉由沖洗而分開。應理解，在沖洗期間反應室中無電漿生成。在一些實施例中，如本文中所描述的循環製程包含從至少2個超循環到至多20000個超循環。例如，循環沉積製程可包含2個超循環、3個超循環、5個超循環、10個超循環、20個超循環、30個超循環、60個超循環、100個超循環、200個超循環、500個超循環、1000個超循環、2000個超循環、5000個超循環、或10000個超循環。
在一些實施例中，在遠端表面上選擇性地沉積金屬氮化物係熱性完成。換言之，且在一些實施例中，在遠端表面上選擇性地沉積金屬氮化物時，在反應室中無電漿生成。此可改善如本文中所描述之方法的間隙填充性質。
在一些實施例中，在遠端表面上選擇性地沉積金屬氮化物的步驟包含一循環製程。循環製程包含複數個子循環。一子循環依下列順序包含：使基材暴露至金屬前驅物，及使基材暴露至氮反應物。使基材暴露至金屬前驅物導致在遠端表面上形成化學吸附金屬前驅物。後續地使基材暴露至氮反應物然後允許氮反應物與化學吸附金屬前驅物起反應。因此，一金屬氮化物形成於遠端表面上。
在一些實施例中，循環製程係熱性。換言之，且在一些實施例中，在子循環期間在反應室中無電漿生成。換言之，且在一些實施例中，在使基材暴露至金屬前驅物時及使基材暴露至氮反應物時，在反應室中無電漿生成。
在一些實施例中，在遠端表面上選擇性沉積金屬氮化物的步驟係以至少0.1 Å/子循環到至多10 Å/循環的生長速率完成，例如從至少0.2 Å/子循環到至多3 Å/子循環、或從至少0.3到至多 1 Å/子循環的生長速率。例如，金屬氮化物係以0.49 Å/子循環的生長速率在遠端表面上沉積。在一些實施例中，近端表面上之生長速率較上表面上者更慢至少2到至多20倍。在一些實施例中，近端表面上之生長速率較上表面上者更慢至少2到至多5倍。在一些實施例中，近端表面上之生長速率較上表面上者更慢至少5到至多10倍。在一些實施例中，近端表面上之生長速率較上表面上者更慢至少10到至多20倍。在一些實施例中，近端表面上之生長速率係少於0.1 Å/子循環。在一些實施例中，近端表面上之生長速率係0 Å/子循環。
在一些實施例中，如本文中所描述的循環製程每超循環包含從至少2個子循環到至多20000個子循環。例如，循環沉積製程可各超循環包含2個子循環、3個子循環、5個子循環、10個子循環、20個子循環、30個子循環、60個子循環、100個子循環、200個子循環、500個子循環、1000個子循環、2000個子循環、5000個子循環、10000個子循環、或更多。
可選地，將基材暴露至金屬前驅物的步驟係有一沖洗跟隨。可選地，後續子循環係由沖洗來分開。應理解，在沖洗期間，在反應室中無電漿生成。
應理解，使基材暴露至金屬前驅物的步驟導致金屬前驅物在遠端表面上優先化學吸附。換言之，藉由將基材暴露至金屬前驅物，相較於已電漿鈍化的近端表面有更多前驅物化學吸附至未鈍化的遠端表面上。
如本文中所描述之方法的任何兩個後續製程步驟可由沖洗步驟分開。
因此，且在一些實施例中，使基材經受電漿處理之步驟及在遠端表面上選擇性地沉積金屬氮化物之步驟由電漿後沖洗來分開。
額外地或替代地，且在一些實施例中，使基材暴露至金屬前驅物之步驟及使基材暴露至氮反應物之步驟由子循環內沖洗來分開。
額外地或替代地，且在一些實施例中，後續子循環由子循環間沖洗來分開。
在一些實施例中，使基材經受電漿處理的步驟持續從至少1 s到至多100 s、或從至少1 s到至多2 s、或從至少2 s到至多5 s、或從至少5 s到至多10 s、或從至少10 s到至多20 s、或從至少20 s到至多50 s、或從至少50 s到至多100 s。
在一些實施例中，使基材暴露至金屬前驅物持續從至少0.01 s到至多100 s、或從至少0.01 s到至多0.02 s、或從至少0.02 s到至多0.05 s、或從至少0.05 s到至多0.1 s、或從至少0.1 s到至多0.2 s、或從至少0.2 s到至多0.5 s、或從至少0.5 s到至多1 s、或從至少1 s到至多2 s、或從至少2 s到至多5 s、或從至少5 s到至多10 s、或從至少10 s到至多20 s、或從至少20 s到至多50 s、或從至少50 s到至多100 s。
在一些實施例中，使基材暴露至氮反應物之步驟持續從至少0.01 s到至多100 s、或從至少0.01 s到至多0.02 s、或從至少0.02 s到至多0.05 s、或從至少0.05 s到至多0.1 s、或從至少0.1 s到至多0.2 s、或從至少0.2 s到至多0.5 s、或從至少0.5 s到至多1 s、或從至少1 s到至多2 s、或從至少2 s到至多5 s、或從至少5 s到至多10 s、或從至少10 s到至多20 s、或從至少20 s到至多50 s、或從至少50 s到至多100 s。
在一些實施例中，子循環間沖洗持續從至少0.01 s到至多100 s、或從至少0.01 s到至多0.02 s、或從至少0.02 s到至多0.05 s、或從至少0.05 s到至多0.1 s、或從至少0.1 s到至多0.2 s、或從至少0.2 s到至多0.5 s、或從至少0.5 s到至多1 s、或從至少1 s到至多2 s、或從至少2 s到至多5 s、或從至少5 s到至多10 s、或從至少10 s到至多20 s、或從至少20 s到至多50 s、或從至少50 s到至多100 s。
在一些實施例中，子循環內沖洗持續從至少0.01 s到至多100 s、或從至少0.01 s到至多0.02 s、或從至少0.02 s到至多0.05 s、或從至少0.05 s到至多0.1 s、或從至少0.1 s到至多0.2 s、或從至少0.2 s到至多0.5 s、或從至少0.5 s到至多1 s、或從至少1 s到至多2 s、或從至少2 s到至多5 s、或從至少5 s到至多10 s、或從至少10 s到至多20 s、或從至少20 s到至多50 s、或從至少50 s到至多100 s。
在一些實施例中，氮反應物包含NH 3。在一些實施例中，氮反應物包含N 2H 2。
在一些實施例中，金屬前驅物中所包含的金屬包含一過渡金屬。在一些實施例中，金屬前驅物中所包含的金屬由過渡金屬所組成。合適的過渡金屬包括Sc、Ti、V、Cr、Mn、Fe、Co、Ni、Cu、Zn、Y、Zr、Nb、Mo、Tc、Ru、Rh、Cd、Hf、Ta、W及Re。在一些實施例中，過渡金屬包含鈦。在一些實施例中，過渡金屬由鈦所組成。
在一些實施例中，金屬前驅物中所包含之金屬包含稀土元素。在一些實施例中，金屬前驅物中所包含之金屬由稀土元素所組成。合適之稀土元素包括鑭系元素，諸如La、Ce、Pr、Nd、Pm、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb、及Lu。
在一些實施例中，金屬前驅物可包含一或多個烷基胺配位子。在一些實施例中，金屬前驅物包含選自NH 2、NHR i、及NR iR ii的一或多個配位子，且R i及R ii中之至少一者係一C1至C4烷基。
在一些實施例中，金屬前驅物具有M(NR 2) n之通式，其中M為金屬，R為直鏈或支鏈的C1至C4烷基，且為至少2到至多5之整數。在一些實施例中，R係甲基。在一些實施例中，n係4。在一些實施例中，金屬前驅物包含肆(二甲基醯胺基)鈦(IV)。
在一些實施例中，金屬前驅物包含一金屬鹵化物。
例示性金屬鹵化物包括氟化物、氯化物、溴化物、及碘化物。在一些實施例中，金屬前驅物包含氯化物。
在一些實施例中，金屬前驅物包含過渡金屬鹵化物。在一些實施例中，金屬前驅物包含過渡金屬氟化物。在一些實施例中，金屬前驅物包含過渡金屬氯化物。在一些實施例中，金屬前驅物包含過渡金屬溴化物。在一些實施例中，金屬前驅物包含過渡金屬碘化物。
在一些實施例中，金屬前驅物係選自鹵化鋯、鹵化鉿、鹵化鈮、鹵化鉭、鹵化釩、鹵化鉬、鹵化鈦、及鹵化鎢。
在一些實施例中，金屬前驅物係選自氟化鋯、氟化鉿、氟化鈮、氟化鉭、氟化釩、氟化鉬、氟化鈦、及氟化鎢。
在一些實施例中，金屬前驅物係選自氯化鋯、氯化鉿、氯化鈮、氯化鉭物、氯化釩、氯化鉬、氯化鈦、及氯化鎢。
在一些實施例中，金屬前驅物係選自溴化鋯、溴化鉿、溴化鈮、溴化鉭、溴化釩、溴化鉬、溴化鈦、及溴化鎢。
在一些實施例中，金屬前驅物係選自碘化鋯、碘化鉿、碘化鈮、碘化鉭、碘化釩、碘化鉬、碘化鈦、及碘化鎢。
在一些實施例中，金屬前驅物係選自由ZrCl 4、HfCl 4、NbCl 4、TaCl 5、VCl 5、Mo 2Cl 10、TiI 4、及WCl 6所組成之列表。在一些實施例中，金屬前驅物包含TiCl 4。
在一些實施例中，金屬前驅物包含IVA族元素之鹵化物。在一些實施例中，金屬前驅物包含鹵化矽。在一些實施例中，金屬前驅物包含鹵化鍺。在一些實施例中，金屬前驅物包含氯化矽。在一些實施例中，金屬前驅物包含氯化鍺。在一些實施例中，金屬前驅物包含溴化矽。在一些實施例中，金屬前驅物包含溴化鍺。在一些實施例中，金屬前驅物包含碘化矽。在一些實施例中，金屬前驅物包含碘化鍺。在一些實施例中，金屬前驅物選自SiCl 4、SiIH 2、Si 2Cl 6、及GeCl 4。
在一些實施例中，基材係維持在至少50 °C到至多600 °C的溫度、或在至少50 °C到至多400 °C的溫度、或在至少100 °C到至多350 °C的溫度、或在至少150 °C到至多200 °C的溫度、或在至少200 °C到至多250 °C的溫度、或在至少250 °C到至多300 °C的溫度。
在一些實施例中，反應室維持之壓力在至少0.1托到至多200托、或至少0.2托到至多100托、或至少0.5托到至多50托、或至少1托到至多20托、或至少2托到至多10托，例如反應室可維持在5托的壓力。在一些實施例中，反應室係維持在至少1托到至多20托的壓力。
在一些實施例中，在遠端表面上選擇性地沉積金屬氮化物之步驟完成的生長速率係至少每子循環0.1 Å到至多每子循環1.5 Å、或每子循環至少0.2 Å至每子循環至多1 Å、或每子循環至少0.3 Å到每子循環至多1 Å，應理解，此等生長速率係指在遠端表面上金屬氮化物的生長速率。
在一些實施例中，且在遠端表面上選擇性地沉積金屬氮化物之步驟期間，近端表面上的金屬氮化物的生長率係在遠端表面上的金屬氮化物的生長率之從至少0%到至多99%，或近端表面上之金屬氮化物的生長速率係在遠端表面上之金屬氮化物的生長速率之從至少0%到至多1%，或近端表面上之金屬氮化物的生長率係遠端表面上金屬氮化物的生長速率之從至少1%到至多2%，或近端表面上之金屬氮化物的生長率係遠端表面上金屬氮化物的生長速率之從至少2%到至多5%，或近端表面上之金屬氮化物的生長速率係在遠端表面上之金屬氮化物的生長速率之從至少5%到至多10%，或近端表面上之金屬氮化物的生長速率係在遠端表面上之金屬氮化物的生長速率之從至少10%到至多20%，或近端表面上之金屬氮化物的生長速率係在遠端表面上之金屬氮化物的生長速率之從至少20%到至多50%，或近端表面上之金屬氮化物的生長速率係在遠端表面上之金屬氮化物的生長速率之從至少50%到至多90%，或近端表面上之金屬氮化物的生長速率係在遠端表面上之金屬氮化物的生長速率之從至少90%到至多95%，或近端表面上之金屬氮化物的生長速率係在遠端表面上之金屬氮化物的生長速率之從至少95%到至多99%。
本文中進一步描述一種半導體處理設備。半導體處理設備包含反應室、基材加熱器、電漿氣體源、電漿模組、金屬前驅物源、氮反應物源、及控制器。反應室包含一基材支撐件用於支撐一基材。基材包含一或多個（例如複數個）間隙特徵。加熱器經建構且配置以在反應室中加熱基材。電漿氣體源經由一電漿閥與反應室流體連通。電漿模組包含一射頻功率源，其經建構且配置以在反應室中生成電漿。金屬前驅物源經由一或多個金屬前驅物閥與反應室流體連接。氮反應物源經由一或多個氮反應物閥與反應室流體連接。控制器經組態用於致使設備進行如本文中所描述之一方法。
可選地，設備經組態用於藉由一載體氣體將前驅物中之至少一者提供至反應室。合適的載體氣體包括鈍氣。換言之，在一些實施例中，半導體處理系統包含氣體注入系統，其包含一採用載體氣體用於將金屬前驅物載送至一或多個反應室的前驅物輸送系統。
本文提供之方法可在任何合適之設備中執行，包括在如圖1所示之半導體處理系統的實施例中。圖1係可用於本發明一些實施例中之電漿增強原子層沉積(PEALD)設備的一示意圖。在此圖式中，藉由在一反應室(3)之內部(11)（反應區）中提供平行且彼此面對的一對導電性平板電極(2、4)，並將來自功率源(25)之RF功率（例如，13.56 MHz及/或27 MHz）施加至一側且將另一側(12)電氣接地，可在電極之間生成電漿。在金屬前驅物被提供至反應室的步驟期間、在氮反應物被提供至反應室的步驟期間、或在後續處理步驟之間的沖洗期間，半導體處理設備不需要生成電漿，且因此，在彼等步驟或沖洗期間不需要施加RF功率至電極中之任一者。溫度調節器可提供在下部平台(2)中，亦即下部電極中。基材(1)係放置於其上，且其溫度係保持恆定在一給定溫度。上部電極(4)亦可充當噴淋板，且各種氣體（諸如電漿氣體、反應物氣體、及/或稀釋氣體（若有）還有前驅物氣體）可各別通過氣體管線(21)及氣體管線(22)以及通過噴淋板(4)而引入至反應室(3)中。額外地，反應室(3)中提供一具有排氣管線(17)的圓管(13)，反應室(3)之內部(11)中之氣體通過其被排出。額外地，轉移室(5)設置於反應室(3)下方，且設有氣體密封管線(24)，以將密封氣體經由轉移室(5)之內部(16)引入至反應室(3)之內部(11)中，其中提供用於分開反應區與轉移區的分隔板(14)。當注意的是，此圖式中省略一閘閥，而晶圓透過閘閥可被移送進或出轉移室(5)。轉移室亦設有排氣管線(6)。在一些實施例中，氧化矽之沉積及表面處理係在相同的反應空間中進行，使得所有步驟可連續地實行，而不需要排空反應室、抽空反應室、或將基材暴露至大氣的中間步驟。
圖2顯示包含間隙特徵(210)之基材(200)的示意性表示。間隙特徵(210)包含近端部分(211)及遠端部分(212)。近端部分(211)包含上表面，且遠端部分(212)包含遠端表面。藉由使基材(200)經受電漿處理，可實質上抑制近端表面。換言之，相較於遠端表面，第一及第二電漿處理可合適地使得近端表面對於前驅物相對不具反應性。
圖3顯示如本文中所描述之方法的實施例之示意性表示。方法包含將基材定位於基材支撐件上之步驟(311)。基材包含間隙特徵。基材然後經受如本文中所描述的電漿處理(312)。可選地，反應室然後使用電漿後沖洗(315)來沖洗。沖洗可例如藉由實質上惰性氣體（諸如鈍氣）來完成。例示性鈍氣包括He、Ne、Ar、Xe、及Kr。替代地，沖洗可藉由含氮氣體混合物完成，例如藉由包含N 2或由其所組成之沖洗氣體。方法進一步包含一藉由本文中所描述之技術而在間隙特徵的遠端表面上沉積金屬氮化物的步驟(316)。可選地，然後使用沉積後沖洗(317)來沖洗反應室。應理解，在沖洗期間，在反應室中無電漿生成。可將自使基材經受電漿處理(312)至在間隙特徵之遠端表面上沉積金屬氮化物之步驟(316)的步驟可選地重複(319)一或多次，藉此導致複數個超循環，超循環包含後續的電漿處理及跟隨的沉積步驟。可選地，後續超循環由沖洗來分開。因此，金屬氮化物沉積於間隙特徵中。當在間隙特徵中已沉積所欲量的金屬氮化物，方法結束(318)。
圖4顯示一方法的部分之實施例的示意性表示，方法用於在基材中所包含的間隙特徵之遠端表面上選擇性地沉積金屬氮化物。圖4中所示的方法之部分對應於在圖3中所示之在遠端表面上沉積金屬氮化物的步驟(316)，且在使基材經受電漿處理之步驟之後及可選地在跟隨此一步驟的沖洗之後開始(411)。然後將基材暴露至金屬前驅物(412)，金屬前驅物選擇性地化學吸附在遠端表面上，如本文中所描述。可選地，然後沖洗反應室(413)。方法然後包含使基材暴露至氮反應物的步驟(414)。可選地，然後沖洗反應室(415)。應理解，在沖洗期間，在反應室中無電漿生成。可將自將基材暴露至金屬前驅物(412)至使基材暴露至氮反應物之步驟(414)的步驟可選地重複(417)一或多次，藉此導致複數個子循環。因此，金屬氮化物沉積於間隙特徵中。當在間隙中已沉積所欲量的金屬氮化物，方法結束(416)。
圖5繪示依據本揭露之實例之例示性結構(500)。裝置或結構(500)包括基材(502)、介電材料(504)、及含金屬氮化物層(506)，金屬氮化物層之至少一部分可根據本文中所描述之方法沉積。當層(506)之至少一部分使用如本文中所描述的方法形成時，其成分之濃度可從層(506)之底部至層(506)之頂部變化，例如，藉由控制在一或多個沉積循環期間的前驅物及/或反應物之量及/或各別之脈衝時間。在一些情況下，層(506)可具有化學計量組成。此層(506)之功函數及其他性質可藉由更改其組成而更改。根據如本文中所描述之方法沉積的層(506)可包括雜質，諸如鹵化物、氫、及類似者。在一些實施例中，單獨或組合的雜質含量可少於一原子百分比、少於0.2原子百分比、或少於0.1原子百分比、或少於0.05原子百分比。
藉由如本文中所描述之方法沉積其至少部分的層(506)之厚度可根據應用而變化。舉例而言，此層(506)具有可從至少5 nm到至多20 nm之厚度。
根據本文中所描述之方法沉積其至少部分之層(506)的功函數可係＞ 4.0 eV、＞ 4.1 eV、＞ 4.2 eV、＞ 4.3 eV、＞ 4.4 eV、＞ 4.5 eV、＞ 4.6 eV、＞ 4.7 eV、＞ 4.8 eV、＞ 4.9 eV、＞ 4.95 eV、或＞ 5.0 eV。替代地，根據本文中所描述之方法沉積其至少部分之層(506)的功函數可係＜ 4.0 eV、＜ 4.1 eV、＜ 4.2 eV、＜ 4.3 eV、＜ 4.4 eV、＜ 4.5 eV、＜ 4.6 eV、＜ 4.7 eV、＜ 4.8 eV、＜ 4.9 eV、＜ 4.95 eV、或＜ 5.0 eV。
介電材料(504)包含界面層(508)及主體層(510)。界面層(508)可例如包含氧化矽層、矽酸鹽層、或其等之混合物。主體層(510)可包含高k介電層。在一些情況下，界面層(508)可不存在，或可不以可察覺程度存在。高k材料(510)可係或可包括例如具有大於約7之介電常數的金屬性氧化物。在一些實施例中，高k材料具有一高於氧化矽之介電常數的介電常數。例示性高k材料包括以下中之一或多者：氧化鉿(HfO 2)、氧化鉭(Ta 2O 5)、氧化釩(VO 2)、氧化鋯(ZrO 2)、氧化鈮(Nb 2O 5)、氧化鈦(TiO 2)、氧化鋁(Al 2O 3)、或氧化鑭(La 2O 3)、其等之混合物、及其等之積層物。其他例示性高k材料包括矽酸鹽，諸如矽酸鉿(HfSiO x)、矽酸鑭(LaSiO x)、矽酸鈦(TiSiO x)、與矽酸銩(TmSiO x)等等。在所繪示實例中，基材(502)包括源極區域(514)、汲極區域(516)、以及通道區域(518)。雖然繪示為水平結構，依據本揭露之實例的結構及裝置可包括垂直及/或三維結構及裝置（諸如鰭式FET裝置及環繞式閘極MOSFET）。
圖6繪示例示性DRAM電容器(600)。在所示的實施例中，電容器包括頂部電極(610、670)，其包含兩部分（亦即，內殼及外殼）。儘管如此，頂部電極可僅包含一個部分，或可包含多於兩個部分（例如三個或更多個部分）。應理解，圖6之實施例中的頂部電極(610、670)的兩個部分係彼此電氣連接（連接未示），亦即，應理解在正常操作期間，其等係保持在相同或大約相同的電位。頂部電極(610、670)包含藉由於如本文中所描述的方法所沉積的一層。例如，頂部電極(610、670)的厚度可例如具有至少0.5 nm到5.0 nm、或至少1.0 nm到至多4.0 nm、或至少2.0 nm到至多3.0 nm、或至少0.5 nm到至多2.5 nm、或至少0.6 nm到至多2.0 nm、或至少0.7 nm到至多1.5 nm。DRAM電容器(600)進一步包含底部電極(640)。底部電極(640)可包含一藉由如本文中所描述之方法所沉積的層。在一些實施例中，底部電極(640)的組成與頂部電極(610、670)的組成相等。替代地，底部電極(640)的組成可不同於頂部電極(610、670)的組成。例如，底部電極(640)可具有至少1.0 nm到至多10.0 nm、或至少3.0 nm到至多7.0 nm、或至少0.5 nm至5.0 nm、或至少1.0 nm到至多4.0 nm、或至少2.0 nm到至多3.0 nm、或至少0.5 nm到至多2.5 nm、或至少0.6 nm到至多2.0 nm、或至少0.7 nm到至多1.5 nm的厚度。底部電極(640)藉由一或多個介電層(620、630)來與頂部電極(610)的外殼分開。所示之實施例配備兩個介電層(620、630)。一或多個介電層(620、630)可包含一高k介電質。例如，高k介電質可選自包含以下之列表：氧化鉿(HfO 2)、氧化鉭(Ta 2O 5)、氧化釩(VO 2)、氧化鈮(Nb 2O 5)、氧化鋯(ZrO 2)、氧化鈦(TiO 2)、氧化鋁(Al 2O 3)、氧化鑭(La 2O 3)、其等之混合物、及其等之積層物。其他例示性高k材料包括矽酸鹽，諸如矽酸鉿(HfSiO x)、矽酸鑭(LaSiO x)、矽酸鈦(TiSiO x)、與矽酸銩(TmSiO x)等等。在一些實施例中，介電層(620)具有相同於介電層(630)的成分。在一些實施例中，介電層(620)具有與介電層(630)不同的組成。例如，兩介電層(620、630)的組合厚度可係從至少0.5 nm到至多10.0 nm、或至少1.0 nm到至多8.0 nm、或至少2.0 nm到至多6.0 nm、或至少3.0 nm到至多4.0 nm。頂部電極(670)的內殼係經由一或多個介電層(650、660)而與底部電極(640)分開。所示之實施例配備兩個此類介電層。一或多個介電層(650、660)可包含高k介電質。例如，高k介電質可選自包含以下之列表：氧化鉿(HfO 2)、氧化鉭(Ta 2O 5)、氧化釩(VO 2)、氧化鈮(Nb 2O 5)、氧化鋯(ZrO 2)、氧化鈦(TiO 2)、氧化鋁(Al 2O 3)、氧化鑭(La 2O 3)、及其等之混合物/積層物。其他例示性高k材料包括矽酸鹽，諸如矽酸鉿(HfSiO x)、矽酸鑭(LaSiO x)、矽酸鈦(TiSiO x)、與矽酸銩(TmSiO x)等等。在一些實施例中，介電層(650)具有與介電層(660)相同的組成。在一些實施例中，介電層(650)具有與介電層(660)不同的組成。例如，介電層(650、660)的組合厚度可係從至少0.5 nm到至多10.0 nm、或至少1.0 nm到至多8.0 nm、或至少2.0 nm到至多6.0 nm、或至少3.0 nm到至多4.0 nm。在一些實施例中，頂部電極(610)之外殼與底部電極(640)之間的一或多個介電層(620、630)之厚度等於頂部電極(670)之內殼與底部電極(640)之間的一或多個介電層(650、660)之厚度（例如，在少於2.0 nm、或少於1.5 nm、或少於1.0 nm、或少於0.5 nm、或少於0.4 nm、或少於0.3 nm、或少於0.2 nm、或少於0.1 nm的誤差範圍內）。在DRAM電容器(680)中，間隙填充介電質(680)可設置在中心。例示性的間隙填充介電質包括低k介電質，例如SiOC、SiOCN、及類似者。
圖7繪示VNAND單元的一部分，即接觸件及電荷捕捉總成(700)。接觸件及電荷捕捉總成(700)包含金屬層(710)。金屬層(710)可由諸如銅、鎢等的金屬製成。替代地，金屬層(710)可包含一根據如本文中所描述之方法所沉積的層。如圖7所繪示，金屬層(710)可用襯體(720)加襯。襯體可改善黏附及/或可防止金屬（例如銅或鎢）從金屬層(710)向外擴散或至少將其最小化。有利地，襯體(720)包含一藉由如本文中所描述之方法所沉積的層。接觸件及電荷捕捉總成(700)包含電荷捕捉層(740)。電荷捕捉層(740)係定位在兩個介電層(730、750)之間。電荷補捉層可包含一傳導層，諸如，例如氮化矽。額外地或替代地，電荷捕捉層可包含一藉由如本文中所描述之方法所沉積的層。介電層(730)中的一者係相鄰於襯體(720)。例如，此介電層(730)可包含高k材料。例如，高k介電質可選自包含以下之列表：氧化鉿(HfO 2)、氧化鉭(Ta 2O 5)、氧化釩(VO 2)、氧化鈮(Nb 2O 5)、氧化鋯(ZrO 2)、氧化鈦(TiO 2)、氧化鋁(Al 2O 3)、氧化鑭(La 2O 3)、及其等之混合物/積層物。其他例示性高k介電質包括矽酸鹽，諸如矽酸鉿(HfSiO x)、矽酸鑭(LaSiO x)、矽酸鈦(TiSiO x)、及矽酸銩(TmSiO x)等等。在VNAND記憶體架構的合適組態中，另一介電層(750)可充當穿隧層，並可相鄰於（例如經摻雜的多晶矽）通道層（未示出）。
圖8繪示依據本揭露之實例之另一結構(800)。結構(800)適於環繞式閘極場效電晶體(GAA FET)（亦稱為側向奈米線FET）裝置及類似者。
在所繪示之實例中，結構(800)包括半導體材料(802)、介電材料(804)、藉由如本文中所描述的方法所形成之層(806)、及傳導層(808)。結構(800)可上覆一基材地形成。藉由如本文中所描述的方法所形成的層(806)可定位在傳導層(808)與介電材料(806)之間，如所示。替代地，藉由如本文中所描述的方法所形成的層(806)可定位在傳導層(808)內部（實施例未示）。
半導體材料(802)可包括任何合適半導電材料。例如，半導體材料(802)可包括IV族、III-V族、或II-VI族半導體材料。舉實例而言，半導體材料(802)可包括矽。
介電材料(804)可與本文中其他地方所描述的介電層（例如，高k介電質）相同或類似。
在顯示如本文中所描述方法之可行性之闡釋性實驗中，金屬氮化物係在使基材經受氮電漿達30 s之後，藉由如本文中所描述之循環沉積製程來沉積。當使基材經受氮電漿時，電漿氣體由Ar、N 2、及He所組成，將基材維持在300 °C的溫度，且將反應室維持在5托的壓力。特定言之，在使基材經受氮電漿的同時，將1.8 slm Ar、0.8 slm N 2、及0.2 slm He提供至反應室。在兩個相異的實驗中，使用150 W及300 W之電漿功率。然後使用由68個交替鈦前驅物及氮反應物暴露的子循環所組成之循環沉積製程將氮化鈦沉積於基材上。使用TiCl 4作為鈦前驅物，且使用NH 3作為氮反應物。20.5 Å的TiN係生長在不暴露至氮電漿之參考樣品上。19.2 Å的TiN係在暴露至150 W的氮電漿之樣品上生長，且19.9 Å的TiN係在暴露至300 W的氮電漿之樣品上生長。因此，TiN生長可藉由含N 2電漿有效地抑制。在本發明不受限於任何特定理論或操作模式的情況下，咸信本文揭示的方法允許以由下而上方式填充間隙，因為在包含此一間隙特徵的基材經受含氮電漿（諸如其中電漿氣體包含N 2的電漿）時，間隙特徵的近端表面較間隙特徵的遠端表面更受抑制。
本文中所描述之實例實施例並未限制本發明之範疇，由於此等實施例僅為本發明之實施例的實例，本發明之範疇係由文後申請專利範圍及其法定等同項所界定。任何等效實施例意欲落於本發明之範疇內。實際上，除本文所示及所描述者外，在所屬技術領域中具有通常知識者當可從本說明書明白本揭露的各種修改，諸如所描述元件的替代可用組合。此類修改及實施例亦意欲落在文後申請專利範圍的範疇內。
在本揭露中，在條件及/或結構未指定之情況下，所屬技術領域中具有通常知識者鑒於本揭露可輕易地提出此類屬於常規實驗事項之條件及/或結構。
2:平板電極 3:反應室 4:平板電極/噴淋板 5:轉移室 6:轉移室之排氣管線 7:反應室之排氣管線 11:反應室之內部 12:側 13:圓管 14:分隔板 16:轉移室之內部 21,22:氣體管線 24:氣體密封管線 25:功率源 200:基材 210:間隙特徵 211:近端部分 212:遠端部分 311,316,414:步驟 312:電漿處理 315,317,413,415:沖洗 318,416:方法結束 319,417:重複 411:開始 412:基材暴露至金屬前驅物 500:結構/裝置 502:基材 504,804:介電材料 506:層 508:界面層 510:主體層 514:源極區域 516:汲極區域 518:通道區域 600:DRAM電容器 610,670:頂部電極 620,630,650,660,730,750:介電層 640:底部電極 680:DRAM電容器/介電質 700:總成 710:金屬層 720:襯體 740:電荷捕捉層 800:結構 802:半導體材料 806:層 808:傳導層
當連同下列闡釋性圖式而考慮時，可藉由參照實施方式及申請專利範圍而衍生對本揭露之實施例之更完整理解。 圖1係經配置用於進行依據本揭露之至少一實施例的方法之半導體處理設備的示意性表示。 圖2顯示包含間隙特徵(210)之基材(200)的示意性表示。 圖3顯示如本文中所描述之方法的實施例之示意性表示。 圖4顯示一方法的部分之實施例的示意性表示，方法用於在基材中所包含的間隙特徵之遠端表面上選擇性地沉積金屬氮化物。 圖5繪示依據本揭露之實例之例示性結構(500)。 圖6繪示例示性DRAM電容器(600)。 圖7繪示VNAND單元的一部分，即接觸件及電荷捕捉總成(700)。 圖8繪示依據本揭露之實例之另一結構(800)。 應瞭解，圖式中的元件是為了簡單與清楚而繪示，且不必然按比例繪製。舉例而言，圖式中之一些元件的尺寸可能相對於其他元件而特別放大，以幫助改善對所繪示本揭露實施例的理解。
311,316:步驟
312:電漿處理
315,317:沖洗
318:方法結束
319:重複

Claims (20)

  1. 一種用於填充一間隙特徵之方法，該方法依給定順序包含： 在一反應室中將一基材定位在一基材支撐件上的一步驟，該基材包含一基材表面，該基材表面包含一或多個間隙特徵，該一或多個間隙特徵包含一近端部分及一遠端部分，該近端部分包含一近端表面且該遠端部分包含一遠端表面； 使該基材經受一電漿處理之一步驟，藉此相對於該遠端表面選擇性地抑制該近端表面；及， 在該遠端表面上選擇性地沉積一金屬氮化物之一步驟。
  2. 如請求項1之方法，其中執行複數個超循環，一超循環包含使該基材經受該電漿處理之該步驟，及在該遠端表面上選擇性地沉積該金屬氮化物之該步驟。
  3. 如請求項1或2之方法，其中在該電漿處理之前的一電漿預處理包含使該基材暴露至一氮電漿。
  4. 如請求項1至3中任一項之方法，其中在該遠端表面上選擇性地沉積該金屬氮化物的該步驟包含一循環製程，該循環製程包含複數個子循環，一子循環依給定順序包含： 使該基材暴露至一金屬前驅物的一步驟，藉此在該遠端表面上形成一化學吸附金屬前驅物；及， 使該基材暴露至一氮反應物的一步驟； 藉此允許該氮反應物與該化學吸附金屬前驅物起反應，因此在該遠端表面上形成該金屬氮化物。
  5. 如請求項4之方法，其中使該基材暴露至該金屬前驅物之該步驟及使該基材暴露至該氮反應物之該步驟係由一子循環內沖洗來分開。
  6. 如請求項4或5之方法，其中後續子循環係由一子循環間沖洗來分開。
  7. 如請求項4至6中任一項之方法，其中該金屬包含一過渡金屬。
  8. 如請求項5之方法，其中該過渡金屬包含鈦。
  9. 如請求項4至8中任一項之方法，其中該金屬前驅物包含一或多個烷基胺配位子。
  10. 如請求項4至9中任一項之方法，其中該金屬前驅物具有M(NR 2) n之一通式，其中M係一金屬，R係一直鏈或支鏈C1至C4烷基，且係從至少2到至多5之一整數。
  11. 如請求項10之方法，其中R係甲基。
  12. 如請求項10或11之方法，其中n係4。
  13. 如請求項4至8中任一項之方法，其中該金屬前驅物包含一金屬鹵化物。
  14. 如請求項13之方法，其中該金屬鹵化物包含一氯化物。
  15. 如請求項14之方法，其中該金屬鹵化物包含TiCl 4。
  16. 如請求項4至15中任一項之方法，其中該氮反應物包含NH 3。
  17. 如請求項1至16中任一項之方法，其中該基材維持在至少50 ⁰C到至多300 ⁰C之一溫度。
  18. 如請求項1至17中任一項之方法，其中在該遠端表面上選擇性地沉積一材料之該步驟係以每子循環至少0.01 Å至每子循環至多1.0 Å之一生長速率完成。
  19. 如請求項1至18中任一項之方法，其中使該基材經受該電漿處理之該步驟及在該遠端表面上選擇性地沉積該金屬氮化物之該步驟係由一電漿後沖洗來分開。
  20. 一種半導體處理設備，其包含： 一反應室，其包含一基材支撐件，用於支撐一包含一或多個間隙特徵的一基材； 一加熱器，其經建構且配置以在該反應室中加熱該基材； 一電漿氣體源，其經由一電漿閥與該反應室流體連通； 一電漿模組，其包含一射頻功率源，該射頻功率源經建構且配置以在該反應室中生成一電漿； 一金屬前驅物源，其經由一或多個金屬前驅物閥與該反應室流體連接； 一氮反應物源，其經由一或多個氮反應物閥與該反應室流體連接；及， 一控制器，其經組態用於致使該半導體處理設備進行如請求項1至19中任一項之一方法。
TW111111215A 2021-04-02 2022-03-25 用於填充間隙之方法以及相關半導體處理設備 TW202246575A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US202163170127P 2021-04-02 2021-04-02
US63/170,127 2021-04-02

Publications (1)

Publication Number Publication Date
TW202246575A true TW202246575A (zh) 2022-12-01

Family

ID=83448273

Family Applications (1)

Application Number Title Priority Date Filing Date
TW111111215A TW202246575A (zh) 2021-04-02 2022-03-25 用於填充間隙之方法以及相關半導體處理設備

Country Status (4)

Country Link
US (1) US20220319855A1 (zh)
KR (1) KR20220137547A (zh)
CN (1) CN115206760A (zh)
TW (1) TW202246575A (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220344355A1 (en) * 2021-04-23 2022-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-gate device gate structure and methods thereof
US20220389580A1 (en) * 2021-06-08 2022-12-08 Applied Materials, Inc. Non-conformal plasma induced ald gapfill

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9425078B2 (en) * 2014-02-26 2016-08-23 Lam Research Corporation Inhibitor plasma mediated atomic layer deposition for seamless feature fill
US9564312B2 (en) * 2014-11-24 2017-02-07 Lam Research Corporation Selective inhibition in atomic layer deposition of silicon-containing films
US10727046B2 (en) * 2018-07-06 2020-07-28 Lam Research Corporation Surface modified depth controlled deposition for plasma based deposition
US11316023B2 (en) * 2020-06-15 2022-04-26 Taiwan Semiconductor Manufacturing Co., Ltd. Dumbbell shaped self-aligned capping layer over source/drain contacts and method thereof

Also Published As

Publication number Publication date
KR20220137547A (ko) 2022-10-12
US20220319855A1 (en) 2022-10-06
CN115206760A (zh) 2022-10-18

Similar Documents

Publication Publication Date Title
US7795160B2 (en) ALD of metal silicate films
US7972977B2 (en) ALD of metal silicate films
KR102271202B1 (ko) 심리스 코발트 갭-충전을 가능하게 하는 방법
KR20190024834A (ko) 기판 표면 상의 갭 피처를 충진하는 방법 및 이와 관련된 반도체 소자 구조
US20140264555A1 (en) Silicon on germanium
US7928006B2 (en) Structure for a semiconductor device and a method of manufacturing the same
US20100151676A1 (en) Densification process for titanium nitride layer for submicron applications
TW202246575A (zh) 用於填充間隙之方法以及相關半導體處理設備
KR20230110582A (ko) 금속 게이트 스택에서의 금속 충전을 위한 방법들 및 장치
TWI540642B (zh) 形成含氮氧化物層及含氮高介電常數層的方法
US20210335615A1 (en) Methods and systems for depositing a layer comprising vanadium, nitrogen, and a further element
KR20220081905A (ko) 실리콘 질화물 증착용 실리콘 전구체
TW202235649A (zh) 填充間隙之方法與相關之系統及裝置
TWI515803B (zh) 矽化鉭內的摻雜鋁
US20220285146A1 (en) Methods and systems for forming a layer comprising vanadium and nitrogen
WO2024163232A1 (en) Methods of forming interconnect structures