CN105762068A - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

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CN105762068A
CN105762068A CN201410799048.3A CN201410799048A CN105762068A CN 105762068 A CN105762068 A CN 105762068A CN 201410799048 A CN201410799048 A CN 201410799048A CN 105762068 A CN105762068 A CN 105762068A
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epitaxial layer
layer
metal silicide
stannum
substrate
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王蓝翔
廖鸿
蒋超
廖端泉
李叶超
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United Microelectronics Corp
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Abstract

本发明公开一种半导体元件及其制作方法。首先提供一基底，该基底上设有一栅极结构，然后形成一第一外延层、一第二外延层以及一硅化金属层于邻近该栅极结构的该基底中，其中该第一外延层、该第二外延层及该硅化金属层包含硅锗锡的合金。

Description

半导体元件及其制作方法
技术领域
本发明涉及一种制作半导体元件的方法，尤其是涉及一种于基底中形成具有硅锗锡合金的外延层的方法。
背景技术
为了能增加半导体结构的载流子迁移率，可以选择对于栅极通道施加压缩应力或是伸张应力。举例来说，若需要施加的是压缩应力，现有技术常利用选择性外延成长(selectiveepitaxialgrowth,SEG)技术于一硅基底内形成晶格排列与该硅基底相同的外延结构，例如硅锗(silicongermanium,SiGe)外延结构。利用硅锗外延结构的晶格常数(latticeconstant)大于该硅基底晶格的特点，对P型金属氧化物半导体晶体管的通道区产生应力，增加通道区的载流子迁移率(carriermobility)，并用于增加金属氧化物半导体晶体管的速度。反之，若是N型半导体晶体管则可选择于硅基底内形成硅碳(siliconcarbide,SiC)外延结构，对栅极通道区产生伸张应力。
前述方法虽然可于某种程度下提升通道区的载流子迁移率，却无法在半导体元件尺寸持续缩小的趋势下更加有效地提升元件的应变(strain)，降低源极/漏极区域的电阻值，以及达到满意的驱动电流(drivingcurrent)。因此，如何改良现有制作工艺技术以解决现有瓶颈即为现今一重要课题。
发明内容
为解决上述问题，本发明优选实施例公开一种制作半导体元件的方法。首先提供一基底，该基底上设有一栅极结构，然后形成一第一外延层、一第二外延层以及一硅化金属层于邻近该栅极结构的该基底中，其中该第一外延层、该第二外延层及该硅化金属层包含硅锗锡的合金。
本发明另一实施例公开一种半导体元件，包含：一基底；一栅极结构设于基底上；一第一外延层设于邻近栅极结构的基底中；一第二外延层设于第一外延层上；以及一硅化金属层设于第二外延层上，其中第一外延层、第二外延层及硅化金属层包含硅锗锡的合金。
附图说明
图1至图4为本发明优选实施例制作一半导体元件的示意图。
主要元件符号说明
12基底14栅极结构
16栅极介电层18栅极材料层
20硬掩模22偏位间隙壁
24轻掺杂漏极26凹槽
28第一外延层30第二外延层
32第三外延层34硅化金属层
具体实施方式
请参照图1至图4，图1至图4为本发明优选实施例制作一半导体元件的示意图。如图1所示，首先提供一基底12，然后于基底上形成至少一栅极结构14。在本实施例中，形成栅极结构14的方式优选依序形成一栅极介电层、一栅极材料层以及一硬掩模于基底12上，并利用一图案化光致抗蚀剂(图未示)当作掩模进行一图案转移制作工艺，以单次蚀刻或逐次蚀刻步骤，去除部分的硬掩模、栅极材料层与栅极介质层，然后剥除图案化光致抗蚀剂，以于基底12上形成至少一由图案化的栅极介电层16、图案化的栅极材料层18以及图案化的硬掩模20所构成的栅极结构14。在本实施例中，栅极结构14的数量虽以单颗为例，但不局限于此，
在一实施例中，基底12例如是硅基底、外延硅基底、碳化硅基底或硅覆绝缘(silicon-on-insulator,SOI)基底等的半导体基底，但不以此为限。栅极介电层16可包含二氧化硅(SiO2)、氮化硅(SiN)或高介电常数(highdielectricconstant,high-k)材料；栅极材料层18可包含金属材料、多晶硅或金属硅化物(silicide)等导电材料；硬掩模20则包含二氧化硅、氮化硅、碳化硅(SiC)或氮氧化硅(SiON)等，但不以此为限。另外，在一实施例中，硬掩模20可进一步包含一第一硬掩模及第二硬掩模，其可分别包含氧化硅及氮化硅，此变化型也属本发明所涵盖的范围。
此外，在一实施例中，还可选择预先在基底12中形成多个掺杂阱(未绘示)或多个作为电性隔离之用的浅沟槽隔离(shallowtrenchisolation,STI)。并且，本实施例虽以平面型晶体管为例，但在其他变化实施例中，本发明的半导体制作工艺也可应用于非平面晶体管，例如是鳍状晶体管(Fin-FET)，此时，图1所标示的元件12即相对应代表为形成于一基底上的鳍状结构。
然后分别在栅极结构14侧壁形成一间隙壁，例如偏位间隙壁22，并选择性进行一轻掺杂离子注入，利用约930℃温度进行一快速升温退火制作工艺活化注入基底12的掺杂，以于偏位间隙壁两侧的基底12中分别形成一轻掺杂漏极24。
随后如图2所示，进行一干蚀刻及/或湿蚀刻制作工艺，利用栅极结构14与偏位间隙壁22作为蚀刻掩模，以沿着偏位间隙壁22向下单次或多次蚀刻基底12，而于栅极结构14两侧的基底12中分别形成一凹槽26。
如图3所示，接着可进行一选择性外延成长制作工艺，先形成一第一外延层28于凹槽26内，然后再依序形成一第二外延层30于第一外延层28上以及一第三外延层32于第二外延层30上。在本实施例中，第一外延层28、第二外延层30及第三外延层32优选包含硅锗锡(SiGeSn)的合金或化合物，其中第二外延层30中锗与锡的含量优选高于第一外延层28与第三外延层32中锗与锡的含量。更具体而言，第一外延层28中锗与锡的含量优选介于15至30原子百分比(atomicpercentage)，第二外延层30中锗与锡的含量介于50至80原子百分比，第三外延层32中锗与锡的含量则介于15至30原子百分比。
需注意的是，本实施例是以制作P通道金属氧化物半导体(PMOS)为例来做说明，因此第一外延层28、第二外延层30及第三外延层32优选包含硅锗(SiGe)所构成的外延结构，但不限于此。此外，本实施例又可于形成第一外延层28、第二外延层30或第三外延层32时进行一同步(in-situ)P型掺杂注入制作工艺，形成包含P型掺杂的硅锗外延结构，以直接作为源极/漏极区域并由此可选择性省略之前或后续源极/漏极的离子注入步骤。另外在其他实施例中，前述的外延成长制作工艺可以选择用单层或多层的方式来形成，并且锗和/或P型掺杂的浓度梯度可以以选择往上渐增等的方式形成，但不以此为限。
然后如图4，进行一硅化金属制作工艺，例如可先覆盖一由钴(Co)、钛(Ti)、镍(Ni)等金属所构成的金属层(图未示)于第三外延层32表面，然后利用高温使金属层与第三外延层32反应而转换为一硅化金属层34。依据本发明的优选实施例，硅化金属制作工艺优选将第三外延层32完全消耗殆尽并在不影响下面第二外延层30及第一外延层28的情况下将第三外延层32完全转化为硅化金属层34。换句话说，硅化金属制作工艺完成后栅极结构14两侧的基底12中优选设有一第一外延层28、一第二外延层30设于第一外延层28上以及一硅化金属层34设于第二外延层30上，其中第一外延层28、第二外延层30及硅化金属层34均包含硅锗锡的合金，且第二外延层30中锗与锡的含量优选高于第一外延层28与硅化金属层34中锗与锡的含量。更具体而言，第一外延层28与第二外延层30优选包含硅锗锡的合金，硅化金属层34在使用镍金属进行前述硅化金属层的情况下优选包含镍硅锗锡(Ni(SiGeSn))的合金，且第一外延层28中锗与锡的含量优选介于15至30原子百分比(atomicpercentage)，第二外延层30中锗与锡的含量介于50至80原子百分比，硅化金属层34中锗与锡的含量则介于15至30原子百分比。至此即完成本发明优选实施例制作一半导体元件的方法。
需注意的是，除了上述实施例将第三外延层32完全转化为硅化金属层34，本发明另一实施例也可选择仅将第三外延层32部分转化为硅化金属层34，如此栅极结构14两侧的基底12中优选设有一第一外延层28、一第二外延层30设于第一外延层28上以及一第三外延层32与硅化金属层34同时设于第二外延层30上，其中第一外延层28、第二外延层30、第三外延层32及硅化金属层34均包含硅锗锡的合金，且第二外延层30中锗与锡的含量优选高于第一外延层28与硅化金属层34中锗与锡的含量。
之后可选择性进行后续晶体管制作工艺，例如可于各栅极结构14侧壁形成一主间隙壁，然后于主间隙壁两侧的基底12中形成一源极/漏极区域。接着可依据制作工艺需求形成硅化金属、接触洞蚀刻停止层、层间介电层等一般标准晶体管制作工艺中的元件，甚至可再进行一金属栅极置换(replacementmetalgate)制作工艺，将栅极结构14转换为一金属栅极。由于该些制作工艺均属本领域者所熟知技术，在此不另加赘述。
此外，除了前述实施例直接将第三外延层32完全反应为硅化金属层34，本发明也可先覆盖层间介电层于栅极结构14及第三外延层32上，然后于层间介电层中形成接触洞后填入金属并形成硅化金属层于接触洞内。在此情况下，硅化金属层将仅形成于部分第三外延层32表面，此实施例也属本发明所涵盖的范围。
综上所述，本发明优选于栅极结构两侧的基底中形成凹槽后依序形成一第一外延层、一第二外延层以及一第三外延层，然后再通过硅化金属制作工艺将第三外延层完全反应转换为一硅化金属层，以于栅极结构两侧形成硅化金属层与两层外延层的堆迭结构。依据本发明的优选实施例，所形成的硅化金属层与两层外延层中均包含硅锗锡的合金，其中合金中的锡原子相较于一般硅锗层中的硅及锗具有较高的晶格常数(latticeconstant)与较低的能带隙(bandgap)。一般而言，晶格常数的增加可提升晶体管元件中施加至通道区的应变(strain)，而能带隙的降低则可同时降低源极/漏极区域的电阻值，进而提升元件的驱动电流(drivecurrent)。整体而言，通过三层具有硅锗锡合金的整合结构，本发明可利用底层的第一外延层来降低外延层与基底之间可能产生的缺陷(defect)，利用中间的第二外延层来提升通道区的应变并同时降低源极/漏极区域的阻值，然后利用顶部的第三外延层来提升一般硅化金属制作工艺中的热稳定性(thermalstability)并同时形成硅化金属层。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (13)

1.一种制作半导体元件的方法，包含：
提供一基底，该基底上设有一栅极结构；以及
形成一第一外延层、一第二外延层以及一硅化金属层于邻近该栅极结构的该基底中，其中该第一外延层、该第二外延层及该硅化金属层包含硅锗锡的合金。
2.如权利要求1所述的方法，还包含：
形成一间隙壁于该栅极结构旁；
形成一凹槽于邻近该间隙壁的该基底中；
形成该第一外延层于该凹槽内；
形成该第二外延层于该第一外延层上；
形成一第三外延层于该第二外延层上；以及
进行一硅化金属制作工艺将该第三外延层转换为该硅化金属层。
3.如权利要求2所述的方法，还包含于形成该第一外延层、该第二外延层或该第三外延层时进行一同步(in-situ)P型掺杂注入制作工艺。
4.如权利要求1所述的方法，其中该第一外延层中锗与锡的含量介于15至30原子百分比。
5.如权利要求1所述的方法，其中该第二外延层中锗与锡的含量介于50至80原子百分比。
6.如权利要求1所述的方法，其中该第三外延层中锗与锡的含量介于15至30原子百分比。
7.如权利要求1所述的方法，其中该硅化金属层包含镍硅锗锡的合金。
8.一种半导体元件，包含：
基底，其具有一栅极结构设于其上；
第一外延层设于邻近该栅极结构的该基底中；
第二外延层设于该第一外延层上；以及
硅化金属层设于该第二外延层上，其中该第一外延层、该第二外延层及该硅化金属层包含硅锗锡的合金。
9.如权利要求8所述的半导体元件，还包含：
间隙壁设于该栅极结构旁；
该第一外延层设于邻近该间隙壁的该基底中；
该第二外延层设于该第一外延层上；以及
该硅化金属层设于该第二外延层上。
10.如权利要求8所述的半导体元件，其中该第一外延层中锗与锡的含量介于15至30原子百分比。
11.如权利要求8所述的半导体元件，其中该第二外延层中锗与锡的含量介于50至80原子百分比。
12.如权利要求8所述的半导体元件，其中该硅化金属层中锗与锡的含量介于15至30原子百分比。
13.如权利要求8所述的半导体元件，其中该硅化金属层包含镍硅锗锡的合金。
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