CN106033725B - 半导体元件及其制作工艺 - Google Patents

半导体元件及其制作工艺 Download PDF

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CN106033725B
CN106033725B CN201510111039.5A CN201510111039A CN106033725B CN 106033725 B CN106033725 B CN 106033725B CN 201510111039 A CN201510111039 A CN 201510111039A CN 106033725 B CN106033725 B CN 106033725B
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material layer
substrate
layer
nanowire
single crystal
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CN106033725A (zh
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陈信宇
江怀慈
林胜豪
李皞明
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United Microelectronics Corp
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United Microelectronics Corp
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Abstract

本发明公开一种半导体元件及其制作工艺，该半导体元件包含一单晶基底、一源极/漏极结构以及一纳米线结构。该源极/漏极结构设置并接触于该单晶基底。该纳米线结构连接该源极/漏极结构。

Description

半导体元件及其制作工艺
技术领域
本发明涉及一种半导体元件及其制作工艺，特别是涉及一种具有纳米线(nanowire)结构的半导体元件及其制作工艺。
背景技术
当半导体元件发展至65纳米技术世代后，使用传统平面式(planar)的金属氧化物半导体(metal-oxide-semiconductor；MOS)晶体管制作工艺难以持续微缩，因此，现有技术提出以非平面(non-planar)多栅极晶体管元件取代平面晶体管元件的解决途径。举例来说，双栅极(dual-gate)鳍式场效晶体管(fin field effect transistor；FinFET)元件、三栅极(tri-gate)鳍式场效晶体管元件、以及Ω式(omega)鳍式场效晶体管元件等都已被提出。现在，则更发展出利用纳米线(nanowire)结构作为通道的全栅极(gate-all-around；GAA)晶体管元件，作为继续提升元件集成度与元件效能的方案。
发明内容
本发明的目的在于提供一种半导体元件，其具有纳米线结构，而能达到优选的元件效能。
本发明另一目的在于提供一种半导体元件的制作工艺，可简化纳米线结构的制作工艺，并有效控制纳米线结构的尺寸。
本发明的目的在于提供一种半导体元件，其包含一单晶基底、一源极/漏极区以及一纳米线结构。该源极/漏极区设置并接触于该单晶基底。该纳米线结构连接该源极/漏极区。
本发明的另一目的在于提供一种半导体元件的制作工艺，包含下列步骤。首先，在一基底上形成依序堆叠至少一介电层及至少一第一材料层。接着，蚀刻该第一材料层及该介电层，暴露出一部分的该基底。在该部分的该基底上形成一第二材料层。后续，将该第一材料层转型成一单晶材料层。并且，移除该介电层，形成一纳米线结构。
本发明的半导体元件的制作工艺，主要是通过直接形成非晶型态半导体材料层，再利用一再结晶制作工艺将该非晶型态半导体材料层转型为单晶型态半导体材料层，以简化纳米线结构、源极/漏极结构或支撑结构的制作工艺，同时可有效控制纳米线结构的尺寸。因此，利用该制作工艺可有效形成具有环绕纳米线结构通道的一栅极结构，而可构成一全栅极晶体管元件。
附图说明
图1至图9为本发明一优选实施例所提供的半导体元件的制作工艺示意图；
图10为本发明一优选实施例所提供的半导体元件的示意图。
主要元件符号说明
10 纳米线结构场效晶体管
100 基底
101 第一主动区域
102 第二主动区域
105 抗接面击穿注入区
110、111、112、112a、112b 介电层
120、121、122、122a、122b 第一材料层
130、131、132、132a、132b 介电层
140、141、142、142a、142b 第一材料层
151、152 源极/漏极区
153 支撑区
161、162、261、262 源极/漏极结构
163、263 支撑结构
171、172 纳米线区
181、182 纳米线结构
210、211、212 介电层
220、221、222、222a、222b 第一材料层
240、241、242、242a、242b 第一材料层
301、302 栅极结构
311、312 栅极介电层
321、322 栅极
400 绝缘层
STI 第一浅沟槽绝缘
具体实施方式
为使熟悉本发明所属技术领域的一般技术者能更进一步了解本发明，下文特列举本发明的数个优选实施例，并配合所附的附图，详细说明本发明的构成内容及所欲达成的功效。
请参照图1至图9，所绘示者为本发明优选实施例中形成半导体元件的制作工艺示意图。首先，如图1所示，提供一基底100，基底100优选是一单晶基底并可包含一半导体材质，例如是硅(silicon；Si)、外延硅(epitaxial silicon)、硅锗(silicon；SiGe)或碳化硅(silicon carbide；SiC)，但不以此为限。
在一实施例中，可预先在基底100上形成多个第一浅沟槽隔离(shallow trenchisolation)STI，通过第一浅沟槽隔离STI定义出彼此电性绝缘的一第一主动区域101以及一第二主动区域102，如图1所示。其中，本发明的制作工艺可选择在第一主动区域101与第二主动区域102的基底100上同时形成具有相同结构或相同材质的纳米线晶体管，或者是分别形成具有不同结构或不同材质的纳米线晶体管。但并不以此为限，在其他实施例中，也可选择在第一主动区域101与第二主动区域102的基底100上分别形成不同导电型的晶体管(未绘示)，使本发明的制作工艺可用以制作包含纳米线晶体管的互补式金属氧化物半导体。
再如图1所示，在一实施例中，接着于第一主动区域101与第二主动区域102的基底100上分别形成有相互堆叠的至少一介电层110、130及至少一第一材料层120、140，以在第一主动区域101与第二主动区域102的基底100上构成一堆叠结构。其中，位于第一主动区域101的堆叠结构是由介电层111、第一材料层121、介电层131及第一材料层141相互堆叠形成，位于第二主动区域102的堆叠结构则是由介电层112、第一材料层122、介电层132及第一材料层142相互堆叠形成。
具体来说，介电层110、130及第一材料层120、140的形成方式，例如是通过一化学或物理气相沉积(chemical/physical vapor deposition；CVD)法在基底100上依序形成，但不限于此。其中，第一材料层120、140优选具有非晶态的半导体材质，例如是非晶硅(amorphous silicon；α-Si)、非晶锗(amorphous germanium；α-Ge)或是非晶硅锗(amorphous silicon germanium；α-SiGe)等，而锗含量可随制作工艺时间逐渐提升，但以不大于60％为主；介电层110、130则例如是具有二氧化硅(SiO2)、氮化硅(SiN)、氮氧化硅(SiON)或适用的低介电常数(low dielectric constant；low-k)等材质，但不以此为限。此外，在一实施例中，第一主动区域101与第二主动区域102内的各第一材料层121、122、141、142可包含相同或不同的材质，举例来说，第一材料层121与第一材料层141可以都包含非晶硅。或者，第一材料层121可包含非晶硅，而第一材料层141则包含非晶硅锗等不同的材料。而在另一实施例中，介电层110优选具有一双层结构，例如通过一热氧化制作工艺先形成直接接触基底100的第一层(未绘示)，再利用化学气相沉积在该第一层上形成一第二层(未绘示)，由此，使该第一层及第二层因材质致密度或组成的不同而有蚀刻选择比。而介电层130则优选是利用与该第二层相同的方法形成，以具有与该第二层相同的致密度或组成而具有相同的蚀刻速率。
接着，如图2至图3所示，其中，图3为图2沿着切线A-A’获得的剖面示意图，绘示分别图案化堆叠在第一主动区域101的第一材料层141、介电层131、第一材料层121及介电层111；以及堆叠在第二主动区域102的第一材料层142、介电层132、第一材料层122及介电层112，以在第一主动区域101的基底100上形成源极/漏极区151，且在第二主动区域102的基底100上形成源极/漏极区152。前述图案化该堆叠结构的制作工艺例如是包含在第一主动区域101及第二主动区域102分别形成一第一掩模层(未绘示)，覆盖一部分的该堆叠结构，以定义源极/漏极区151、152。接着进行一蚀刻步骤，移除部分堆叠在第一主动区域101外的第一材料层141、介电层131、第一材料层121及介电层111；以及移除部分堆叠在第二主动区域102外的第一材料层142、介电层132、第一材料层122及介电层112，以曝露出位于源极/漏极区151、152的部分基底100及第一浅沟槽隔离STI，如图2所示。其中，该蚀刻步骤例如是一干蚀刻及/或湿蚀刻，但不以此为限。随后即可去除该第一掩模层，并且可选择性进行一清洗制作工艺。
在一实施例中，该些源极/漏极区151、152是形成在该图案化堆叠结构的两侧。此外，在另一实施例中，在定义第二主动区域102的源极/漏极区152时，可进一步形成至少一支撑区153。举例来说，通过该第一掩模层在第二主动区域102定义源极/漏极区152时，同时定义支撑区153，并一并利用该蚀刻步骤移除位于支撑区153的第一材料层142、介电层132、第一材料层122及介电层112，曝露出位于支撑区153的部分基底100，如图2所示。其中，支撑区153优选是位于源极/漏极区152之间，并将位于第二主动区域102的堆叠结构(包含第一材料层142、介电层132、第一材料层122及介电层112)区分为两部分(第一材料层142a、142b；介电层132a、132b；第一材料层122a、122b及介电层112a；112b)，如图3所示。在另一实施例中，可选择在定义该些源极/漏极区151、152时，同时形成多个浅沟槽，也就是说，在形成源极/漏极区151、152时一并定义出电性绝缘的多个浅沟槽隔离区域。
后续，如图4所示，在第一主动区域101的源极/漏极区151形成直接接触部分的基底100的源极/漏极结构161，并且于第二主动区域102的源极/漏极区152形成直接接触部分的基底100的源极/漏极结构162。在一实施例中，源极/漏极结构161、162形成的方式例如可包含直接利用一化学或物理气相沉积在源极/漏极区151、152形成一第二材料层，以作为源极/漏极结构161、162。或者，该方法也可包含利用一选择性外延制作工艺形成源极/漏极结构161、162，例如是一低温外延制作工艺。其中，第二材料层可以包含非晶硅、单晶硅、非晶锗、单晶锗、非晶硅锗或是单晶硅锗等，但不以此为限。值得进一步说明的是，在一实施例中，第一材料层120、140可选择与第二材料层具相同的结晶型态或相同的材质，也可选择与第二材料层具不同的结晶型态或不同的材质。举例来说，第一材料层120、140可包含非晶硅，而第二材料层则可选择也包含非晶硅，或是包含单晶硅。
在一实施例中，可选择在形成曝露源极/漏极区151、152的基底100后，还额外进行一离子掺杂步骤，例如一抗接面击穿注入(anti punch through Implantation；APT)，以掺杂相反导电型态的一离子至源极/漏极区151、152，并在源极/漏极区151、152的基底100中形成一抗接面击穿注入区105，如图4所示。举例来说，若选择在第一主动区域101形成P型晶体管，则掺杂n型离子至抗接面击穿注入区105，以确保后续形成的源极/漏极结构161与基底100的电性隔离作用，避免该源极/漏极结构161的信号会通过基底100传送而影响晶体管的效能。反之，若选择在第一主动区域101形成N型晶体管，则需掺杂p型离子来形成抗接面击穿注入区105。
另外，在另一实施例中，在形成位于第二主动区域102的源极/漏极结构162时，可同时在支撑区153形成一支撑结构163。其中，支撑结构163可与源极/漏极结构162同时形成，也就是说在源极/漏极区151、152及支撑区153一并形成该第二材料层，以使支撑结构163与源极/漏极结构162具有相同的材质。或者，在另一实施例中，也可选择依序形成支撑结构163与源极/漏极结构162，而使两者分别具有不同的材质。此外，在此实施例中，也可选择在掺杂抗接面击穿注入离子至源极/漏极区152的基底100时，同时在支撑区153的基底100形成抗接面击穿注入区105，如图4所示。
后续，如图5至图6所示，其中，图6为图5沿着切线B-B’获得的剖面示意图。首先，再次图案化堆叠在第一主动区域101的第一材料层141、介电层131、第一材料层121及介电层111；以及堆叠在第二主动区域102的第一材料层142、介电层132、第一材料层122及介电层112，以在第一主动区域101及第二主动区域102上分别定义出一纳米线(nanowire)区171、172。前述再次图案化该堆叠结构的制作工艺同样可包含在第一主动区域101及第二主动区域102分别形成一第二掩模层(未绘示)，覆盖另一部分的该堆叠结构，接着进行一蚀刻步骤，移除一部分堆叠在第一主动区域101的第一材料层141、介电层131、第一材料层121及介电层111；以及移除一部分堆叠在第二主动区域102的第一材料层142、介电层132、第一材料层122及介电层112，以保留位于纳米线区171、172内的材料层120、140及介电层110、130，如图5所示。随后即可去除该第二掩模层，并且可选择性进行另一清洗制作工艺。
值得注意的是，该蚀刻步骤，例如是一干蚀刻及/或湿蚀刻，是完全移除位于纳米线区171、172以外的第一材料层140、120及介电层130，但仅部分移除位于纳米线区171、172以外的介电层110，使一定厚度的介电层110仍被保留在纳米线区171、172外的基底100上，以电性隔离基底100与后续形成的栅极结构，如图5所示。在一实施例中，若介电层110具有双层结构，则可选择在该蚀刻步骤中仅移除介电层130与介电层110的该第二层，使该第一层被保留在纳米线区171、172外的基底100上，电性隔离基底100。
值得注意的是，在图案化堆叠第一材料层140、介电层130、第一材料层120及介电层110之前或之后，可进行一再结晶制作工艺。如图5及图6所示，是在图案化之后进行该再结晶制作工艺，使得位于第一主动区域101的半导体材料层(位于纳米线区171)，与位于第二主动区域102内的半导体材料层(位于纳米线区171)转型成单晶型态的晶格结构。也就是说，若前述形成的第一材料层120、140及/或该第二材料层(源极/漏极结构161、162)具有非晶态的半导体材质，则可通过该再结晶制作工艺转型为单晶型态的半导体材质，例如是单晶硅(single crystal silicon；S-Si)、单晶锗(single crystal germanium；S-Ge)或是单晶硅锗(single crystal silicon germanium；S-SiGe)，并形成如图5及图6所示的第一材料层241、242、221、222以及源极/漏极结构261、262。此外，在一实施例中，位于第二主动区域102的支撑结构163若具有非晶态的半导体材质，则可同样通过该再结晶制作工艺转型为单晶型态的半导体材质，形成如图6所示的支撑结构263。
具体来说，在一实施例中，该再结晶制作工艺可选择包含一热制作工艺，例如大体上是加热至500℃至700℃，或者也可选择包含一激光制作工艺，例如利用激光光束照射第一材料层120、140及/或该第二材料层以使其转型。然而，熟悉该项技术人士应知本发明的再结晶制作工艺并不以前述为限，而可另包含其他适合使非晶态半导体材质转型为单晶型态半导体材质的步骤。此外，在另一实施例中，也可选择调整该再结晶制作工艺操作的时序，例如是在源极/漏极结构161、162形成之后，先进行该再结晶制作工艺，而后再于第一主动区域101及第二主动区域102上定义出纳米线区171、172。或者是，选择在形成完整的纳米线结构后再进行该再结晶制作工艺。
之后，如图7所示以一蚀刻制作工艺移除位于纳米线区171、172的介电层130、110，形成主要由两端支撑的纳米线结构181、182。值得注意的是，在一实施例中，在第二主动区域102额外形成的支撑结构263是位于源极/漏极结构262之间，并将纳米线结构182分隔为两部分，因而可具有进一步支撑纳米线结构182的作用，如图7所示。此外，另需注意的是，该蚀刻制作工艺是完全移除位于纳米线区171、172内的介电层130，但仅部分移除位于纳米线区171、172内的介电层110。也就是说，一定厚度的介电层110仍被保留在纳米线区171、172内的基底100上，并位于基底100及纳米线结构181、182之间，而在基底100及纳米线结构181、182之间形成一介电层211、212，如图7所示。至此，第一主动区域101与第二主动区域102的基底100上(除源极/漏极区151、152及支撑区153外)，仍保留有一定厚度的介电层110，如介电层211、212，以电性隔离基底100与后续形成的栅极结构。因此纳米线结构181、182是被悬置于基底100之上，尤其是指基底100的介电层211、212之上，而与基底100电性隔离。此外，在一实施例中，也可选择在该蚀刻步骤中仅移除介电层130及介电层110的该第二层，也就是说保留介电层110的该第一层而形成介电层211、212。
最后，如图8及图9所示，其中，图9为图8沿C-C’及D-D’切线获得的剖面示意图，绘示分别在第一主动区域101及第二主动区域102形成跨越于纳米线结构181、182之上的栅极结构301、302。具体来说，栅极结构301、302的形成方法例如是包含全面性地在纳米线结构181、182及源极/漏极结构261、262表面形成一栅极介电层(未绘示)，形成全面性地覆盖纳米线结构181、182的一栅极层(未绘示)，再图案化该栅极层及该栅极介电层，形成至少部分环绕纳米线结构181、182的栅极321、322，例如大体上环绕纳米线结构181长度的1/5至1/3，以及位于栅极321、322与纳米线结构181、182之间的栅极介电层311、312，如图8所示。在一实施例中，可选择图案化该栅极层，而形成环绕整个纳米线结构181的一栅极(未绘示)，使该栅极的两端可直接接触位于源极/漏极结构261上的栅极介电层(未绘示)。
另一方面，位于第二主动区域102的栅极322则可选择同时覆盖支撑结构263及其两侧的纳米线结构182上，并部分环绕位于支撑结构263两侧的纳米线结构182，例如是环绕纳米线结构182长度的1/5至1/3，如图8所示。需注意的是，位于第二主动区域102的栅极322在平行于支撑结构263延伸的方向上仅部分覆盖支撑结构263，如图9所示。在另一实施例中，也可选择形成环绕整个纳米线结构182的一栅极(未绘示)。也就是说，该栅极是完全覆盖位于支撑结构263两侧的纳米线结构182，使该栅极可直接接触位于源极/漏极结构262上的栅极介电层(未绘示)。后续，则可再进行一掺杂制作工艺，在栅极结构301、302的栅极321、322覆盖处以外的部分分别掺杂相同导电型的离子，以形成合适的源极/漏极掺杂区(未绘示)。
在另一实施例中，栅极介电层311、312例如是包含氧化硅、氮化硅、氮氧化硅或适用的高介电常数材料等介电材质，且其形成方式可包含利用一热氧化制作工艺，以在纳米线结构181、182及源极/漏极结构261、262的外表面形成均匀的栅极介电层311、312，但不以此为限。栅极321、322则可包含多晶硅，或是金属栅极所需的功函数金属层等。此外，在另一实施例中，可选择在形成栅极介电层311、312与栅极321、322之前，先进行一退火(annealing)制作工艺，例如是利用氢(hydrogen；H2)或氧(oxygen；O2)的热制作工艺，圆角化纳米线结构181、182。也就是说，通过该退火制作工艺修正纳米线结构181、182的边角，以形成如图9左所示的圆柱状的截面。在另一实施例中，更可依需要在形成栅极介电层311、312与栅极321、322之前，选择性地进行一修整(trimming)步骤，以进一步控制纳米线结构181、182的直径。
据此，即获得本发明一实施例的半导体元件，其具有环绕纳米线结构通道的一栅极结构，因而可构成一全栅极晶体管元件。此外，本发明半导体元件的制作工艺主要是通过直接形成非晶型态的半导体材料层，再利用一再结晶制作工艺将非晶型态半导体材料层转型为单晶型态半导体材料层，以简化纳米线结构、源极/漏极结构或支撑结构的制作工艺，同时可有效控制纳米线结构的尺寸。
后续则可选择全面性覆盖一绝缘材料层(未绘示)于该半导体元件的基底100以及纳米线结构181、182上，再进行一平坦化步骤以移除多余的该绝缘材料层，以形成绝缘层400。绝缘层400是环绕整个纳米线结构181、182及源极/漏极结构261、262，以做为一第二浅沟槽隔离，使得纳米线结构场效晶体管10是埋设在第一浅沟槽隔离STI及该第二浅沟绝缘(即绝缘层400)中，如图10所示。本发明之后可再搭配一金属栅极置换(replacement metalgate；RMG)制作工艺，上述相关步骤与现有制作晶体管的步骤类似，在此不多加赘述。
请再参照图10，本发明的一优选实施例的纳米线结构场效晶体管10具有单晶基底100；设置并接触于单晶基底100的多个源极/漏极结构261、262；以及分别结构连接该些源极/漏极结构261、262的多个纳米线结构181、182。并且，更进一包含至少环绕一部分的纳米线结构181、182的栅极321、322，以及分别设置在栅极321、322及纳米线结构181、182之间的栅极介电层311、312。值得注意的是，纳米线结构场效晶体管10更具有介电层210(介电层211、212)，介电层210是设置在该单晶基底100上，位于纳米线结构181、182与单晶基底100之间以电性隔离位于纳米线结构181、182上的栅极321、322与单晶基底100。另外，在一实施例中，单晶基底100还包含一抗接面击穿注入区105，该抗接面击穿注入区105位于该源极/漏极结构261、262之下。
并且，在一实施例中，纳米线结构181、182、单晶基底100与该源极/漏极结构261、262可包含不同的材质，优选是具有不同的单晶型态半导体材质，例如是单晶硅、单晶锗或是单晶硅锗；但在其他实施例中纳米线结构181、182、单晶基底100与源极/漏极结构261、262也可包含相同的单晶型态半导体材质。在另一实施例中，纳米线结构场效晶体管10还可以具有一支撑结构263，支撑结构263是设置在部分的纳米线结构182之间并位于单晶基底100上，以进一步支撑纳米线结构182。在另一实施例中，纳米线结构场效晶体管10还可以包含多个设置于基底的浅沟槽隔离STI，是环绕源极/漏极结构261、262设置。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (18)

1.一种半导体元件的制作工艺，其特征在于，包含:
在一基底上形成依序堆叠的至少一介电层及至少一第一材料层，该介电层包括直接接触该基底的第一层和位于该第一层上的第二层；
蚀刻该第一材料层及该介电层，暴露出一部分的该基底；
在该部分的该基底上形成一第二材料层；
将该第一材料层转型成一单晶材料层；以及
移除该介电层的该第二层并保留该第一层，使该单晶材料层形成一纳米线结构，该第一层位于该基底与该纳米线结构之间。
2.依据权利要求1所述的半导体元件的制作工艺，其特征在于，还包含:
图案化该第一材料层，该第一材料层是在转型成该单晶材料层之前进行图案化。
3.依据权利要求1所述的半导体元件的制作工艺，其特征在于，还包含:
图案化该第一材料层，该第一材料层是在转型成该单晶材料层之后进行图案化。
4.依据权利要求1所述的半导体元件的制作工艺，其特征在于，该第一材料层是通过一热制作工艺或一激光制作工艺进行转型。
5.依据权利要求1所述的半导体元件的制作工艺，其特征在于，该第二材料层直接接触该基底。
6.依据权利要求1所述的半导体元件的制作工艺，其特征在于，该部分的基底包含一源极/漏极区或一支撑区。
7.依据权利要求1所述的半导体元件的制作工艺，其特征在于，还包含:
该部分的基底进行一抗接面击穿离子注入制作工艺。
8.依据权利要求1所述的半导体元件的制作工艺，其特征在于，还包含:
形成一栅极，该栅极至少部分环绕该纳米线结构；以及
形成一栅极介电层，该栅极介电层位于该栅极及该纳米线结构之间。
9.依据权利要求8所述的半导体元件的制作工艺，其特征在于，在形成该栅极介电层之前还包含:
进行一退火制作工艺，圆角化该纳米线结构。
10.依据权利要求1所述的半导体元件的制作工艺，其特征在于，该第一材料层及该第二材料层包含不同材质，或者，该第一材料层及该基底包含不同材质。
11.依据权利要求1所述的半导体元件的制作工艺，其特征在于，该第二材料层是通过一低温外延制作工艺而形成。
12.一半导体元件，其特征在于，包含:
单晶基底；
源极/漏极结构，设置并接触于该单晶基底；
纳米线结构，该纳米线结构连接该源极/漏极结构；以及
介电层，设置于该单晶基底的顶面上且与该单晶基底的该顶面直接接触，并在一投影方向上位于该纳米线结构与该单晶基底的该顶面之间。
13.依据权利要求12所述的半导体元件，其特征在于，该单晶基底还包含一抗接面击穿注入区，该抗接面击穿注入区位于该源极/漏极结构之下。
14.依据权利要求12所述的半导体元件，其特征在于，还包含:
栅极，该栅极至少环绕一部分该纳米线结构设置；以及
栅极介电层，该栅极介电层设置在该栅极及该纳米线结构之间。
15.依据权利要求12所述的半导体元件，其特征在于，还包含:
支撑结构，该支撑结构设置在该单晶基底之上，以支撑该纳米线结构。
16.依据权利要求12所述的半导体元件，其特征在于，该纳米线结构与该源极/漏极结构具有不同的材质。
17.依据权利要求12所述的半导体元件，其特征在于，该纳米线结构与单晶基底具有不同的材质。
18.依据权利要求12所述的半导体元件，其特征在于，还包含一浅沟隔离，该浅沟隔离环绕该源极/漏极结构及该纳米线结构。
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