TW201719769A - 鰭式場效電晶體的製作方法 - Google Patents

鰭式場效電晶體的製作方法 Download PDF

Info

Publication number
TW201719769A
TW201719769A TW105137192A TW105137192A TW201719769A TW 201719769 A TW201719769 A TW 201719769A TW 105137192 A TW105137192 A TW 105137192A TW 105137192 A TW105137192 A TW 105137192A TW 201719769 A TW201719769 A TW 201719769A
Authority
TW
Taiwan
Prior art keywords
dielectric layer
gate strip
semiconductor
exposed
gate
Prior art date
Application number
TW105137192A
Other languages
English (en)
Other versions
TWI682467B (zh
Inventor
張哲誠
林志翰
曾鴻輝
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW201719769A publication Critical patent/TW201719769A/zh
Application granted granted Critical
Publication of TWI682467B publication Critical patent/TWI682467B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L2029/7858—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1211—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

一種鰭式場效電晶體的製作方法，包括：圖案化基板以形成多個溝渠以及位於溝渠之間的半導體鰭片。於溝渠內形成多個絕緣體，並且形成第一介電層以覆蓋半導體鰭片與絕緣體。於第一介電層上形成擬閘極條。於擬閘極條的側壁上形成多個間隙物擬閘極條。移除擬閘極條與位於其下方的第一介電層直到間隙物的側壁、半導體鰭片的部分以及絕緣體的部分被暴露出來。形成第二介電層以選擇性地覆蓋半導體鰭片被暴露出來的部分，其中第一介電層的厚度小於第二介電層的厚度。於間隙物之間形成閘極以覆蓋第二介電層、間隙物的側壁以及絕緣體被暴露出的部分。

Description

鰭式場效電晶體的製作方法
本發明是有關於一種鰭式場效電晶體。
由於半導體元件的尺寸不斷縮小，三維多閘極結構，例如鰭式場效電晶體（FinFET）已被開發，以取代平面互補金屬氧化物半導體（CMOS）元件。鰭式場效電晶體的結構特徵為矽基鰭片（silicon based fin）從基板的表面垂直延伸，並且閘極會圍繞由鰭片所形成的導電通道，以對通道進一步提供更好的電氣控制。
以具有短通道（即通道長度小於50奈米）的鰭式場效應晶體的閘極替換製程為例，覆蓋矽基鰭片的部分氧化物層需要被過度蝕刻，以使得後續的高介電常數介電層和閘極的沈積具有更好的製程裕度(process window)。然而，氧化物層的高蝕刻量會導致金屬閘極的漏電路徑和擠出路徑產生。
一種鰭式場效電晶體的製作方法，包括：圖案化基板以形成多個位於基板內的溝渠以及位於溝渠之間的半導體鰭片；於溝渠內形成多個絕緣體；形成第一介電層以覆蓋半導體鰭片與絕緣體；於第一介電層上形成擬閘極條，擬閘極條的長度方向不同於半導體鰭片的長度方向；於擬閘極條的多個側壁上形成一對間隙物；移除擬閘極條與位於其下方的第一介電層直到間隙物的多個側壁、半導體鰭片的一部分以及絕緣體的多個部分被暴露出來；形成第二介電層以選擇性地覆蓋半導體鰭片被暴露出來的部分，其中第一介電層的厚度小於第二介電層的厚度；以及於間隙物之間形成閘極以覆蓋第二介電層、間隙物被暴露出的側壁以及絕緣體被暴露出來的部分。
以下揭露內容提供用於實施所提供的標的之不同特徵的許多不同實施例或實例。以下所描述的構件及配置的具體實例是為了以簡化的方式傳達本發明為目的。當然，這些僅僅為實例而非用以限制。舉例來說，於以下描述中，在第一特徵上方或在第一特徵上形成第二特徵可包括第二特徵與第一特徵形成為直接接觸的實施例，且亦可包括第二特徵與第一特徵之間可形成有額外特徵使得第二特徵與第一特徵可不直接接觸的實施例。此外，本發明在各種實例中可使用相同的元件符號及/或字母來指代相同或類似的部件。元件符號的重複使用是為了簡單及清楚起見，且並不表示所欲討論的各個實施例及/或配置本身之間的關係。
另外，為了易於描述附圖中所繪示的一個構件或特徵與另一組件或特徵的關係，本文中可使用例如「在…下」、「在…下方」、「下部」、「在…上」、「在…上方」、「上部」及類似術語的空間相對術語。除了附圖中所繪示的定向之外，所述空間相對術語意欲涵蓋元件在使用或操作時的不同定向。設備可被另外定向（旋轉90度或在其他定向），而本文所用的空間相對術語相應地作出解釋。
本發明的實施例中所揭露的半導體元件的製作方法，而前述的半導體元件包括至少一個長通道的鰭式場效電晶體以及至少一個短通道的鰭式場效電晶體。在本發明的某些實施例中，半導體元件可形成塊狀矽基板（bulk silicon substrates）上。當然，半導體元件亦可以選擇地形成在絕緣體上矽（silicon-on-insulator，SOI）基板或絕緣體上鍺（germanium-on-insulator，GOI）基板上。此外，根據實施例，矽基板可以包括其它導電層或其它半導體元件，例如電晶體、二極管或類似物。上述的實施例並不限於此。
請參考圖1，其依據本發明的一些實施例繪示出一種半導體元件的製作方法的流程圖。所述的製作方法至少包括步驟S10、步驟S12、步驟S14、步驟S16、步驟S18、步驟S20、步驟S22、步驟S24以及步驟S26。首先，在步驟S10中，提供一基板，接著，圖案化基板以形成多個溝渠以及多個位於溝渠之間的半導體鰭片。在步驟S12中，於溝渠內形成多個絕緣體。前述的絕緣體例如是用以絕緣半導體鰭片的淺溝渠隔離(shallow trench isolation，STI)結構。在步驟S14中，形成一第一介電層以覆蓋半導體鰭片以及絕緣體。在步驟S16中，於第一介電層上形成至少一第一擬閘極條與至少一第二擬閘極條，其中第一擬閘極條的長度方向與第二擬閘極條的長度方向不同，而第一擬閘極條的寬度小於第二擬閘極條的寬度。第一擬閘極條與第二擬閘極條為導電條，例如是多晶矽條。在步驟S18中，於第一擬閘極條與第二擬閘極條上分別形成一對第一間隙物與一對第二間隙物。在步驟S20中，移除第一擬閘極條而形成一第一凹槽。在步驟S22中，移除第二擬閘極條與位於其下方的第一介電層直到暴露出第二間隙物的側壁、半導體鰭片的部分以及絕緣體的部份而形成一第二凹槽。在步驟S24中，於第二凹槽內形成一第二介電層，以選擇性地覆蓋半導體鰭片被暴露出來的部分，其中第一介電層的厚度小於第二介電層的厚度。前述的第二介電層例如是透過原子層沉積（ALD）、化學氣相沉積（CVD）或物理氣相沉積（PVD）所形成。在步驟S26中，於第一凹槽內形成一第一閘極以及於第二凹槽內形成一第二閘極，以覆蓋第二介電層、第二間隙物被暴露出來的側壁以及絕緣體被暴露出來的部分。如圖1所示，第一擬閘極條的移除是在第二擬閘極條的移除之前進行。然而，移除第一擬閘極條與第二擬閘極條的順序並不限於此。
圖2A繪示為半導體元件於製作方法的不同階段中的一個階段的透視圖。在圖1的步驟S10與圖2A中，提供一基板200。於一實施例中，基板200包括一結晶矽基板(如晶圓)。基板200可依據設計需求而包括多種摻雜區(例如是p型基板或n型基板)。於其他實施例中，摻雜區可摻雜有p型與/或n型摻質。舉例來說，摻雜區可摻雜有p型摻質，例如是硼或二氟化硼（BF2）；而n型摻質，例如是磷、砷、與/或上述的組合。摻雜區可以被配置為n型的鰭式場效電晶體、p型鰭式場效電晶體或上述的組合。於其他實施例中，基板200可以由一些其它適合的元素半導體，如鑽石或鍺；適合的化合物半導體，如砷化鎵、碳化矽、砷化銦或磷化銦；或者適合的合金半導體，如碳化矽鍺 (silicon germanium carbide，SiGeC)、磷化砷鎵(gallium arsenic phosphide)或磷化銦鎵(gallium indium phosphide)所組成。
於一實施例中，於基板200上依序形成一接墊層202a與一遮罩層202b。接墊層202a例如是透過熱氧化製程所形成的一氧化矽薄膜。接墊層202可以作為基板200與遮罩層202b之間的黏著層。接墊層202a可以作為蝕刻遮罩層202b的蝕刻終止層。於至少一實施例中，遮罩層202b為一氮化矽層，其是通過低壓化學氣相沉積（PECVD）或電漿增強化學氣相沉積（PECVD）所形成。遮罩層202b於後續的微影製程中被用以作為一硬遮罩(hard mask)。接著，於遮罩層202b上形成具有一預定圖案的一圖案化光阻層204。
圖2B繪示為半導體元件於製作方法的不同階段中的一個階段的透視圖。在圖1的步驟S10以及圖2A至圖2B中，遮罩層202b與接墊層202a沒有被圖案化光阻層204所覆蓋的地方依序被蝕刻，而形成一圖案化遮罩層202b'以及一圖案化接墊層202a'，進而暴露出下面的基板200。以圖案化遮罩層202b'、圖案化接墊層202a'以及圖案化光阻層204為遮罩，基板200的部分被暴露出來且被蝕刻而形成多個溝渠206與多個半導體鰭片208。於基板200被圖案化之後，圖案化遮罩層202b'、圖案化接墊層202a'以及圖案化光阻層204覆蓋住半導體鰭片208。兩相鄰的溝渠206是透過一間隙S而隔開。舉例來說，位於溝渠206之間的間隙S可小於約30奈米。換言之，兩相鄰的溝渠206是由一對應的半導體鰭片208而隔開。
半導體鰭片208的高度與溝渠206的深度介於約5奈米至約500奈米之間。於形成溝渠206與半導體鰭片208之後，移除圖案化光阻層204。於一實施例中，可進行一清潔製程以移除半導體基板200a和半導體鰭片208的原生氧化物。清潔過程可以用氫氟酸稀釋溶液或其它適當的清洗液來進行。
圖2C繪示為半導體元件於製作方法的不同階段中的一個階段的透視圖。在圖1的步驟S12與圖2B至圖2C中，形成一絕緣材料210於基板200a上以覆蓋半導體鰭片208並且填滿溝渠206。除了半導體鰭片208，絕緣材料210更覆蓋圖案化接墊層202a'與圖案化遮罩層202b'。絕緣材料210可包括氧化矽、氮化矽、氧氮化矽、旋塗介電材料或低介電常數的介電材料。絕緣材料210可透過高密度電漿化學氣相沈積（HDP-CVD）、亞大氣壓化學氣相沈積（ASCVD）或旋轉塗佈來形成。
圖2D繪示為半導體元件於製作方法的不同階段中的一個階段的透視圖。在圖1的步驟S12中與圖2C至圖2D中，舉例而言，進行一化學機械研磨製程以移除絕緣材料210的一部分、圖案化遮罩層202b'和圖案化的接墊層202a'直到半導體鰭片208被暴露出來。如圖2D所示，於研磨絕緣材料210之後，研磨後的絕緣材料210的頂表面實質上與半導體鰭片208的頂表面T2共平面。
圖2E繪示為半導體元件於製作方法的不同階段中的一個階段的透視圖。在圖1的步驟S12中與圖2D至圖2E中，透過一蝕刻製程移除部分填充於溝渠206內已被研磨的絕緣材料210，以於基板200a上形成多個絕緣體210a，而半導體鰭片208位於兩相鄰的絕緣體210a之間。於一實施例中，蝕刻製程可以是採用氫氟酸（HF）的濕法蝕刻製程或者是乾式蝕刻製程。絕緣體210a的上表面T1低於半導體鰭片208的頂表面T2。換言之，半導體鰭片208突出於絕緣體210a的上表面T1，且半導體鰭片208的側壁SW因而暴露出來。半導體鰭片208的頂表面T2與絕緣體210a的上表面T1之間具有一高度差H，而高度差H介於約15奈米至約50奈米之間。
圖2F繪示為半導體元件於製作方法的不同階段中的一個階段的透視圖。在圖1的步驟S14與圖2E至圖2F中，於絕緣體210a形成之後，形成一第一介電層212以共形地覆蓋絕緣體210a的上表面T1、半導體鰭片208的頂表面T2以及半導體鰭片208的側壁SW。於一實施例中，第一介電層212可包括氧化矽、氮化矽、氧氮化物或高介電常數的介電材料。高介電常數的介電材料包括金屬氧化物。舉例來說，用於高介電常數的介電材料的金屬氧化物包括氧化物鋰、鈹、鎂、鈣、鍶、鈧、釔、鋯、鉿、鋁、鑭、鈰、鐠、釹、釤、銪、釓、鏑、鈥、鉺、銩、鐿、鑥、與/或上述的混合物。於一實施例中，第一介電層212為厚度為約0.2奈米至5奈米的高介電常數的介電層。第一介電層212可以透過合適的方法，例如是原子層沉積（ALD）、化學氣相沉積（CVD）、物理氣相沉積（PVD）、熱氧化或UV臭氧氧化來形成。第一介電層212足夠薄且具有良好的品質，可作為在短通道的鰭式場效電晶體的閘極介電層。
圖2G繪示為半導體元件於製作方法的不同階段中的一個階段的透視圖。在圖1的步驟S16與圖2F至圖2G中，於第一介電層212上形成至少一第一擬閘極條214a與至少一第二擬閘極條214b，其中第一擬閘極條214a及第二擬閘極條214b的長度方向D1與半導體鰭片208的長度方向D2不同。沿著長度方向D1，第一擬閘極條214a的一第一寬度W1小於第二擬閘極條214b的一第二寬度W2。第一擬閘極條214a與第二擬閘極條214b的長度方向D1例如是垂直於半導體鰭片208的長度方向D2。圖2G中的第一擬閘極條214a與第二擬閘極條214b的數量僅為示意，於其他實施例中，可根據實際的設計需求來形成兩個或更多的第一擬閘極條214a與第二擬閘極條214b。第一擬閘極條214a與第二擬閘極條214b包括含矽材料，例如是多晶矽、非晶矽或上述的組合。於一實施例中，第一擬閘極條214a的第一寬度W1介於5奈米至50奈米之間，而第二擬閘極條214b的第二寬度W2則大於50奈米。
在圖1的步驟S18與圖2G中，於形成第一擬閘極條214a與第二擬閘極條214b之後，於第一擬閘極條214a的側壁與第二擬閘極條214b的側壁上分別形成一對第一間隙物216a與一對第二間隙物216b。如圖2H所示，第一間隙物216a形成在第一介電層212上且沿著第一擬閘極條214a的側壁延伸，而第二間隙物216b形成在第一介電層212上且沿著第二擬閘極條214b的側壁延伸。第一間隙物216a與第二間隙物216b是由介電材料所形成，例如是氮化矽或碳氮氧化矽（SiCON）。第一間隙物216a與第二間隙物216b可包括單層或多層結構。由於第一間隙物216a是由第一擬閘極條214a隔開，因此第一間隙物216a之間的一第一間隙G1實質上等於第一擬閘極條214a的第一寬度W1。同樣地，第二間隙物216b之間的一第二間隙G2實質上等於第二擬閘極條214b的第二寬度W2。
圖2H繪示為半導體元件於製作方法的不同階段中的一個階段的透視圖。如圖2H所示，於第一介電層212上形成多個層間介電層218。層間介電層218的上表面實質上與第一擬閘極條214a的上表面以及第二擬閘極條214b的上表面實質上共平面。於其他實施例中，於層間介電層218形成以前，可以先進行一些製程（例如是第一介電層212的圖案化製程、鰭片凹槽(fin recessing)製程、半導體鰭片上的應變源極/汲極磊晶(strained source/drain epitaxial)製程以及矽化(silicidation)製程等）。上述製程的細節被省略。
圖2I至2J繪示為半導體元件於製作方法的不同階段的透視圖。在圖1的步驟S20及步驟S22與圖2H至圖2J中，移除第一擬閘極條214a與第二擬閘極條214b。於一實施例中，移除第一擬閘極條214a與第二擬閘極條214b的方法例如是一蝕刻製程。透過選擇適當的蝕刻液，層間介電層218、第一介電層212、第一間隙物216a以及第二間隙物216b在第一擬閘極條214a和第二擬閘極條214b的移除過程中便不會被顯著地損壞。於移除第一擬閘極條214a之後，第一間隙物216a之間形成一第一凹槽C1，而第一介電層212的部分因此而被暴露出來。半導體鰭片208對應第一凹槽C1的此部分(繪示在於圖2J的右側部分)仍然被第一介電層212所覆蓋。
如圖2J所示，移除第一介電層212的部分以及位於第二擬閘極條214b的部分絕緣體210a直到第二間隙物216b的側壁、半導體鰭片208的部分以及絕緣體210a的部分被暴露出來而形成第二凹槽C2。於第二凹槽C2的形成過程中，被第一凹槽C1所暴露出的第一介電層212例如是被良好地保護以免於被移除。於一實施例中，被第一凹槽C1所暴露出的第一介電層212可被光阻層所保護及覆蓋以免於被移除。
於第二凹槽C2的形成過程中，第一介電層212會被蝕刻且稍微過度蝕刻。於其他實施例中，於形成第二凹槽C2的過程中，絕緣體210a可以作為一蝕刻終止層，以便控制第二凹槽C2的輪廓。於第二凹槽C2形成之後，半導體鰭片208對應第二凹槽C2的部分(繪示在圖2J的左側部分)會被暴露出來。值得注意的是，沿著半導體鰭片208的長度方向D2，半導體鰭片208對應於第二凹槽C2的部份(繪示在圖2J的左側部分)具有較大尺寸，而半導體鰭片208對應於第一凹槽C1的部分(繪示在圖2J的右側部分)具有較小尺寸。
圖2K繪示為半導體元件於製作方法的不同階段中的一個階段的透視圖。在圖1的步驟S24與圖2J至圖2K中，於形成第二凹槽C2之後，於第二凹槽C2內形成一第二介電層220以選擇性地覆蓋住半導體鰭片208被暴露出來的部分，其中第一介電層212的厚度小於第二介電層220的厚度。第二介電層220選擇性地成長於半導體鰭片208被暴露出來的部分上，據此，形成在第二凹槽C2內的第二介電層220沒有完全覆蓋住絕緣體210a所被暴露出來的部分，而第二間隙物216b的側壁僅僅一部分與第二介電層220接觸。於一實施例中，第二介電層220可以包括氧化矽、氮化矽、氧氮化物或高介電常數的介電材料。高介電常數的介電材料包括金屬氧化物。舉例來說，用於高介電常數的介電材料的金屬氧化物包括氧化物鋰、鈹、鎂、鈣、鍶、鈧、釔、鋯、鉿、鋁、鑭、鈰、鐠、釹、釤、銪、釓、鏑、鈥、鉺、銩、鐿、鑥、與/或上述的混合物。於一實施例中，第二介電層220為一具有厚度在大約5奈米到50奈米的高介電常數的介電層。第二介電層220可透過合適的方法如熱氧化來形成。第二介電層220比第一介電層212更厚，適合用作在長通道的鰭式場效電晶體的閘極介電層。
如圖2K至圖2L所示，於第一凹槽C1內形成一第一閘極222a，並且於第二凹槽C2內形成一第二閘極222b以覆蓋第二介電層220、第二間隙物216b的側壁以及絕緣體210a被暴露出來的部分。第二介電層220配置於第二閘極222b與半導體鰭片208被暴露出的部分之間。第二介電層220不存在於第二閘極222b與第二間隙物216b之間。於一些實施例中，第一閘極222a與第二閘極222b可包括一層或多層結構。於一些實施例中，第一閘極222a與第二閘極222b可包括金屬，例如是鋁、銅、鎢、鈦、鉭、氮化鈦、鋁化鈦、氮化鋁鈦、氮化鉭、矽化鎳、矽化鈷、其他具有功函數且與基底材料相容的導電材料，或上述材料的組合。於一些實施例中，第一閘極222a與第二閘極222b的厚度例如是介於約30奈米至約60奈米之間。第一閘極222a與第二閘極222b可透過合適的方法，例如原子層沉積（ALD）、化學氣相沉積（CVD）、物理氣相沉積（PVD）、電鍍或上述製程的組合來形成。
於一實施例中，第一閘極222a的寬度W3為5奈米至50奈米，而第二閘極222b的寬度W4大於50奈米。與第一閘極222重疊且被第一閘極222a覆蓋的部分半導體鰭片208可作為一短通道鰭式場效電晶體的通道，而與第二閘極222b重疊且被第二閘極222b覆蓋的部分半導體鰭片208可作為長通道鰭式場效電晶體的通道。
如圖2G與圖2L所示，第一閘極222a的寬度W3、第一擬閘極條214a的寬度W1以及第一間隙物216a之間的第一間隙G1實質上相同(即W3=W1=G1)。第二閘極222b的寬度W4、第二擬閘極條214b的寬度W2以及第二間隙物216b之間的第二間隙G2實質上相同(即W4=W2=G2)。
在短通道的鰭式場效電晶體中(繪示於圖2L的右側部分)，較薄的第一介電層212被形成以用作閘極介電層；在長通道的鰭式場效電晶體中(繪示於圖2L的左側部分)，較薄的第一介電層212被移除，且被選擇性地成長以及較厚的第二介電層220所取代。由於第二介電層220具有較大的厚度，半導體鰭片208被暴露出來的部分會被良好地包覆以防止第二閘極222b的漏電路徑(leakage path)和擠出路徑(extrusion path)的形成。因此，閘極置換製程的製程裕度可被放大。據此，可提高半導體元件的良率(yield)和可靠性。
根據本發明的一些實施例，鰭式場效應晶體的製造方法包括至少以下步驟。圖案化基板以形成多個位於基板內的溝渠以及位於溝渠之間的半導體鰭片。於溝渠內形成多個絕緣體。形成第一介電層以覆蓋半導體鰭片與絕緣體。於第一介電層上形成擬閘極條，擬閘極條的長度方向不同於半導體鰭片的長度方向。於擬閘極條的多個側壁上形成一對間隙物。移除擬閘極條與位於擬閘極條下方的第一介電層直到間隙物的多個側壁、半導體鰭片的一部分以及絕緣體的多個部分被暴露出來。形成第二介電層以選擇性地覆蓋半導體鰭片被暴露出來的部分，其中第一介電層的厚度小於第二介電層的厚度。於間隙物之間形成閘極以覆蓋第二介電層、間隙物被暴露出的側壁以及絕緣體被暴露出來的部分。
在所述鰭式場效應晶體的製造方法中，於擬閘極條移除之前，於第一介電層上形成間隙物，且間隙物沿著擬閘極條的側壁延伸。
在所述鰭式場效應晶體的製造方法中，移除擬閘極條與第一介電層以形成一位於間隙物之間的凹槽，而第二介電層形成於凹槽所暴露出的半導體鰭片的部分上。
在所述鰭式場效應晶體的製造方法中，擬閘極條、第一介電層以及部分的絕緣體是在形成凹槽的一蝕刻製程中被移除。
在所述鰭式場效應晶體的製造方法中，第二介電層是透過熱氧化而形成。
在所述鰭式場效應晶體的製造方法中，具有寬度大於50奈米的閘極形成於間隙物之間以覆蓋第二介電層、間隙物被暴露出的側壁以及絕緣體被暴露出的部分。
在所述鰭式場效應晶體的製造方法更包括於移除擬閘極條之前，形成一源極與一汲極於半導體鰭片上。
根據本發明的一些實施例，半導體元件的製作方法至少包括以下步驟。圖案化基板以形成多個位於基板內的溝渠以及多個位於溝渠之間的半導體鰭片。形成多個絕緣體於溝渠內。形成第一介電層以覆蓋半導體鰭片與絕緣體。形成至少一第一擬閘極條與至少一第二擬閘極條於第一介電層上，其中第一擬閘極條與第二擬閘極條的長度方向不同於半導體鰭片的長度方向，且第一擬閘極條的寬度小於第二擬閘極條的寬度。分別形成一對第一間隙物以及一對第二間隙物於第一擬閘極條的多個側壁上以及第二擬閘極條的多個側壁上。移除第一擬閘極條以形成第一凹槽。移除第二擬閘極條與位於第二擬閘極條下方的第一介電層直到第二間隙物的多個側壁、半導體鰭片的一部分以及絕緣體的多個部分被暴露出來，而形成第二凹槽。形成第二介電層於第二凹槽內以選擇性地覆蓋半導體鰭片被暴露出來的部分，其中第一介電層的厚度小於第二介電層的厚度。形成第一閘極於第一凹槽內。形成第二閘極於第二凹槽內以覆蓋第二介電層，第二間隙物被暴露出來的側壁以及絕緣體被暴露出來的部分。
在所述半導體元件的製造方法中，第一擬閘極條與第二擬閘極條於同一步驟中移除。
在所述半導體元件的製造方法中，形成第一擬閘極條與第二擬閘極條的方法，包括：形成導電層於第一介電層上；以及圖案化該導電層以形成具有第一寬度的第一導電條以及具有第二寬度的第二導電條，第一寬度小於第二寬度。
在所述半導體元件的製造方法中，第一間隙物形成於第一介電層上且沿著第一擬閘極條的側壁延伸，第二間隙物形成於第一介電層上且沿著第二擬閘極條的側壁延伸。
在所述半導體元件的製造方法中，移除第二擬閘極條，位於第二擬閘極條下方的第一介電層以及部分的絕緣體是在形成第二凹槽的蝕刻製程中。
在所述半導體元件的製造方法中，第二介電層是透過熱氧化而形成。具有寬度介於5奈米至50奈米的第一閘極形成於第一凹槽內，而具有寬度大於50奈米的第二閘極形成於第二凹槽內，以覆蓋第二介電層、第二間隙物的被暴露出來的側壁以及絕緣體被暴露出來的部分。
在所述半導體元件的製造方法中，半導體元件的製作方法，更包括:於移除第一擬閘極條與第二擬閘極條之前，形成多個源極與多個汲極於半導體鰭片上。
根據本發明的其他實施例，半導體元件包括一基板、多個絕緣體、一第一介電層、一對第一間隙物、一第一閘極、一對第二間隙物、一第二介電層和一第二閘極。基板包括多個溝渠以及多個位於溝渠之間的半導體鰭片。絕緣體位於溝渠內。第一介電層覆蓋半導體鰭片與絕緣體，且暴露出半導體鰭片的一部分以及絕緣體的部分。第一間隙物配置於第一介電層上。第一閘極配置於第一介電層上且位於第一間隙物之間。第二間隙物配置於第一介電層上。第二介電層配置於第二間隙物之間，其中第二介電層選擇性覆蓋半導體鰭片被暴露出來的部分，而第一介電層的厚度小於第二介電層的厚度。第二閘極配置於第二間隙物之間以覆蓋第二介電層、第二間隙物被暴露出的側壁以及絕緣體被暴露出來的部分，其中第一閘極的寬度小於第二閘極的寬度。
在所述半導體元件中，第一介電層的厚度介於0.2奈米至5奈米之間，且第二介電層的厚度介於5奈米至50奈米之間。
在所述半導體元件中，第一閘極的寬度介於5奈米至50奈米之間，而第二閘極的寬度大於50奈米。
在所述半導體元件中，第二閘極的寬度實質上等於第二間隙物之間的一間隙。
在所述半導體元件中，第二介電層配置於半導體鰭片被暴露出出來的部分與第二閘極之間。
以上概述了數個實施例的特徵，使本領域具有通常知識者可更佳了解本發明的態樣。本領域具有通常知識者應理解，其可輕易地使用本發明作為設計或修改其他製程與結構的依據，以實行本文所介紹的實施例的相同目的及/或達到相同優點。本領域具有通常知識者還應理解，這種等效的配置並不悖離本發明的精神與範疇，且本領域具有通常知識者在不悖離本發明的精神與範疇的情況下可對本文做出各種改變、置換以及變更。
200、200a‧‧‧基板 202a‧‧‧接墊層 202a’‧‧‧圖案化接墊層 202b‧‧‧遮罩層 202b’‧‧‧圖案化遮罩層 204‧‧‧圖案化光阻層 206‧‧‧溝渠 208‧‧‧半導體鰭片 210‧‧‧絕緣材料 210a‧‧‧絕緣體 212‧‧‧第一介電層 214a‧‧‧第一擬閘極條 214b‧‧‧第二擬閘極條 216a‧‧‧第一間隙物 216b‧‧‧第二間係物 218‧‧‧層間介電層 220‧‧‧第二介電層 222a‧‧‧第一閘極 222b‧‧‧第二閘極 C1‧‧‧第一凹槽 C2‧‧‧第二凹槽 D1、D2‧‧‧長度方向 G1‧‧‧第一間隙 G2‧‧‧第二間隙 H‧‧‧高度差 S‧‧‧間隙 T1‧‧‧上表面 T2‧‧‧頂表面 SW‧‧‧側壁 W1‧‧‧第一寬度 W2‧‧‧第二寬度 W3、W4‧‧‧寬度 S10、S12、S14、S16、S18、S20、S22、S24、S26‧‧‧步驟
圖1繪示為根據一些實施例的一種半導體元件的製作方法的流程圖。 圖2A至圖2L是根據一些實施例的一種半導體元件的製造方法的透視圖。
S10、S12、S14、S16、S18、S20、S22、S24、S26‧‧‧步驟

Claims (1)

  1. 一種鰭式場效電晶體的製作方法，包括： 圖案化一基板以形成多個位於該基板內的溝渠以及位於該些溝渠之間的一半導體鰭片； 於該些溝渠內形成多個絕緣體； 形成一第一介電層以覆蓋該半導體鰭片與該些絕緣體； 於該第一介電層上形成一擬閘極條，該擬閘極條的長度方向不同於該半導體鰭片的長度方向； 於該擬閘極條的多個側壁上形成一對間隙物； 移除該擬閘極條與位於該擬閘極條下方的該第一介電層直到該些間隙物的多個側壁、該半導體鰭片的一部分以及該些絕緣體的多個部分被暴露出來； 形成一第二介電層以選擇性地覆蓋該半導體鰭片被暴露出來的該部分，其中該第一介電層的厚度小於該第二介電層的厚度；以及 於該些間隙物之間形成一閘極以覆蓋該第二介電層、該些間隙物被暴露出的該些側壁以及該些絕緣體被暴露出來的部分。
TW105137192A 2015-11-16 2016-11-15 鰭式場效電晶體的製作方法與半導體元件及其製作方法 TWI682467B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/941,673 2015-11-16
US14/941,673 US10020304B2 (en) 2015-11-16 2015-11-16 Fin field effect transistor, semiconductor device and fabricating method thereof

Publications (2)

Publication Number Publication Date
TW201719769A true TW201719769A (zh) 2017-06-01
TWI682467B TWI682467B (zh) 2020-01-11

Family

ID=58692155

Family Applications (1)

Application Number Title Priority Date Filing Date
TW105137192A TWI682467B (zh) 2015-11-16 2016-11-15 鰭式場效電晶體的製作方法與半導體元件及其製作方法

Country Status (3)

Country Link
US (3) US10020304B2 (zh)
CN (1) CN106711046B (zh)
TW (1) TWI682467B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109698119A (zh) * 2017-10-23 2019-04-30 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法和半导体器件
US10867860B2 (en) 2018-08-30 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming FinFET device

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150214331A1 (en) * 2014-01-30 2015-07-30 Globalfoundries Inc. Replacement metal gate including dielectric gate material
US10020304B2 (en) * 2015-11-16 2018-07-10 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor, semiconductor device and fabricating method thereof
CN107452679B (zh) * 2016-06-01 2020-05-05 中芯国际集成电路制造(上海)有限公司 半导体装置及其制造方法
US10460995B2 (en) * 2016-11-29 2019-10-29 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacture of a FinFET device
US10679988B2 (en) * 2017-09-18 2020-06-09 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including FinFETS having different channel heights and manufacturing method thereof
US10325912B2 (en) * 2017-10-30 2019-06-18 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure cutting process and structures formed thereby
US10515815B2 (en) * 2017-11-21 2019-12-24 Lam Research Corporation Atomic layer deposition and etch in a single plasma chamber for fin field effect transistor formation
DE102018126911A1 (de) * 2017-11-30 2019-06-06 Intel Corporation Gate-Schnitt und Finnentrimmisolation für fortschrittliche Integrierter-Schaltkreis-Struktur-Fertigung
TW202333375A (zh) 2017-11-30 2023-08-16 美商英特爾股份有限公司 用於先進積體電路結構製造的鰭切割和鰭修整隔離
US11881520B2 (en) * 2017-11-30 2024-01-23 Intel Corporation Fin patterning for advanced integrated circuit structure fabrication
KR102535087B1 (ko) * 2018-04-20 2023-05-19 삼성전자주식회사 반도체 장치
US10586860B2 (en) 2018-05-03 2020-03-10 Globalfoundries Inc. Method of manufacturing finfet devices using narrow and wide gate cut openings in conjunction with a replacement metal gate process
US10886269B2 (en) * 2018-09-18 2021-01-05 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US11508735B2 (en) * 2019-08-28 2022-11-22 Taiwan Semiconductor Manufacturing Company, Ltd. Cell manufacturing
EP3813124A1 (en) * 2019-10-22 2021-04-28 Imec VZW Split replacement metal gate integration
CN112909090A (zh) * 2019-12-04 2021-06-04 吴俊鹏 环绕式栅极组件及其制造方法
US20220328641A1 (en) * 2021-04-09 2022-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. Gate-all-around structures and manufacturing method thereof

Family Cites Families (154)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6054355A (en) * 1997-06-30 2000-04-25 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device which includes forming a dummy gate
JP3851752B2 (ja) * 2000-03-27 2006-11-29 株式会社東芝 半導体装置の製造方法
JP2004087960A (ja) * 2002-08-28 2004-03-18 Fujitsu Ltd 半導体装置の製造方法
US7183184B2 (en) * 2003-12-29 2007-02-27 Intel Corporation Method for making a semiconductor device that includes a metal gate electrode
CN100385667C (zh) * 2004-01-06 2008-04-30 台湾积体电路制造股份有限公司 集成电路及其制造方法
US7157378B2 (en) * 2004-07-06 2007-01-02 Intel Corporation Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode
US7361958B2 (en) * 2004-09-30 2008-04-22 Intel Corporation Nonplanar transistors with metal gate electrodes
US7230287B2 (en) * 2005-08-10 2007-06-12 International Business Machines Corporation Chevron CMOS trigate structure
KR100652433B1 (ko) * 2005-09-08 2006-12-01 삼성전자주식회사 다중 비트 저장이 가능한 비휘발성 메모리 소자 및 그 제조방법
US7462538B2 (en) * 2005-11-15 2008-12-09 Infineon Technologies Ag Methods of manufacturing multiple gate CMOS transistors having different gate dielectric materials
US7521775B2 (en) * 2006-06-13 2009-04-21 Intel Corporation Protection of three dimensional transistor structures during gate stack etch
US7517764B2 (en) * 2006-06-29 2009-04-14 International Business Machines Corporation Bulk FinFET device
US20080079084A1 (en) * 2006-09-28 2008-04-03 Micron Technology, Inc. Enhanced mobility MOSFET devices
KR20080046438A (ko) * 2006-11-22 2008-05-27 삼성전자주식회사 반도체 소자 및 그 제조 방법
US7898040B2 (en) * 2007-06-18 2011-03-01 Infineon Technologies Ag Dual gate FinFET
US7700993B2 (en) * 2007-11-05 2010-04-20 International Business Machines Corporation CMOS EPROM and EEPROM devices and programmable CMOS inverters
DE102007063270B4 (de) * 2007-12-31 2011-06-01 Amd Fab 36 Limited Liability Company & Co. Kg Verfahren zur Verringerung zur Erzeugung von Ladungseinfangstellen in Gatedielektrika in MOS-Transistoren durch Ausführen einer Wasserstoffbehandlung
DE102008059500B4 (de) * 2008-11-28 2010-08-26 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung eines Mehr-Gatetransistors mit homogen silizidierten Stegendbereichen
US8173499B2 (en) * 2009-06-12 2012-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. Method of fabricating a gate stack integration of complementary MOS device
US7855105B1 (en) * 2009-06-18 2010-12-21 International Business Machines Corporation Planar and non-planar CMOS devices with multiple tuned threshold voltages
US8415718B2 (en) * 2009-10-30 2013-04-09 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming epi film in substrate trench
US8269283B2 (en) * 2009-12-21 2012-09-18 Intel Corporation Methods and apparatus to reduce layout based strain variations in non-planar transistor structures
US20110147848A1 (en) * 2009-12-23 2011-06-23 Kuhn Kelin J Multiple transistor fin heights
JP5410398B2 (ja) * 2010-01-13 2014-02-05 パナソニック株式会社 半導体装置
DE102010003555B4 (de) * 2010-03-31 2019-12-24 Globalfoundries Dresden Module One Llc & Co. Kg Aluminiumsicherungen in einem Halbleiterbauelement, das Metallgateelektrodenstrukturen aufweist
US8450169B2 (en) * 2010-11-29 2013-05-28 International Business Machines Corporation Replacement metal gate structures providing independent control on work function and gate leakage current
CN102487085B (zh) * 2010-12-01 2014-04-23 中国科学院微电子研究所 半导体器件及其制造方法
US8704294B2 (en) * 2011-06-13 2014-04-22 United Microelectronics Corp. Semiconductor device having metal gate and manufacturing method thereof
US8723272B2 (en) * 2011-10-04 2014-05-13 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device and method of manufacturing same
US8623716B2 (en) * 2011-11-03 2014-01-07 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-gate semiconductor devices and methods of forming the same
US8987824B2 (en) * 2011-11-22 2015-03-24 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-gate semiconductor devices
US8901665B2 (en) * 2011-12-22 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Gate structure for semiconductor device
CN107680968B (zh) * 2011-12-28 2022-02-22 英特尔公司 在三栅极(finfet)工艺上集成多个栅极电介质晶体管的方法
CN104011842B (zh) * 2011-12-31 2016-10-26 英特尔公司 用于高鳍状物的硬掩模蚀刻停止层
CN104125843A (zh) * 2012-01-10 2014-10-29 赛诺菲-安万特德国有限公司 用于皮内注射的引导组件
US8809178B2 (en) * 2012-02-29 2014-08-19 Globalfoundries Inc. Methods of forming bulk FinFET devices with replacement gates so as to reduce punch through leakage currents
US9263342B2 (en) * 2012-03-02 2016-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having a strained region
KR101850409B1 (ko) * 2012-03-15 2018-06-01 삼성전자주식회사 듀얼 게이트 절연막을 갖는 반도체 장치의 제조 방법
US9666690B2 (en) * 2012-05-02 2017-05-30 GlobalFoundries, Inc. Integrated circuit and method for fabricating the same having a replacement gate structure
KR20130127257A (ko) * 2012-05-14 2013-11-22 삼성전자주식회사 반도체 장치 및 그 제조 방법
US8629511B2 (en) * 2012-05-15 2014-01-14 International Business Machines Corporation Mask free protection of work function material portions in wide replacement gate electrodes
US9012975B2 (en) * 2012-06-14 2015-04-21 United Microelectronics Corp. Field effect transistor and manufacturing method thereof
US8941177B2 (en) * 2012-06-27 2015-01-27 International Business Machines Corporation Semiconductor devices having different gate oxide thicknesses
CN103531453B (zh) * 2012-07-02 2016-12-21 中芯国际集成电路制造(上海)有限公司 半导体集成器件及其制作方法
US8940626B2 (en) * 2012-07-05 2015-01-27 Globalfoundries Inc. Integrated circuit and method for fabricating the same having a replacement gate structure
CN103545183B (zh) * 2012-07-12 2016-06-29 中芯国际集成电路制造(上海)有限公司 Cmos器件及其制作方法
US9136177B2 (en) * 2012-07-30 2015-09-15 Globalfoundries Inc. Methods of forming transistor devices with high-k insulation layers and the resulting devices
US8772146B2 (en) * 2012-08-28 2014-07-08 Samsung Electronics Co., Ltd. Semiconductor device and method for fabricating the same
US20140061792A1 (en) * 2012-08-28 2014-03-06 International Business Machines Corporation Field effect transistor devices with recessed gates
US8703556B2 (en) * 2012-08-30 2014-04-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method of making a FinFET device
US9318567B2 (en) * 2012-09-05 2016-04-19 United Microelectronics Corp. Fabrication method for semiconductor devices
US8803253B2 (en) * 2012-09-11 2014-08-12 Texas Instruments Incorporated Replacement metal gate process for CMOS integrated circuits
US20140070328A1 (en) * 2012-09-12 2014-03-13 Toshiba America Electronic Components, Inc. Semiconductor device and method of fabricating the same
US8753970B2 (en) * 2012-09-12 2014-06-17 Globalfoundries Inc. Methods of forming semiconductor devices with self-aligned contacts and the resulting devices
US20140103452A1 (en) * 2012-10-15 2014-04-17 Marvell World Trade Ltd. Isolation components for transistors formed on fin features of semiconductor substrates
US9064948B2 (en) * 2012-10-22 2015-06-23 Globalfoundries Inc. Methods of forming a semiconductor device with low-k spacers and the resulting device
US8809139B2 (en) * 2012-11-29 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Fin-last FinFET and methods of forming same
CN103855094A (zh) * 2012-11-30 2014-06-11 中国科学院微电子研究所 半导体器件及其制造方法
JP5989538B2 (ja) * 2012-12-25 2016-09-07 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US9013003B2 (en) * 2012-12-27 2015-04-21 United Microelectronics Corp. Semiconductor structure and process thereof
CN103928333B (zh) * 2013-01-15 2019-03-12 中国科学院微电子研究所 半导体器件及其制造方法
KR102049774B1 (ko) * 2013-01-24 2019-11-28 삼성전자 주식회사 반도체 장치 및 그 제조 방법
US8987791B2 (en) * 2013-02-27 2015-03-24 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs and methods for forming the same
US8826213B1 (en) * 2013-03-11 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Parasitic capacitance extraction for FinFETs
US8943455B2 (en) * 2013-03-12 2015-01-27 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for layout verification for polysilicon cell edge structures in FinFET standard cells
US9231045B2 (en) * 2013-04-30 2016-01-05 GlobalFoundries, Inc. Methods for fabricating integrated circuits with polycrystalline silicon resistor structures using a replacment gate process flow, and the integrated circuits fabricated thereby
US8877625B1 (en) * 2013-05-14 2014-11-04 Globalfoundries Inc. Methods of forming semiconductor devices with different insulation thickness on the same semiconductor substrate and the resulting devices
KR102078187B1 (ko) * 2013-05-31 2020-02-17 삼성전자 주식회사 반도체 장치 및 그 제조 방법
US9000536B2 (en) * 2013-06-28 2015-04-07 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor having a highly doped region
US9847404B2 (en) * 2013-07-06 2017-12-19 Semiwise Limited Fluctuation resistant FinFET
US20150021681A1 (en) * 2013-07-16 2015-01-22 United Microelectronics Corp. Semiconductor device having metal gate and manufacturing method thereof
US20150024584A1 (en) * 2013-07-17 2015-01-22 Global Foundries, Inc. Methods for forming integrated circuits with reduced replacement metal gate height variability
US9349850B2 (en) * 2013-07-17 2016-05-24 Taiwan Semiconductor Manufacturing Company, Ltd. Thermally tuning strain in semiconductor devices
KR102073967B1 (ko) * 2013-07-30 2020-03-02 삼성전자주식회사 전계 효과 트랜지스터를 포함하는 반도체 소자
US9257348B2 (en) * 2013-08-06 2016-02-09 Globalfoundries Inc. Methods of forming replacement gate structures for transistors and the resulting devices
US8951868B1 (en) * 2013-11-05 2015-02-10 International Business Machines Corporation Formation of functional gate structures with different critical dimensions using a replacement gate process
US9093302B2 (en) * 2013-11-13 2015-07-28 Globalfoundries Inc. Methods of forming substantially self-aligned isolation regions on FinFET semiconductor devices and the resulting devices
KR102105363B1 (ko) * 2013-11-21 2020-04-28 삼성전자 주식회사 반도체 장치 및 그 제조 방법
US9082851B2 (en) * 2013-11-22 2015-07-14 International Business Machines Corporation FinFET having suppressed leakage current
KR102085525B1 (ko) * 2013-11-27 2020-03-09 삼성전자 주식회사 반도체 장치 및 그 제조 방법
CN104733312B (zh) * 2013-12-18 2018-09-07 中芯国际集成电路制造(上海)有限公司 鳍式场效应晶体管的形成方法
US9184087B2 (en) * 2013-12-27 2015-11-10 Taiwan Semiconductor Manufacturing Co., Ltd. Mechanisms for forming FinFETs with different fin heights
KR102155511B1 (ko) * 2013-12-27 2020-09-15 삼성전자 주식회사 반도체 장치 및 그 제조 방법
US9219116B2 (en) * 2014-01-15 2015-12-22 Taiwan Semiconductor Manufacturing Company, Ltd. Fin structure of semiconductor device
US9515186B2 (en) * 2014-01-23 2016-12-06 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same
US9627375B2 (en) * 2014-02-07 2017-04-18 Taiwan Semiconductor Manufacturing Company Ltd. Indented gate end of non-planar transistor
US9620621B2 (en) * 2014-02-14 2017-04-11 Taiwan Semiconductor Manufacturing Company Ltd. Gate structure of field effect transistor with footing
US9401415B2 (en) * 2014-02-14 2016-07-26 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor (FinFET) device and method for forming the same
US9553171B2 (en) * 2014-02-14 2017-01-24 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor (FinFET) device and method for forming the same
CN104867873B (zh) * 2014-02-21 2018-03-20 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法
US9312136B2 (en) * 2014-03-06 2016-04-12 International Business Machines Corporation Replacement metal gate stack for diffusion prevention
KR102212267B1 (ko) * 2014-03-19 2021-02-04 삼성전자주식회사 반도체 장치 및 그 제조 방법
US9202812B2 (en) * 2014-03-21 2015-12-01 International Business Machines Corporation Abrupt source/drain junction formation using a diffusion facilitation layer
US9431537B2 (en) * 2014-03-26 2016-08-30 Samsung Electronics Co., Ltd. Semiconductor devices and methods of fabricating the same
US9171934B2 (en) * 2014-04-01 2015-10-27 Globalfoundries Inc. Methods of forming semiconductor devices using a layer of material having a plurality of trenches formed therein
KR102017611B1 (ko) * 2014-04-04 2019-09-04 삼성전자주식회사 반도체 장치 및 그 제조방법
US9559191B2 (en) * 2014-04-16 2017-01-31 International Business Machines Corporation Punch through stopper in bulk finFET device
US10468528B2 (en) * 2014-04-16 2019-11-05 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device with high-k metal gate stack
US9525069B2 (en) * 2014-04-21 2016-12-20 Globalfoundries Inc. Structure and method to form a FinFET device
CN105023843A (zh) * 2014-04-22 2015-11-04 联华电子股份有限公司 半导体元件的制作方法
CN105097701B (zh) * 2014-04-25 2017-11-03 中芯国际集成电路制造(上海)有限公司 静态存储单元的形成方法
KR102146469B1 (ko) * 2014-04-30 2020-08-21 삼성전자 주식회사 반도체 장치 및 이의 제조 방법
US9112032B1 (en) * 2014-06-16 2015-08-18 Globalfoundries Inc. Methods of forming replacement gate structures on semiconductor devices
US9530665B2 (en) * 2014-06-24 2016-12-27 International Business Machines Corporation Protective trench layer and gate spacer in finFET devices
US9190272B1 (en) * 2014-07-15 2015-11-17 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same
US9190488B1 (en) * 2014-08-13 2015-11-17 Globalfoundries Inc. Methods of forming gate structure of semiconductor devices and the resulting devices
US9536985B2 (en) * 2014-09-29 2017-01-03 Globalfoundries Inc. Epitaxial growth of material on source/drain regions of FinFET structure
TWI600159B (zh) * 2014-10-01 2017-09-21 聯華電子股份有限公司 半導體元件及其製作方法
US10134861B2 (en) * 2014-10-08 2018-11-20 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure and method for forming the same
US9362001B2 (en) * 2014-10-14 2016-06-07 Ememory Technology Inc. Memory cell capable of operating under low voltage conditions
US9478634B2 (en) * 2014-11-07 2016-10-25 Globalfoundries Inc. Methods of forming replacement gate structures on finFET devices and the resulting devices
US9305923B1 (en) * 2014-12-02 2016-04-05 International Business Machines Corporation Low resistance replacement metal gate structure
US9425103B2 (en) * 2014-12-04 2016-08-23 Globalfoundries Inc. Methods of using a metal protection layer to form replacement gate structures for semiconductor devices
US9362181B1 (en) * 2014-12-05 2016-06-07 Globalfoundries Inc. Methods of forming diffusion breaks on integrated circuit products comprised of FinFET devices and the resulting products
US9590032B2 (en) * 2014-12-12 2017-03-07 Taiwan Semiconductor Manufacturing Co., Ltd. Fin-FET device and manufacturing method thereof
US9564501B2 (en) * 2014-12-23 2017-02-07 Stmicroelectronics, Inc. Reduced trench profile for a gate
CN105810729B (zh) * 2014-12-29 2018-09-11 中国科学院微电子研究所 鳍式场效应晶体管及其制造方法
US9478660B2 (en) * 2015-01-12 2016-10-25 Taiwan Semiconductor Manufacturing Co., Ltd. Protection layer on fin of fin field effect transistor (FinFET) device structure
US9929242B2 (en) * 2015-01-12 2018-03-27 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US9502567B2 (en) * 2015-02-13 2016-11-22 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor fin structure with extending gate structure
US9331074B1 (en) * 2015-01-30 2016-05-03 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US9425318B1 (en) * 2015-02-27 2016-08-23 GlobalFoundries, Inc. Integrated circuits with fets having nanowires and methods of manufacturing the same
US9530869B2 (en) * 2015-03-10 2016-12-27 Globalfoundries Inc. Methods of forming embedded source/drain regions on finFET devices
US9570315B2 (en) * 2015-03-18 2017-02-14 United Microelectronics Corporation Method of interfacial oxide layer formation in semiconductor device
KR102455149B1 (ko) * 2015-05-06 2022-10-18 삼성전자주식회사 반도체 소자의 제조 방법
US9496183B1 (en) * 2015-05-07 2016-11-15 International Business Machines Corporation Selective thickening of pFET dielectric
US9583485B2 (en) * 2015-05-15 2017-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Fin field effect transistor (FinFET) device structure with uneven gate structure and method for forming the same
US9748394B2 (en) * 2015-05-20 2017-08-29 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET having a multi-portioned gate stack
KR20160141034A (ko) * 2015-05-27 2016-12-08 삼성전자주식회사 반도체 소자 및 반도체 소자의 제조 방법
US9613958B2 (en) * 2015-06-10 2017-04-04 International Business Machines Corporation Spacer chamfering gate stack scheme
US9564489B2 (en) * 2015-06-29 2017-02-07 Taiwan Semiconductor Manufacturing Company, Ltd. Multiple gate field-effect transistors having oxygen-scavenged gate stack
KR102214096B1 (ko) * 2015-08-06 2021-02-09 삼성전자주식회사 반도체 장치 제조 방법
US9576980B1 (en) * 2015-08-20 2017-02-21 International Business Machines Corporation FinFET devices having gate dielectric structures with different thicknesses on same semiconductor structure
US9607838B1 (en) * 2015-09-18 2017-03-28 Taiwan Semiconductor Manufacturing Co., Ltd. Enhanced channel strain to reduce contact resistance in NMOS FET devices
US9570580B1 (en) * 2015-10-30 2017-02-14 Taiwan Semiconductor Manufacturing Company, Ltd. Replacement gate process for FinFET
CN106653691A (zh) * 2015-11-04 2017-05-10 中芯国际集成电路制造(上海)有限公司 半导体结构的制造方法
CN106684144B (zh) * 2015-11-05 2019-11-01 中芯国际集成电路制造(上海)有限公司 半导体结构的制造方法
US10020304B2 (en) * 2015-11-16 2018-07-10 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor, semiconductor device and fabricating method thereof
US9412616B1 (en) * 2015-11-16 2016-08-09 Globalfoundries Inc. Methods of forming single and double diffusion breaks on integrated circuit products comprised of FinFET devices and the resulting products
US9461044B1 (en) * 2015-11-30 2016-10-04 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor, semiconductor device and fabricating method thereof
US9954081B2 (en) * 2015-12-15 2018-04-24 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor, semiconductor device and fabricating method thereof
EP4071787B1 (en) * 2015-12-18 2023-09-27 Floadia Corporation Memory cell, nonvolatile semiconductor storage device, and method for manufacturing nonvolatile semiconductor storage device
US9704969B1 (en) * 2015-12-31 2017-07-11 Taiwan Semiconductor Manufacturing Co., Ltd. Fin semiconductor device having multiple gate width structures
US20170200803A1 (en) * 2016-01-11 2017-07-13 Samsung Electronics Co., Ltd. Semiconductor device and method for fabricating the same
US9773792B1 (en) * 2016-03-25 2017-09-26 Taiwan Semiconductor Manufacturing Co., Ltd. One-time programming cell
EP3244447A1 (en) * 2016-05-11 2017-11-15 IMEC vzw Method for forming a gate structure and a semiconductor device
US9741717B1 (en) * 2016-10-10 2017-08-22 International Business Machines Corporation FinFETs with controllable and adjustable channel doping
US10164063B2 (en) * 2016-12-14 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure with protection layer
US10242982B2 (en) * 2017-03-10 2019-03-26 Globalfoundries Inc. Method for forming a protection device having an inner contact spacer and the resulting devices
CN108807532B (zh) * 2017-04-28 2021-07-06 中芯国际集成电路制造(上海)有限公司 半导体装置及其制造方法
US10475895B2 (en) * 2017-05-25 2019-11-12 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method for manufacturing the same
US10170317B1 (en) * 2017-09-28 2019-01-01 Taiwan Semiconductor Manufacturing Co., Ltd. Self-protective layer formed on high-k dielectric layer
US10461080B2 (en) * 2017-11-30 2019-10-29 Taiwan Semiconductor Manufacturing Co., Ltd. Method for manufacturing a FinFET device
US10535517B2 (en) * 2018-03-23 2020-01-14 International Business Machines Corporation Gate stack designs for analog and logic devices in dual channel Si/SiGe CMOS

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109698119A (zh) * 2017-10-23 2019-04-30 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法和半导体器件
CN109698119B (zh) * 2017-10-23 2021-02-19 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法和半导体器件
US10867860B2 (en) 2018-08-30 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming FinFET device
TWI739147B (zh) * 2018-08-30 2021-09-11 台灣積體電路製造股份有限公司 半導體裝置及其形成方法

Also Published As

Publication number Publication date
US20200243520A1 (en) 2020-07-30
CN106711046A (zh) 2017-05-24
US20180315754A1 (en) 2018-11-01
US20170141106A1 (en) 2017-05-18
US10020304B2 (en) 2018-07-10
US11699701B2 (en) 2023-07-11
US10622353B2 (en) 2020-04-14
CN106711046B (zh) 2021-08-06
TWI682467B (zh) 2020-01-11

Similar Documents

Publication Publication Date Title
TWI682467B (zh) 鰭式場效電晶體的製作方法與半導體元件及其製作方法
US11682697B2 (en) Fin recess last process for FinFET fabrication
TWI711086B (zh) 用於製造鰭狀場效電晶體的方法、半導體裝置及用於製造其的方法
TWI740857B (zh) 鰭式場效電晶體的製作方法
TWI624875B (zh) 鰭式場效應電晶體及其製造方法
KR101637679B1 (ko) Ｆⅰｎｆｅｔ을 형성하기 위한 메커니즘들을 포함하는 반도체 디바이스및 그 형성 방법
US10868179B2 (en) Fin-type field effect transistor structure and manufacturing method thereof
US9899526B2 (en) Fin-type field effect transistor structure and manufacturing method thereof
TW201735265A (zh) 半導體結構及其製造方法
CN112530943A (zh) 半导体器件及其制造方法
TWI710030B (zh) 半導體元件及半導體元件的製造方法
US9793174B1 (en) FinFET device on silicon-on-insulator and method of forming the same
US10014295B2 (en) Self heating reduction for analog radio frequency (RF) device
US20170148789A1 (en) Effective device formation for advanced technology nodes with aggressive fin-pitch scaling
US10158023B2 (en) Fabricating method of fin field effect transistor
CN107706110B (zh) FinFET器件的制造方法
CN115719707A (zh) 一种围栅器件及其制造方法