TW201719769A - 鰭式場效電晶體的製作方法 - Google Patents

鰭式場效電晶體的製作方法 Download PDF

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TW201719769A
TW201719769A TW105137192A TW105137192A TW201719769A TW 201719769 A TW201719769 A TW 201719769A TW 105137192 A TW105137192 A TW 105137192A TW 105137192 A TW105137192 A TW 105137192A TW 201719769 A TW201719769 A TW 201719769A
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dielectric layer
gate strip
semiconductor
exposed
gate
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TW105137192A
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TWI682467B (zh
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張哲誠
林志翰
曾鴻輝
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台灣積體電路製造股份有限公司
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Abstract

一種鰭式場效電晶體的製作方法，包括：圖案化基板以形成多個溝渠以及位於溝渠之間的半導體鰭片。於溝渠內形成多個絕緣體，並且形成第一介電層以覆蓋半導體鰭片與絕緣體。於第一介電層上形成擬閘極條。於擬閘極條的側壁上形成多個間隙物擬閘極條。移除擬閘極條與位於其下方的第一介電層直到間隙物的側壁、半導體鰭片的部分以及絕緣體的部分被暴露出來。形成第二介電層以選擇性地覆蓋半導體鰭片被暴露出來的部分，其中第一介電層的厚度小於第二介電層的厚度。於間隙物之間形成閘極以覆蓋第二介電層、間隙物的側壁以及絕緣體被暴露出的部分。

Description

鰭式場效電晶體的製作方法
本發明是有關於一種鰭式場效電晶體。
由於半導體元件的尺寸不斷縮小，三維多閘極結構，例如鰭式場效電晶體（FinFET）已被開發，以取代平面互補金屬氧化物半導體（CMOS）元件。鰭式場效電晶體的結構特徵為矽基鰭片（silicon based fin）從基板的表面垂直延伸，並且閘極會圍繞由鰭片所形成的導電通道，以對通道進一步提供更好的電氣控制。
以具有短通道（即通道長度小於50奈米）的鰭式場效應晶體的閘極替換製程為例，覆蓋矽基鰭片的部分氧化物層需要被過度蝕刻，以使得後續的高介電常數介電層和閘極的沈積具有更好的製程裕度(process window)。然而，氧化物層的高蝕刻量會導致金屬閘極的漏電路徑和擠出路徑產生。
一種鰭式場效電晶體的製作方法，包括：圖案化基板以形成多個位於基板內的溝渠以及位於溝渠之間的半導體鰭片；於溝渠內形成多個絕緣體；形成第一介電層以覆蓋半導體鰭片與絕緣體；於第一介電層上形成擬閘極條，擬閘極條的長度方向不同於半導體鰭片的長度方向；於擬閘極條的多個側壁上形成一對間隙物；移除擬閘極條與位於其下方的第一介電層直到間隙物的多個側壁、半導體鰭片的一部分以及絕緣體的多個部分被暴露出來；形成第二介電層以選擇性地覆蓋半導體鰭片被暴露出來的部分，其中第一介電層的厚度小於第二介電層的厚度；以及於間隙物之間形成閘極以覆蓋第二介電層、間隙物被暴露出的側壁以及絕緣體被暴露出來的部分。
以下揭露內容提供用於實施所提供的標的之不同特徵的許多不同實施例或實例。以下所描述的構件及配置的具體實例是為了以簡化的方式傳達本發明為目的。當然，這些僅僅為實例而非用以限制。舉例來說，於以下描述中，在第一特徵上方或在第一特徵上形成第二特徵可包括第二特徵與第一特徵形成為直接接觸的實施例，且亦可包括第二特徵與第一特徵之間可形成有額外特徵使得第二特徵與第一特徵可不直接接觸的實施例。此外，本發明在各種實例中可使用相同的元件符號及/或字母來指代相同或類似的部件。元件符號的重複使用是為了簡單及清楚起見，且並不表示所欲討論的各個實施例及/或配置本身之間的關係。
另外，為了易於描述附圖中所繪示的一個構件或特徵與另一組件或特徵的關係，本文中可使用例如「在…下」、「在…下方」、「下部」、「在…上」、「在…上方」、「上部」及類似術語的空間相對術語。除了附圖中所繪示的定向之外，所述空間相對術語意欲涵蓋元件在使用或操作時的不同定向。設備可被另外定向（旋轉90度或在其他定向），而本文所用的空間相對術語相應地作出解釋。
本發明的實施例中所揭露的半導體元件的製作方法，而前述的半導體元件包括至少一個長通道的鰭式場效電晶體以及至少一個短通道的鰭式場效電晶體。在本發明的某些實施例中，半導體元件可形成塊狀矽基板（bulk silicon substrates）上。當然，半導體元件亦可以選擇地形成在絕緣體上矽（silicon-on-insulator，SOI）基板或絕緣體上鍺（germanium-on-insulator，GOI）基板上。此外，根據實施例，矽基板可以包括其它導電層或其它半導體元件，例如電晶體、二極管或類似物。上述的實施例並不限於此。
請參考圖1，其依據本發明的一些實施例繪示出一種半導體元件的製作方法的流程圖。所述的製作方法至少包括步驟S10、步驟S12、步驟S14、步驟S16、步驟S18、步驟S20、步驟S22、步驟S24以及步驟S26。首先，在步驟S10中，提供一基板，接著，圖案化基板以形成多個溝渠以及多個位於溝渠之間的半導體鰭片。在步驟S12中，於溝渠內形成多個絕緣體。前述的絕緣體例如是用以絕緣半導體鰭片的淺溝渠隔離(shallow trench isolation，STI)結構。在步驟S14中，形成一第一介電層以覆蓋半導體鰭片以及絕緣體。在步驟S16中，於第一介電層上形成至少一第一擬閘極條與至少一第二擬閘極條，其中第一擬閘極條的長度方向與第二擬閘極條的長度方向不同，而第一擬閘極條的寬度小於第二擬閘極條的寬度。第一擬閘極條與第二擬閘極條為導電條，例如是多晶矽條。在步驟S18中，於第一擬閘極條與第二擬閘極條上分別形成一對第一間隙物與一對第二間隙物。在步驟S20中，移除第一擬閘極條而形成一第一凹槽。在步驟S22中，移除第二擬閘極條與位於其下方的第一介電層直到暴露出第二間隙物的側壁、半導體鰭片的部分以及絕緣體的部份而形成一第二凹槽。在步驟S24中，於第二凹槽內形成一第二介電層，以選擇性地覆蓋半導體鰭片被暴露出來的部分，其中第一介電層的厚度小於第二介電層的厚度。前述的第二介電層例如是透過原子層沉積（ALD）、化學氣相沉積（CVD）或物理氣相沉積（PVD）所形成。在步驟S26中，於第一凹槽內形成一第一閘極以及於第二凹槽內形成一第二閘極，以覆蓋第二介電層、第二間隙物被暴露出來的側壁以及絕緣體被暴露出來的部分。如圖1所示，第一擬閘極條的移除是在第二擬閘極條的移除之前進行。然而，移除第一擬閘極條與第二擬閘極條的順序並不限於此。
圖2A繪示為半導體元件於製作方法的不同階段中的一個階段的透視圖。在圖1的步驟S10與圖2A中，提供一基板200。於一實施例中，基板200包括一結晶矽基板(如晶圓)。基板200可依據設計需求而包括多種摻雜區(例如是p型基板或n型基板)。於其他實施例中，摻雜區可摻雜有p型與/或n型摻質。舉例來說，摻雜區可摻雜有p型摻質，例如是硼或二氟化硼（BF2）；而n型摻質，例如是磷、砷、與/或上述的組合。摻雜區可以被配置為n型的鰭式場效電晶體、p型鰭式場效電晶體或上述的組合。於其他實施例中，基板200可以由一些其它適合的元素半導體，如鑽石或鍺；適合的化合物半導體，如砷化鎵、碳化矽、砷化銦或磷化銦；或者適合的合金半導體，如碳化矽鍺 (silicon germanium carbide，SiGeC)、磷化砷鎵(gallium arsenic phosphide)或磷化銦鎵(gallium indium phosphide)所組成。
於一實施例中，於基板200上依序形成一接墊層202a與一遮罩層202b。接墊層202a例如是透過熱氧化製程所形成的一氧化矽薄膜。接墊層202可以作為基板200與遮罩層202b之間的黏著層。接墊層202a可以作為蝕刻遮罩層202b的蝕刻終止層。於至少一實施例中，遮罩層202b為一氮化矽層，其是通過低壓化學氣相沉積（PECVD）或電漿增強化學氣相沉積（PECVD）所形成。遮罩層202b於後續的微影製程中被用以作為一硬遮罩(hard mask)。接著，於遮罩層202b上形成具有一預定圖案的一圖案化光阻層204。
圖2B繪示為半導體元件於製作方法的不同階段中的一個階段的透視圖。在圖1的步驟S10以及圖2A至圖2B中，遮罩層202b與接墊層202a沒有被圖案化光阻層204所覆蓋的地方依序被蝕刻，而形成一圖案化遮罩層202b'以及一圖案化接墊層202a'，進而暴露出下面的基板200。以圖案化遮罩層202b'、圖案化接墊層202a'以及圖案化光阻層204為遮罩，基板200的部分被暴露出來且被蝕刻而形成多個溝渠206與多個半導體鰭片208。於基板200被圖案化之後，圖案化遮罩層202b'、圖案化接墊層202a'以及圖案化光阻層204覆蓋住半導體鰭片208。兩相鄰的溝渠206是透過一間隙S而隔開。舉例來說，位於溝渠206之間的間隙S可小於約30奈米。換言之，兩相鄰的溝渠206是由一對應的半導體鰭片208而隔開。
半導體鰭片208的高度與溝渠206的深度介於約5奈米至約500奈米之間。於形成溝渠206與半導體鰭片208之後，移除圖案化光阻層204。於一實施例中，可進行一清潔製程以移除半導體基板200a和半導體鰭片208的原生氧化物。清潔過程可以用氫氟酸稀釋溶液或其它適當的清洗液來進行。
圖2C繪示為半導體元件於製作方法的不同階段中的一個階段的透視圖。在圖1的步驟S12與圖2B至圖2C中，形成一絕緣材料210於基板200a上以覆蓋半導體鰭片208並且填滿溝渠206。除了半導體鰭片208，絕緣材料210更覆蓋圖案化接墊層202a'與圖案化遮罩層202b'。絕緣材料210可包括氧化矽、氮化矽、氧氮化矽、旋塗介電材料或低介電常數的介電材料。絕緣材料210可透過高密度電漿化學氣相沈積（HDP-CVD）、亞大氣壓化學氣相沈積（ASCVD）或旋轉塗佈來形成。
圖2D繪示為半導體元件於製作方法的不同階段中的一個階段的透視圖。在圖1的步驟S12中與圖2C至圖2D中，舉例而言，進行一化學機械研磨製程以移除絕緣材料210的一部分、圖案化遮罩層202b'和圖案化的接墊層202a'直到半導體鰭片208被暴露出來。如圖2D所示，於研磨絕緣材料210之後，研磨後的絕緣材料210的頂表面實質上與半導體鰭片208的頂表面T2共平面。
圖2E繪示為半導體元件於製作方法的不同階段中的一個階段的透視圖。在圖1的步驟S12中與圖2D至圖2E中，透過一蝕刻製程移除部分填充於溝渠206內已被研磨的絕緣材料210，以於基板200a上形成多個絕緣體210a，而半導體鰭片208位於兩相鄰的絕緣體210a之間。於一實施例中，蝕刻製程可以是採用氫氟酸（HF）的濕法蝕刻製程或者是乾式蝕刻製程。絕緣體210a的上表面T1低於半導體鰭片208的頂表面T2。換言之，半導體鰭片208突出於絕緣體210a的上表面T1，且半導體鰭片208的側壁SW因而暴露出來。半導體鰭片208的頂表面T2與絕緣體210a的上表面T1之間具有一高度差H，而高度差H介於約15奈米至約50奈米之間。
圖2F繪示為半導體元件於製作方法的不同階段中的一個階段的透視圖。在圖1的步驟S14與圖2E至圖2F中，於絕緣體210a形成之後，形成一第一介電層212以共形地覆蓋絕緣體210a的上表面T1、半導體鰭片208的頂表面T2以及半導體鰭片208的側壁SW。於一實施例中，第一介電層212可包括氧化矽、氮化矽、氧氮化物或高介電常數的介電材料。高介電常數的介電材料包括金屬氧化物。舉例來說，用於高介電常數的介電材料的金屬氧化物包括氧化物鋰、鈹、鎂、鈣、鍶、鈧、釔、鋯、鉿、鋁、鑭、鈰、鐠、釹、釤、銪、釓、鏑、鈥、鉺、銩、鐿、鑥、與/或上述的混合物。於一實施例中，第一介電層212為厚度為約0.2奈米至5奈米的高介電常數的介電層。第一介電層212可以透過合適的方法，例如是原子層沉積（ALD）、化學氣相沉積（CVD）、物理氣相沉積（PVD）、熱氧化或UV臭氧氧化來形成。第一介電層212足夠薄且具有良好的品質，可作為在短通道的鰭式場效電晶體的閘極介電層。
圖2G繪示為半導體元件於製作方法的不同階段中的一個階段的透視圖。在圖1的步驟S16與圖2F至圖2G中，於第一介電層212上形成至少一第一擬閘極條214a與至少一第二擬閘極條214b，其中第一擬閘極條214a及第二擬閘極條214b的長度方向D1與半導體鰭片208的長度方向D2不同。沿著長度方向D1，第一擬閘極條214a的一第一寬度W1小於第二擬閘極條214b的一第二寬度W2。第一擬閘極條214a與第二擬閘極條214b的長度方向D1例如是垂直於半導體鰭片208的長度方向D2。圖2G中的第一擬閘極條214a與第二擬閘極條214b的數量僅為示意，於其他實施例中，可根據實際的設計需求來形成兩個或更多的第一擬閘極條214a與第二擬閘極條214b。第一擬閘極條214a與第二擬閘極條214b包括含矽材料，例如是多晶矽、非晶矽或上述的組合。於一實施例中，第一擬閘極條214a的第一寬度W1介於5奈米至50奈米之間，而第二擬閘極條214b的第二寬度W2則大於50奈米。
在圖1的步驟S18與圖2G中，於形成第一擬閘極條214a與第二擬閘極條214b之後，於第一擬閘極條214a的側壁與第二擬閘極條214b的側壁上分別形成一對第一間隙物216a與一對第二間隙物216b。如圖2H所示，第一間隙物216a形成在第一介電層212上且沿著第一擬閘極條214a的側壁延伸，而第二間隙物216b形成在第一介電層212上且沿著第二擬閘極條214b的側壁延伸。第一間隙物216a與第二間隙物216b是由介電材料所形成，例如是氮化矽或碳氮氧化矽（SiCON）。第一間隙物216a與第二間隙物216b可包括單層或多層結構。由於第一間隙物216a是由第一擬閘極條214a隔開，因此第一間隙物216a之間的一第一間隙G1實質上等於第一擬閘極條214a的第一寬度W1。同樣地，第二間隙物216b之間的一第二間隙G2實質上等於第二擬閘極條214b的第二寬度W2。
圖2H繪示為半導體元件於製作方法的不同階段中的一個階段的透視圖。如圖2H所示，於第一介電層212上形成多個層間介電層218。層間介電層218的上表面實質上與第一擬閘極條214a的上表面以及第二擬閘極條214b的上表面實質上共平面。於其他實施例中，於層間介電層218形成以前，可以先進行一些製程（例如是第一介電層212的圖案化製程、鰭片凹槽(fin recessing)製程、半導體鰭片上的應變源極/汲極磊晶(strained source/drain epitaxial)製程以及矽化(silicidation)製程等）。上述製程的細節被省略。
圖2I至2J繪示為半導體元件於製作方法的不同階段的透視圖。在圖1的步驟S20及步驟S22與圖2H至圖2J中，移除第一擬閘極條214a與第二擬閘極條214b。於一實施例中，移除第一擬閘極條214a與第二擬閘極條214b的方法例如是一蝕刻製程。透過選擇適當的蝕刻液，層間介電層218、第一介電層212、第一間隙物216a以及第二間隙物216b在第一擬閘極條214a和第二擬閘極條214b的移除過程中便不會被顯著地損壞。於移除第一擬閘極條214a之後，第一間隙物216a之間形成一第一凹槽C1，而第一介電層212的部分因此而被暴露出來。半導體鰭片208對應第一凹槽C1的此部分(繪示在於圖2J的右側部分)仍然被第一介電層212所覆蓋。
如圖2J所示，移除第一介電層212的部分以及位於第二擬閘極條214b的部分絕緣體210a直到第二間隙物216b的側壁、半導體鰭片208的部分以及絕緣體210a的部分被暴露出來而形成第二凹槽C2。於第二凹槽C2的形成過程中，被第一凹槽C1所暴露出的第一介電層212例如是被良好地保護以免於被移除。於一實施例中，被第一凹槽C1所暴露出的第一介電層212可被光阻層所保護及覆蓋以免於被移除。
於第二凹槽C2的形成過程中，第一介電層212會被蝕刻且稍微過度蝕刻。於其他實施例中，於形成第二凹槽C2的過程中，絕緣體210a可以作為一蝕刻終止層，以便控制第二凹槽C2的輪廓。於第二凹槽C2形成之後，半導體鰭片208對應第二凹槽C2的部分(繪示在圖2J的左側部分)會被暴露出來。值得注意的是，沿著半導體鰭片208的長度方向D2，半導體鰭片208對應於第二凹槽C2的部份(繪示在圖2J的左側部分)具有較大尺寸，而半導體鰭片208對應於第一凹槽C1的部分(繪示在圖2J的右側部分)具有較小尺寸。
圖2K繪示為半導體元件於製作方法的不同階段中的一個階段的透視圖。在圖1的步驟S24與圖2J至圖2K中，於形成第二凹槽C2之後，於第二凹槽C2內形成一第二介電層220以選擇性地覆蓋住半導體鰭片208被暴露出來的部分，其中第一介電層212的厚度小於第二介電層220的厚度。第二介電層220選擇性地成長於半導體鰭片208被暴露出來的部分上，據此，形成在第二凹槽C2內的第二介電層220沒有完全覆蓋住絕緣體210a所被暴露出來的部分，而第二間隙物216b的側壁僅僅一部分與第二介電層220接觸。於一實施例中，第二介電層220可以包括氧化矽、氮化矽、氧氮化物或高介電常數的介電材料。高介電常數的介電材料包括金屬氧化物。舉例來說，用於高介電常數的介電材料的金屬氧化物包括氧化物鋰、鈹、鎂、鈣、鍶、鈧、釔、鋯、鉿、鋁、鑭、鈰、鐠、釹、釤、銪、釓、鏑、鈥、鉺、銩、鐿、鑥、與/或上述的混合物。於一實施例中，第二介電層220為一具有厚度在大約5奈米到50奈米的高介電常數的介電層。第二介電層220可透過合適的方法如熱氧化來形成。第二介電層220比第一介電層212更厚，適合用作在長通道的鰭式場效電晶體的閘極介電層。
如圖2K至圖2L所示，於第一凹槽C1內形成一第一閘極222a，並且於第二凹槽C2內形成一第二閘極222b以覆蓋第二介電層220、第二間隙物216b的側壁以及絕緣體210a被暴露出來的部分。第二介電層220配置於第二閘極222b與半導體鰭片208被暴露出的部分之間。第二介電層220不存在於第二閘極222b與第二間隙物216b之間。於一些實施例中，第一閘極222a與第二閘極222b可包括一層或多層結構。於一些實施例中，第一閘極222a與第二閘極222b可包括金屬，例如是鋁、銅、鎢、鈦、鉭、氮化鈦、鋁化鈦、氮化鋁鈦、氮化鉭、矽化鎳、矽化鈷、其他具有功函數且與基底材料相容的導電材料，或上述材料的組合。於一些實施例中，第一閘極222a與第二閘極222b的厚度例如是介於約30奈米至約60奈米之間。第一閘極222a與第二閘極222b可透過合適的方法，例如原子層沉積（ALD）、化學氣相沉積（CVD）、物理氣相沉積（PVD）、電鍍或上述製程的組合來形成。
於一實施例中，第一閘極222a的寬度W3為5奈米至50奈米，而第二閘極222b的寬度W4大於50奈米。與第一閘極222重疊且被第一閘極222a覆蓋的部分半導體鰭片208可作為一短通道鰭式場效電晶體的通道，而與第二閘極222b重疊且被第二閘極222b覆蓋的部分半導體鰭片208可作為長通道鰭式場效電晶體的通道。
如圖2G與圖2L所示，第一閘極222a的寬度W3、第一擬閘極條214a的寬度W1以及第一間隙物216a之間的第一間隙G1實質上相同(即W3=W1=G1)。第二閘極222b的寬度W4、第二擬閘極條214b的寬度W2以及第二間隙物216b之間的第二間隙G2實質上相同(即W4=W2=G2)。
在短通道的鰭式場效電晶體中(繪示於圖2L的右側部分)，較薄的第一介電層212被形成以用作閘極介電層；在長通道的鰭式場效電晶體中(繪示於圖2L的左側部分)，較薄的第一介電層212被移除，且被選擇性地成長以及較厚的第二介電層220所取代。由於第二介電層220具有較大的厚度，半導體鰭片208被暴露出來的部分會被良好地包覆以防止第二閘極222b的漏電路徑(leakage path)和擠出路徑(extrusion path)的形成。因此，閘極置換製程的製程裕度可被放大。據此，可提高半導體元件的良率(yield)和可靠性。
根據本發明的一些實施例，鰭式場效應晶體的製造方法包括至少以下步驟。圖案化基板以形成多個位於基板內的溝渠以及位於溝渠之間的半導體鰭片。於溝渠內形成多個絕緣體。形成第一介電層以覆蓋半導體鰭片與絕緣體。於第一介電層上形成擬閘極條，擬閘極條的長度方向不同於半導體鰭片的長度方向。於擬閘極條的多個側壁上形成一對間隙物。移除擬閘極條與位於擬閘極條下方的第一介電層直到間隙物的多個側壁、半導體鰭片的一部分以及絕緣體的多個部分被暴露出來。形成第二介電層以選擇性地覆蓋半導體鰭片被暴露出來的部分，其中第一介電層的厚度小於第二介電層的厚度。於間隙物之間形成閘極以覆蓋第二介電層、間隙物被暴露出的側壁以及絕緣體被暴露出來的部分。
在所述鰭式場效應晶體的製造方法中，於擬閘極條移除之前，於第一介電層上形成間隙物，且間隙物沿著擬閘極條的側壁延伸。
在所述鰭式場效應晶體的製造方法中，移除擬閘極條與第一介電層以形成一位於間隙物之間的凹槽，而第二介電層形成於凹槽所暴露出的半導體鰭片的部分上。
在所述鰭式場效應晶體的製造方法中，擬閘極條、第一介電層以及部分的絕緣體是在形成凹槽的一蝕刻製程中被移除。
在所述鰭式場效應晶體的製造方法中，第二介電層是透過熱氧化而形成。
在所述鰭式場效應晶體的製造方法中，具有寬度大於50奈米的閘極形成於間隙物之間以覆蓋第二介電層、間隙物被暴露出的側壁以及絕緣體被暴露出的部分。
在所述鰭式場效應晶體的製造方法更包括於移除擬閘極條之前，形成一源極與一汲極於半導體鰭片上。
根據本發明的一些實施例，半導體元件的製作方法至少包括以下步驟。圖案化基板以形成多個位於基板內的溝渠以及多個位於溝渠之間的半導體鰭片。形成多個絕緣體於溝渠內。形成第一介電層以覆蓋半導體鰭片與絕緣體。形成至少一第一擬閘極條與至少一第二擬閘極條於第一介電層上，其中第一擬閘極條與第二擬閘極條的長度方向不同於半導體鰭片的長度方向，且第一擬閘極條的寬度小於第二擬閘極條的寬度。分別形成一對第一間隙物以及一對第二間隙物於第一擬閘極條的多個側壁上以及第二擬閘極條的多個側壁上。移除第一擬閘極條以形成第一凹槽。移除第二擬閘極條與位於第二擬閘極條下方的第一介電層直到第二間隙物的多個側壁、半導體鰭片的一部分以及絕緣體的多個部分被暴露出來，而形成第二凹槽。形成第二介電層於第二凹槽內以選擇性地覆蓋半導體鰭片被暴露出來的部分，其中第一介電層的厚度小於第二介電層的厚度。形成第一閘極於第一凹槽內。形成第二閘極於第二凹槽內以覆蓋第二介電層，第二間隙物被暴露出來的側壁以及絕緣體被暴露出來的部分。
在所述半導體元件的製造方法中，第一擬閘極條與第二擬閘極條於同一步驟中移除。
在所述半導體元件的製造方法中，形成第一擬閘極條與第二擬閘極條的方法，包括：形成導電層於第一介電層上；以及圖案化該導電層以形成具有第一寬度的第一導電條以及具有第二寬度的第二導電條，第一寬度小於第二寬度。
在所述半導體元件的製造方法中，第一間隙物形成於第一介電層上且沿著第一擬閘極條的側壁延伸，第二間隙物形成於第一介電層上且沿著第二擬閘極條的側壁延伸。
在所述半導體元件的製造方法中，移除第二擬閘極條，位於第二擬閘極條下方的第一介電層以及部分的絕緣體是在形成第二凹槽的蝕刻製程中。
在所述半導體元件的製造方法中，第二介電層是透過熱氧化而形成。具有寬度介於5奈米至50奈米的第一閘極形成於第一凹槽內，而具有寬度大於50奈米的第二閘極形成於第二凹槽內，以覆蓋第二介電層、第二間隙物的被暴露出來的側壁以及絕緣體被暴露出來的部分。
在所述半導體元件的製造方法中，半導體元件的製作方法，更包括:於移除第一擬閘極條與第二擬閘極條之前，形成多個源極與多個汲極於半導體鰭片上。
根據本發明的其他實施例，半導體元件包括一基板、多個絕緣體、一第一介電層、一對第一間隙物、一第一閘極、一對第二間隙物、一第二介電層和一第二閘極。基板包括多個溝渠以及多個位於溝渠之間的半導體鰭片。絕緣體位於溝渠內。第一介電層覆蓋半導體鰭片與絕緣體，且暴露出半導體鰭片的一部分以及絕緣體的部分。第一間隙物配置於第一介電層上。第一閘極配置於第一介電層上且位於第一間隙物之間。第二間隙物配置於第一介電層上。第二介電層配置於第二間隙物之間，其中第二介電層選擇性覆蓋半導體鰭片被暴露出來的部分，而第一介電層的厚度小於第二介電層的厚度。第二閘極配置於第二間隙物之間以覆蓋第二介電層、第二間隙物被暴露出的側壁以及絕緣體被暴露出來的部分，其中第一閘極的寬度小於第二閘極的寬度。
在所述半導體元件中，第一介電層的厚度介於0.2奈米至5奈米之間，且第二介電層的厚度介於5奈米至50奈米之間。
在所述半導體元件中，第一閘極的寬度介於5奈米至50奈米之間，而第二閘極的寬度大於50奈米。
在所述半導體元件中，第二閘極的寬度實質上等於第二間隙物之間的一間隙。
在所述半導體元件中，第二介電層配置於半導體鰭片被暴露出出來的部分與第二閘極之間。
以上概述了數個實施例的特徵，使本領域具有通常知識者可更佳了解本發明的態樣。本領域具有通常知識者應理解，其可輕易地使用本發明作為設計或修改其他製程與結構的依據，以實行本文所介紹的實施例的相同目的及/或達到相同優點。本領域具有通常知識者還應理解，這種等效的配置並不悖離本發明的精神與範疇，且本領域具有通常知識者在不悖離本發明的精神與範疇的情況下可對本文做出各種改變、置換以及變更。
200、200a‧‧‧基板 202a‧‧‧接墊層 202a’‧‧‧圖案化接墊層 202b‧‧‧遮罩層 202b’‧‧‧圖案化遮罩層 204‧‧‧圖案化光阻層 206‧‧‧溝渠 208‧‧‧半導體鰭片 210‧‧‧絕緣材料 210a‧‧‧絕緣體 212‧‧‧第一介電層 214a‧‧‧第一擬閘極條 214b‧‧‧第二擬閘極條 216a‧‧‧第一間隙物 216b‧‧‧第二間係物 218‧‧‧層間介電層 220‧‧‧第二介電層 222a‧‧‧第一閘極 222b‧‧‧第二閘極 C1‧‧‧第一凹槽 C2‧‧‧第二凹槽 D1、D2‧‧‧長度方向 G1‧‧‧第一間隙 G2‧‧‧第二間隙 H‧‧‧高度差 S‧‧‧間隙 T1‧‧‧上表面 T2‧‧‧頂表面 SW‧‧‧側壁 W1‧‧‧第一寬度 W2‧‧‧第二寬度 W3、W4‧‧‧寬度 S10、S12、S14、S16、S18、S20、S22、S24、S26‧‧‧步驟
圖1繪示為根據一些實施例的一種半導體元件的製作方法的流程圖。 圖2A至圖2L是根據一些實施例的一種半導體元件的製造方法的透視圖。
S10、S12、S14、S16、S18、S20、S22、S24、S26‧‧‧步驟

Claims (1)

  1. 一種鰭式場效電晶體的製作方法，包括： 圖案化一基板以形成多個位於該基板內的溝渠以及位於該些溝渠之間的一半導體鰭片； 於該些溝渠內形成多個絕緣體； 形成一第一介電層以覆蓋該半導體鰭片與該些絕緣體； 於該第一介電層上形成一擬閘極條，該擬閘極條的長度方向不同於該半導體鰭片的長度方向； 於該擬閘極條的多個側壁上形成一對間隙物； 移除該擬閘極條與位於該擬閘極條下方的該第一介電層直到該些間隙物的多個側壁、該半導體鰭片的一部分以及該些絕緣體的多個部分被暴露出來； 形成一第二介電層以選擇性地覆蓋該半導體鰭片被暴露出來的該部分，其中該第一介電層的厚度小於該第二介電層的厚度；以及 於該些間隙物之間形成一閘極以覆蓋該第二介電層、該些間隙物被暴露出的該些側壁以及該些絕緣體被暴露出來的部分。
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