TWI711086B - 用於製造鰭狀場效電晶體的方法、半導體裝置及用於製造其的方法 - Google Patents

用於製造鰭狀場效電晶體的方法、半導體裝置及用於製造其的方法 Download PDF

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TWI711086B
TWI711086B TW105134689A TW105134689A TWI711086B TW I711086 B TWI711086 B TW I711086B TW 105134689 A TW105134689 A TW 105134689A TW 105134689 A TW105134689 A TW 105134689A TW I711086 B TWI711086 B TW I711086B
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dielectric layer
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TW201729290A (zh
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張哲誠
林志翰
曾鴻輝
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台灣積體電路製造股份有限公司
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Abstract

本發明實施例提供一種用於製造鰭式場效電晶體的方 法，包括以下步驟。圖案化基底以形成溝渠，並且在溝渠之間形成半導體鰭片。在溝渠中形成絕緣體，並且形成介電層以覆蓋半導體鰭片和絕緣體。在介電層上形成虛擬閘極帶。間隙壁形成在虛擬閘極帶的側壁上。移除虛擬閘極帶和在下方的介電層，直至暴露出間隙壁、部分半導體鰭片和絕緣體的部分側壁。選擇性地形成第二介電層以覆蓋半導體鰭片的暴露部分，其中介電層的厚度小於第二介電層的厚度。在間隙壁之間形成閘極以覆蓋第二介電層、間隙壁的側壁和絕緣體的暴露部分。

Description

用於製造鰭狀場效電晶體的方法、半導體裝置 及用於製造其的方法
本發明實施例是有關於一種用於製造半導體裝置的方法，且特別是有關於一種用於製造鰭狀場效電晶體的方法。
隨著半導體裝置的尺寸不斷縮小，已經開發出諸如鰭式場效電晶體(FinFET)的三維多閘極結構以代替平面的互補金屬氧化物半導體(CMOS)裝置。FinFET的結構特徵是從基底的表面豎直向上延伸的基於矽的鰭片，並且包圍由鰭片形成的導電通道的閘極進一步對通道提供更好的電性控制。
對於短通道(即通道長度小於50nm)FinFET的閘極替換製程來說，需要蝕刻掉覆蓋基於矽的鰭片的部分氧化層並且以後續沉積的高k介電層代替之。然而，氧化層的高蝕刻量造成後續形成的金屬閘極的漏電路徑和擠壓路徑(extrusion path)。
在本發明的一實施例中，一種用於製造鰭式場效電晶體(FinFET)的方法，包括：圖案化基底以在基底中形成多個溝渠，並且在溝渠之間形成半導體鰭片；在溝渠中形成多個絕緣體；形成介電層以覆蓋半導體鰭片和絕緣體；在介電層上形成虛擬閘極帶，虛擬閘極帶的長度方向與半導體鰭片的長度方向不同；在虛擬閘極帶的側壁上形成一對間隙壁；移除虛擬閘極帶並且減薄在下方的介電層以在一對間隙壁之間形成減薄部分；以及在一對間隙壁之間形成閘極以覆蓋減薄部分和一對間隙壁的側壁。
S10、S12、S14、S16、S18、S20、S22、S24、S26:步驟
200、200a:基底
202a、202a’:墊層
202b、202b’:罩幕層
204:光阻層
206:溝渠
208:鰭片
210:絕緣材料
210a:絕緣體
212:介電層
212a:減薄部分
214a:第一虛擬閘極帶
214b:第二虛擬閘極帶
216a:第一間隙壁
216b:第二間隙壁
218:層間介電層
222a:第一閘極
222b:第二閘極
224a:第一覆蓋層
224b:第二覆蓋層
C1:第一腔體
C2:第二腔體
D1、D2:長度方向
G1、G2:間隙
GR1:第一閘極凹口
GR2:第二閘極凹口
H:高度差
R:凹口
S:間隔
SW:側壁
T1、T2:頂部表面
W1、W2、W3、W4:寬度
圖1是根據一些實施例繪示用於製造半導體裝置的方法的流程圖。
圖2A至圖2K是根據一些實施例的用於製造半導體裝置的方法的透視圖。
圖3至圖5是根據一些實施例的半導體裝置的截面圖。
以下揭露內容提供用於實施所提供的標的之不同特徵的許多不同實施例或實例。以下所描述的構件及配置的具體實例是為了以簡化的方式傳達本揭露為目的。當然，這些僅僅為實例而非用以限制。舉例來說，於以下描述中，在第二特徵上方或在第 二特徵上形成第一特徵可包括第一特徵與第二特徵形成為直接接觸的實施例，且亦可包括第一特徵與第二特徵之間可形成有額外特徵，使得第一特徵與第二特徵可不直接接觸的實施例。此外，本揭露在各種實例中可重複使用元件符號及/或字母。元件符號的重複使用是為了簡單及清楚起見，且並不表示所欲討論的各個實施例及/或配置本身之間的關係。
另外，為了易於描述附圖中所繪示的一個構件或特徵與另一組件或特徵的關係，本文中可使用例如「在...下」、「在...下方」、「下部」、「在...上」、「在...上方」、「上部」及類似術語的空間相對術語。除了附圖中所繪示的定向之外，所述空間相對術語意欲涵蓋元件在使用或操作時的不同定向。設備可被另外定向(旋轉90度或在其他定向)，而本文所用的空間相對術語相應地作出解釋。
本發明的實施例描述了包括至少一個長通道FinFET和至少一個短通道FinFET的半導體裝置的示例性製造過程。在本發明的某些實施例中，半導體裝置可以形成在塊狀矽基底上。但是可選擇地，半導體裝置可以形成在絕緣體上矽(SOI)基底或絕緣體上鍺(GOI)基底上。另外，根據實施例，矽基底可以包括其他導電層或其他半導體元件，例如電晶體、二極體等。然而，本文所記載的實施例並不限於此。
參照圖1，根據本發明的一些實施例繪示用於製造半導體裝置的方法的流程圖。製造方法至少包括步驟S10、步驟S12、步 驟S14、步驟S16、步驟S18、步驟S20、步驟S22、步驟S24以及步驟S26。首先，在步驟S10中，提供基底，且接著圖案化基底以形成多個溝渠以及在溝渠之間的多個半導體鰭片。在步驟S12中，在溝渠中形成多個絕緣體。舉例來說，此絕緣體為用於隔離半導體鰭片的淺溝渠隔離(STI)結構。在步驟S14中，形成介電層以覆蓋半導體鰭片和絕緣體。在步驟S16中，在介電層上形成至少一個第一虛擬閘極帶和至少一個第二虛擬閘極帶，其中，第一和第二虛擬閘極帶的長度方向不同於半導體鰭片的長度方向，並且第一虛擬閘極帶的寬度小於第二虛擬閘極帶的寬度。第一虛擬閘極帶和第二虛擬閘極帶例如是多晶矽帶等導電帶。在步驟S18中，在第一虛擬閘極帶和第二虛擬閘極帶的側壁上分別形成一對第一間隙壁和一對第二間隙壁。在步驟S20中，移除第一虛擬閘極帶，並且減薄下面的介電層以在一對第一間隙壁之間形成減薄部分。在步驟S22中，移除第二虛擬閘極帶。在步驟S24中，第一閘極形成在一對第一間隙壁之間以覆蓋減薄部分和第一間隙壁的側壁。在步驟S26中，第二閘極形成在一對第二間隙壁之間以覆蓋介電層和第二間隙壁的側壁。
如圖1所示，在移除第二虛擬閘極帶之前先移除第一虛擬閘極帶。然而，第一虛擬閘極帶(步驟S20)和第二虛擬閘極帶(步驟S22)的移除順序在本發明實施例中不做限定。舉例來說，第一虛擬閘極帶和第二虛擬閘極帶可以在相同的製程中移除。相似地，第一閘極(步驟S24)和第二閘極(步驟S26)的形成順序 在本發明實施例中不做限制。舉例來說，第一閘極和第二閘極可以通過相同的製程形成。
圖2A是半導體裝置製造方法的一個階段的半導體裝置的透視圖。在圖1的步驟S10中，並且如圖2A所示，提供基底200。在一個實施例中，基底200包括晶體矽基底(舉例來說，晶圓)。基底200根據設計要求可以包括不同的摻雜區域(舉例來說，p型基底或n型基底)。在一些實施例中，摻雜區域可以摻雜有p型及/或n型摻雜劑。舉例來說，摻雜區域可以摻雜有諸如硼或BF2的p型摻雜劑、諸如磷或砷的n型摻雜劑、及/或它們的組合。摻雜區域可以配置用於n型FinFET、p型FinFET或它們的組合。在一些可選實施例中，基底200可以由一些諸如金剛石或鍺的其他合適的元素半導體、諸如砷化鎵、碳化矽、砷化銦、或磷化銦的合適的化合物半導體、或者諸如碳化矽鍺、磷化鎵砷或磷化銦鎵的合適的合金半導體製成。
在一個實施例中，墊層202a和罩幕層202b順序形成在基底200上。墊層202a可以是例如通過熱氧化製程形成的氧化矽薄膜。墊層202a可以作為基底200與罩幕層202b之間的黏合層。墊層202a還可以作為用於蝕刻罩幕層202b的蝕刻停止層。在至少一個實施例中，罩幕層202b例如是通過低壓化學汽相沉積(LPCVD)或電漿增強化學汽相沉積(PECVD)形成的氮化矽層。罩幕層202b在後續的微影製程過程中作為硬罩幕使用。然後，在罩幕層202b上形成具有預定圖案的圖案化的光阻層204。
圖2B是半導體裝置製造方法的一個階段的半導體裝置的透視圖。在圖1的步驟S10中，並且如圖2A至圖2B所示，依序蝕刻未被圖案化的光阻層204覆蓋的罩幕層202b和墊層202a以形成圖案化的罩幕層202b’和圖案化的墊層202a’，以便暴露下層的基底200。通過使用圖案化的罩幕層202b’、圖案化的墊層202a’以及圖案化的光阻層204作為罩幕，暴露和蝕刻部分基底200以形成溝渠206和半導體鰭片208。在圖案化基底200以後，半導體鰭片208被圖案化的罩幕層202b’、圖案化的墊層202a’、以及圖案化的光阻層204覆蓋。兩個相鄰的溝渠206通過間隔S間隔開。舉例來說，在溝渠206之間的間隔S可以小於約30nm。換句話說，兩個相鄰的溝渠206通過相應的半導體鰭片208間隔開。
半導體鰭片208的高度和溝渠206的深度範圍為約5nm至約500nm。在形成溝渠206和半導體鰭片208後，移除圖案化的光阻層204。在一個實施例中，可以執行清洗製程以移除半導體基底200a和半導體鰭片208的原生氧化物。清洗製程可以使用稀釋的氫氟(DHF)酸或其他合適的清洗溶液執行。
圖2C是半導體裝置製造方法的一個階段的半導體裝置的透視圖。在圖1的步驟S12中，並且如圖2B至圖2C所示，在基底200a上形成絕緣材料210以覆蓋半導體鰭片208並填充溝渠206。除半導體鰭片208以外，絕緣材料210進一步覆蓋圖案化的墊層202a’和圖案化的罩幕層202b’。絕緣材料210可以包括氧化矽、氮化矽、氮氧化矽、旋塗介電材料、或低k介電材料。絕緣 材料210可以通過高密度電漿化學汽相沉積(HDP-CVD)、次大氣壓CVD(SACVD)或通過旋塗形成。
圖2D是半導體裝置製造方法的一個階段的半導體裝置的透視圖。在圖1的步驟S12中，並且如圖2C至圖2D所示，例如執行化學機械研磨製程以移除部分絕緣材料210、圖案化的罩幕層202b’和圖案化的墊層202a’，直至暴露出半導體鰭片208。如圖2D所示，在研磨絕緣材料210後，經研磨的絕緣材料210的頂部表面實質上與半導體鰭片的頂部表面T2共面。
圖2E是半導體裝置製造方法的一個階段的半導體裝置的透視圖。在圖1的步驟S12中，並且如圖2D至圖2E所示，通過蝕刻製程部分移除填充在溝渠206中的經研磨的絕緣材料210，使得絕緣體210a形成在基底200a上並且每個絕緣體210a位於兩相鄰的半導體鰭片208之間。在一個實施例中，蝕刻製程可以是使用氫氟酸(HF)的濕蝕刻製程或者乾蝕刻製程。絕緣體210a的頂部表面T1低於半導體鰭片208的頂部表面T2。換句話說，半導體鰭片208從絕緣體210a的頂部表面T1突出，並且因此暴露出來半導體鰭片208的側壁SW。鰭片208的頂部表面T2與絕緣體210a的頂部表面T1之間的高度差為H，並且此高度差H的範圍為約15nm至約50mm。
圖2F是半導體裝置製造方法的一個階段的半導體裝置的透視圖。在圖1的步驟S14中，並且如圖2E至圖2F所示，在絕緣體210a形成後，形成介電層212以共形地覆蓋絕緣體210a的 頂部表面T1、半導體鰭片208的頂部表面T2以及半導體鰭片208的側壁SW。在一個實施例中，介電層212可以包括氧化矽、氮化矽、氮氧化矽或高k介電材料。高k介電材料包括金屬氧化物。用於高k介電材料的金屬氧化物的實例包括Li、Be、Mg、Ca、Sr、Sc、Y、Zr、Hf、Al、La、Ce、Pr、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb、Lu的氧化物及/或它們的混合物。在一個實施例中，介電層212為厚度在約5nm至50nm範圍內的高k介電層。介電層212可以通過諸如原子層沉積(ALD)、化學汽相沉積(CVD)、物理汽相沉積(PVD)、熱氧化或紫外具氧氧化的合適的製程形成。介電層212足夠厚並且具有良好的品質以在長通道FinFET中作為閘極介電層使用。
圖2G是半導體裝置製造方法的一個階段的半導體裝置的透視圖。在圖1的步驟S16中，並且如圖2F至圖2G所示，在介電層212上形成至少一個第一虛擬閘極帶214a和至少一個第二虛擬閘極帶214b，其中第一虛擬閘極帶214a和第二虛擬閘極帶214b的長度方向D1與半導體鰭片208的長度方向D2不同。沿長度方向D1，第一虛擬閘極帶214a的第一寬度W1小於第二虛擬閘極帶214b的第二寬度W2。舉例來說，第一虛擬閘極帶214a和第二虛擬閘極帶214b的長度方向D1垂直於半導體鰭片208的長度方向D2。圖2G中繪示的第一虛擬閘極帶214a和第二虛擬閘極帶214b的數量僅是為了說明，在一些可選實施例中，根據實際設計要求，可以形成兩個或更多的第一虛擬閘極帶214a和第二虛擬閘 極帶214b。第一虛擬閘極帶214a和第二虛擬閘極帶214b包括含矽材料，例如多晶矽、非晶矽或它們的組合。在一個實施例中，第一虛擬閘極帶214a的第一寬度W1的範圍為5nm至50nm，並且第二虛擬閘極帶214b的第二寬度W2大於50nm。
在圖1的步驟18中，並且如圖2G所示，在第一虛擬閘極帶214a和第二虛擬閘極帶214b形成後，一對第一間隙壁216a和一對第二間隙壁216b分別形成在第一虛擬閘極帶214a和第二虛擬閘極帶214b的側壁上。如圖2H所示，第一間隙壁216a形成在介電層212上，並且沿第一虛擬閘極帶214a的側壁延伸，而第二間隙壁216b形成在介電層212上，並且沿第二虛擬閘極帶214b的側壁延伸。第一間隙壁216a和第二間隙壁216b由諸如氮化矽或SiCON的介電材料形成。第一間隙壁216a和第二間隙壁216b可以包括單層或多層結構。由於一對第一間隙壁216a通過第一虛擬閘極帶214a間隔開，該對第一間隙壁216a之間的第一間隙G1實質上等於第一虛擬閘極帶214a的第一寬度W1。相似地，該對第二間隙壁216b之間的第二間隙G2實質上等於第二虛擬閘極帶214b的第二寬度W2。
圖2H是半導體裝置製造方法的一個階段的半導體裝置的透視圖。如圖2H所示，形成層間介電層218以覆蓋未被閘極堆疊結構覆蓋的介電層212。層間介電層218的頂部表面實質上與第一虛擬閘極帶214a和第二虛擬閘極帶214b的頂部表面共面。在一些實施例中，在形成層間介電層218之前，可以先執行一些製 程(舉例來說，介電層212的圖案化製程、鰭片凹口製程、在半導體鰭片上的應力源極/汲極磊晶製程、矽化製程等)。省略描述上述製程的細節。
圖21是半導體裝置製造方法的一個階段的半導體裝置的透視圖。在圖1的步驟S20、S22中，並且如圖2H至圖2I所示，移除第一虛擬閘極帶214a和第二虛擬閘極帶214b。舉例來說，在一個實施例中，通過蝕刻製程移除第一虛擬閘極帶214a和第二虛擬閘極帶214b。通過選擇適當的蝕刻劑，可以移除第一虛擬閘極帶214a和第二虛擬閘極帶214b而不會明顯地破壞層間介電層218、介電層212、第一間隙壁216a和第二間隙壁216b。在移除第一虛擬閘極帶214a和第二虛擬閘極帶214b後，在該對第一間隙壁216a之間形成第一腔體C1並且在該對第二間隙壁216b之間形成第二腔體C2。換句話說，部分介電層212通過第一腔體C1和第二腔體C2暴露出來。
圖2J是半導體裝置製造方法的一個階段的半導體裝置的透視圖。在圖1的步驟S20、S22中，並且如圖2J所示，在形成第一腔體C1和第二腔體C2後，部分移除通過第一腔體C1暴露的部分介電層212。換句話說，減薄通過第一腔體C1暴露的部分介電層212以在該對第一間隙壁216a之間形成減薄部分212a。在減薄部分212a的形成過程中，執行額外的蝕刻製程，並且通過第二腔體C2暴露的部分介電層212可以被良好保護以不被減薄。在一個實施例中，通過第二腔體C2暴露的部分介電層212可以由光 阻層保護和覆蓋以避免被移除。在一些實施例中，減薄部分212a的剩餘厚度範圍為0.2nm至5nm，並且被該對第一間隙壁216a和該對第二間隙壁216b覆蓋的介電層的厚度範圍為5nm至50nm。如圖2J所示，減薄部分212a包括在第一腔體C1下方的凹口R。介電層212的減薄部分212a足夠薄並且具有良好的品質以在短通道FinFET中作為閘極介電層使用。
圖2K是半導體裝置製造方法的一個階段的半導體裝置的透視圖。在圖1的步驟S24、S26中，並且如圖2J至圖2K所示，在形成介電層212的減薄部分212a後，在第一腔體C1中形成第一閘極222a並且在第二腔體C2中形成第二閘極222b。舉例來說，第一閘極222a和第二閘極222b可以通過相同的製程形成。第一閘極222a覆蓋通過第一腔體C1暴露的減薄部分212a，並且第二閘極222b覆蓋通過第二腔體C2暴露的部分介電層212。如圖2K所示，凹口R的延伸方向實質上與第一閘極222a的長度方向D1平行。
在一個實施例中，第一閘極222a的寬度W3的範圍為5nm至50nm，並且第二閘極222b的寬度W4大於50nm。半導體鰭片208中與第一閘極222a重疊並被第一閘極222a覆蓋的部分作為短通道FinFET的通道；並且半導體鰭片208中與第二閘極222b重疊並被第二閘極222b覆蓋的部分作為長通道FinFET的通道。
如圖2G和圖2K所示，第一閘極222a的寬度W3、第一虛擬閘極帶214a的寬度W1以及在該對第一間隙壁216a之間的第 一間隙G1實質上相等(即，W3=W1=G1)。第二閘極222b的寬度W4、第二虛擬閘極帶214b的寬度W2以及該對第二間隙壁216b之間的第二間隙G2實質上相等(即，W4=W2=G2)。
圖3繪示了沿圖2K中半導體裝置的截面A-A’的截面圖。參照圖2K和圖3，第一閘極222a和第二閘極222b的頂部表面與第一間隙壁216a、第二間隙壁216b以及層間介電層218的頂部表面實質上共面。在一些實施例中，如圖4和圖5所示，閘極堆疊結構可以具有其他合適的修改。
如圖4所示，在一些實施例中，形成第一覆蓋層224a和第二覆蓋層224b以覆蓋第一閘極222a和第二閘極222b。第一覆蓋層224a和第二覆蓋層224b可以進一步覆蓋第一間隙壁216a、第二間隙壁216b和層間介電層218的頂部表面。如圖5所示，在一些可選實施例中，部分地移除第一閘極222a和第二閘極222b從其頂部表面，以便分別在該對第一間隙壁216a之間形成第一閘極凹口GR1，並且在該對第二間隙壁216b之間形成第二閘極凹口GR2。然後，分別在第一閘極凹口GR1和第二閘極凹口GR2中形成第一覆蓋層224a和第二覆蓋層224b。需要注意的是，第一閘極凹口GR1和第二閘極凹口GR2的頂部表面與第一間隙壁216a、第二間隙壁216b以及層間介電層218的頂部表面例如實質上共面。
在短通道FiaFET(繪示於圖2K和圖3至圖5的右側部分中)中，形成介電層212的減薄部分212a以作為閘極介電層使 用；在長通道FinFET(繪示於圖2K和圖3至圖5的左側部分中)中，在半導體鰭片208和第二閘極222b之間的介電層212作為閘極介電層使用。由於介電層212良好保護半導體鰭片208，可以防止第一閘極222a和第二閘極222b的漏電路徑和擠壓路徑。相應地，增加閘極替換製程的製程裕度。因此，提高了半導體裝置的產量和可靠性。
根據本發明的一些實施例，用於製造FinFET的方法至少包括以下步驟。圖案化基底以在基底中形成溝渠並且在溝渠之間形成半導體鰭片。在溝渠中形成多個絕緣體，並且形成介電層以覆蓋半導體鰭片和絕緣體。在介電層上形成虛擬閘極帶，其中虛擬閘極帶的長度方向不同於半導體鰭片的長度方向。在虛擬閘極帶的側壁上形成一對間隙壁。移除虛擬閘極帶並且減薄在下方的介電層以在一對間隙壁之間形成減薄部分。在一對間隙壁之間形成閘極以覆蓋減薄部分和一對間隙壁的側壁。
根據本發明的可選實施例，一種用於製造半導體裝置的方法至少包括以下步驟。圖案化基底以在基底中形成多個溝渠並且在溝渠之間形成多個半導體鰭片。在溝渠中形成多個絕緣體。形成介電層以覆蓋半導體鰭片和絕緣體。在介電層上形成至少一個第一虛擬閘極帶和至少一個第二虛擬閘極帶，其中第一和第二虛擬閘極帶的長度方向不同於半導體鰭片的長度方向，並且第一虛擬閘極帶的寬度小於第二虛擬閘極帶的寬度。分別在第一和第二虛擬閘極帶的側壁上形成一對第一間隙壁和一對第二間隙壁。 移除第一虛擬閘極帶並且減薄在下方的介電層以在一對第一間隙壁之間形成減薄部分。移除第二虛擬閘極帶。在一對第一間隙壁之間形成第一閘極以覆蓋減薄部分和第一間隙壁的側壁。在一對第二間隙壁之間形成第二閘極以覆蓋介電層和第二間隙壁的側壁。
根據本公開的再一可選實施例，半導體裝置包括基底、多個絕緣體、介電層、第一閘極、一對第一間隙壁、第二閘極以及一對第二間隙壁。基底包括多個溝渠和位於溝渠之間的多個半導體鰭片。絕緣體設置在溝渠中。介電層覆蓋半導體鰭片和絕緣體並包括減薄部分。第一閘極設置在減薄部分上。一對第一間隙壁設置在第一閘極的側壁上。第二閘極設置在介電層上。一對第二間隙壁設置在第二閘極的側壁上，其中，第一和第二閘極的長度方向不同於半導體鰭片的長度方向，並且第一閘極的寬度小於第二閘極的寬度。
根據本發明的一個實施例，在移除虛擬閘極帶之前，一對間隙壁形成在介電層上並且沿虛擬閘極帶的側壁延伸。
根據本發明的一個實施例，減薄部分的厚度範圍為0.2nm至5nm，並且被一對間隙壁覆蓋的介電層的厚度範圍為5nm至50nm。
根據本發明的一個實施例，減薄部分包括凹口，並且凹口通過蝕刻製程形成。
根據本發明的一個實施例，具有5nm至50nm寬度的閘 極形成在一對間隙壁之間，以覆蓋減薄部分和一對間隙壁的側壁。
根據本發明的一個實施例，進一步包括：形成覆蓋層以覆蓋閘極和一對間隙壁。
根據本發明的一個實施例，進一步包括：部分地移除閘極以在一對間隙壁之間形成閘極凹口；以及在閘極凹口中形成覆蓋層以覆蓋閘極。
根據本發明的一個實施例，第一和第二虛擬閘極帶在相同的製程中移除。
根據本發明的一個實施例，形成一對第一間隙壁以覆蓋介電層並沿第一虛擬閘極帶的側壁延伸，並且形成一對第二間隙壁以覆蓋介電層並沿第二虛擬閘極帶的側壁延伸。
根據本發明的一個實施例，減薄部分的厚度範圍為0.2nm至5nm，並且被一對第一和第二間隙壁覆蓋的介電層的厚度範圍為5nm至50nm。
根據本發明的一個實施例，具有5nm至50nm寬度的第一閘極形成在一對第一間隙壁之間以覆蓋減薄部分，並且寬度大於50nm的第二閘極形成在一對第二間隙壁之間以覆蓋介電層。
根據本發明的一個實施例，進一步包括：形成第一覆蓋層以覆蓋第一閘極和一對第一間隙壁；以及形成第二覆蓋層以覆蓋第二閘極和一對第二間隙壁。
根據本發明的一個實施例，進一步包括：部分地移除第一閘極和第二閘極以分別在一對第一間隙壁之間形成第一閘極凹 口，並且在一對第二間隙壁之間形成第二閘極凹口；以及在第一閘極凹口和第二閘極凹口中分別形成第一覆蓋層和第二覆蓋層。
根據本發明的一個實施例，減薄部分的厚度範圍為0.2nm至5nm，並且被第一間隙壁、第二間隙壁和第二閘極覆蓋的介電層的厚度範圍為5nm至50nm。
根據本發明的一個實施例，第一閘極的寬度範圍為5nm至50nm，並且第二閘極的寬度大於50nm。
根據本發明的一個實施例，凹口沿第一閘極的長度方向延伸。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
S10、S12、S14、S16、S18、S20、S22、S24、S26:步驟

Claims (10)

  1. 一種用於製造鰭式場效電晶體的方法，包括：圖案化基底，以在所述基底中形成多個溝渠並且在所述溝渠之間形成半導體鰭片；在所述溝渠中形成多個絕緣體；形成介電層以覆蓋所述半導體鰭片和所述絕緣體；在所述介電層上形成虛擬閘極帶，所述虛擬閘極帶的長度方向與所述半導體鰭片的長度方向不同；在所述虛擬閘極帶的側壁上形成一對間隙壁；移除所述虛擬閘極帶並且減薄在下方的所述介電層以在所述一對間隙壁之間形成減薄部分；以及在所述一對間隙壁之間形成閘極以覆蓋所述減薄部分和所述一對間隙壁的側壁。
  2. 如申請專利範圍第1項所述的方法，其中在移除所述虛擬閘極帶之前，所述一對間隙壁形成在所述介電層上並且沿所述虛擬閘極帶的所述側壁延伸。
  3. 如申請專利範圍第1項所述的方法，其中所述減薄部分的厚度範圍為0.2nm至5nm，並且被所述一對間隙壁覆蓋的所述介電層的厚度範圍為5nm至50nm。
  4. 如申請專利範圍第1項所述的方法，其中所述減薄部分包括凹口，並且所述凹口通過蝕刻製程形成。
  5. 如申請專利範圍第1項所述的方法，具有5nm至50nm寬度的所述閘極形成在所述一對間隙壁之間，以覆蓋所述減薄部分和所述一對間隙壁的所述側壁。
  6. 如申請專利範圍第1項所述的方法，進一步包括：形成覆蓋層以覆蓋所述閘極和所述一對間隙壁。
  7. 一種用於製造半導體裝置的方法，包括：圖案化基底以在所述基底中形成多個溝渠並且在所述溝渠之間形成多個半導體鰭片；在所述溝渠中形成多個絕緣體；形成介電層以覆蓋所述半導體鰭片和所述絕緣體；在所述介電層上形成至少一個第一虛擬閘極帶和至少一個第二虛擬閘極帶，其中所述第一和第二虛擬閘極帶的長度方向不同於所述半導體鰭片的長度方向，並且所述第一虛擬閘極帶的寬度小於所述第二虛擬閘極帶的寬度；分別在所述第一和第二虛擬閘極帶的側壁上形成一對第一間隙壁和一對第二間隙壁；移除所述第一虛擬閘極帶並且減薄在下方的所述介電層以在所述一對第一間隙壁之間形成減薄部分；移除所述第二虛擬閘極帶；在所述一對第一間隙壁之間形成第一閘極以覆蓋所述減薄部分和所述第一間隙壁的所述側壁；以及 在所述一對第二間隙壁之間形成第二閘極以覆蓋所述介電層和所述第二間隙壁的所述側壁。
  8. 如申請專利範圍第7項所述的方法，所述第一和所述第二虛擬閘極帶在相同的製程中移除。
  9. 如申請專利範圍第7項所述的方法，形成所述一對第一間隙壁以覆蓋所述介電層並沿所述第一虛擬閘極帶的所述側壁延伸，並且形成所述一對第二間隙壁以覆蓋所述介電層並沿所述第二虛擬閘極帶的所述側壁延伸。
  10. 一種半導體裝置，包括：基底，包括多個溝渠和位於所述溝渠之間的多個半導體鰭片；多個絕緣體，設置在所述溝渠中；介電層，覆蓋所述半導體鰭片和所述絕緣體並包括減薄部分；第一閘極，設置在所述減薄部分上；一對第一間隙壁，設置在所述第一閘極的側壁上；第二閘極，設置在所述介電層上；以及一對第二間隙壁，設置在所述第二閘極的側壁上，其中，所述第一和所述第二閘極的長度方向不同於所述半導體鰭片的長度方向，並且所述第一閘極的寬度小於第二閘極的寬度。
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