CN106711046A - 鳍式场效晶体管的制作方法 - Google Patents

鳍式场效晶体管的制作方法 Download PDF

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Publication number
CN106711046A
CN106711046A CN201611032568.7A CN201611032568A CN106711046A CN 106711046 A CN106711046 A CN 106711046A CN 201611032568 A CN201611032568 A CN 201611032568A CN 106711046 A CN106711046 A CN 106711046A
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dielectric layer
gate bar
fin
exposed
semiconductor fin
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CN106711046B (zh
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张哲诚
林志翰
曾鸿辉
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种鳍式场效晶体管的制作方法，包括：图案化衬底以形成多个沟槽以及位于沟槽之间的半导体鳍片。于沟槽内形成多个绝缘体，并且形成第一介电层以覆盖半导体鳍片与绝缘体。于第一介电层上形成拟栅极条。于拟栅极条的侧壁上形成多个间隙物拟栅极条。移除拟栅极条与位于其下方的第一介电层直到间隙物的侧壁、半导体鳍片的一部分以及绝缘体的多个部分被暴露出来。形成第二介电层以选择性地覆盖半导体鳍片被暴露出来的部分，其中第一介电层的厚度小于第二介电层的厚度。于间隙物之间形成栅极以覆盖第二介电层、间隙物的侧壁以及绝缘体被暴露出的部分。

Description

鳍式场效晶体管的制作方法
技术领域
本发明一实施例是有关于一种鳍式场效晶体管。
背景技术
由于半导体器件的尺寸不断缩小，三维多栅极结构，例如鳍式场效晶体管(FinFET)已被开发，以取代平面互补金属氧化物半导体(CMOS)器件。鳍式场效晶体管的结构特征为硅基鳍片(silicon based fin)从衬底的表面垂直延伸，并且栅极会围绕由鳍片所形成的导电信道，以对信道进一步提供更好的电气控制。
以具有短信道(即信道长度小于50奈米)的鳍式场效应晶体的栅极替换工艺为例，覆盖硅基鳍片的部分氧化物层需要被过度蚀刻，以使得后续的高介电常数介电层和栅极的沉积具有更好的工艺窗口(process window)。然而，氧化物层的高蚀刻量会导致金属栅极的漏电路径和挤出路径产生。
发明内容
一种鳍式场效晶体管的制作方法，包括：图案化衬底以形成多个位于衬底内的沟槽以及位于沟槽之间的半导体鳍片；于沟槽内形成多个绝缘体；形成第一介电层以覆盖半导体鳍片与绝缘体；于第一介电层上形成拟栅极条，拟栅极条的长度方向不同于半导体鳍片的长度方向；于拟栅极条的多个侧壁上形成一对间隙物；移除拟栅极条与位于其下方的第一介电层直到间隙物的多个侧壁、半导体鳍片的一部分以及绝缘体的多个部分被暴露出来；形成第二介电层以选择性地覆盖半导体鳍片被暴露出来的部分，其中第一介电层的厚度小于第二介电层的厚度；以及于间隙物之间形成栅极以覆盖第二介电层、间隙物被暴露出的侧壁以及绝缘体被暴露出来的部分。
附图说明
包含附图以便进一步理解本发明，且附图并入本说明书中并构成本说明书的一部分。附图说明本发明的实施例，并与描述一起用于解释本发明的原理。
图1绘示为根据一些实施例的一种半导体器件的制作方法的流程图。
图2A至图2L是根据一些实施例的一种半导体器件的制造方法的透视图。
附图标号说明
200、200a：衬底
202a：接垫层
202a’：图案化接垫层
202b：掩模层
202b’：图案化掩模层
204：图案化光刻胶层
206：沟槽
208：半导体鳍片
210：绝缘材料
210a：绝缘体
212：第一介电层
214a：第一拟栅极条
214b：第二拟栅极条
216a：第一间隙物
216b：第二间隙物
218：层间介电层
220：第二介电层
222a：第一栅极
222b：第二栅极
C1：第一凹槽
C2：第二凹槽
D1、D2：长度方向
G1：第一间隙
G2：第二间隙
H：高度差
S：间隙
T1：上表面
T2：顶表面
SW：侧壁
W1：第一宽度
W2：第二宽度
W3、W4：宽度
S10、S12、S14、S16、S18、S20、S22、S24、S26：步骤。
具体实施方式
以下揭露内容提供用于实施所提供的目标之不同特征的许多不同实施例或实例。以下所描述的构件及配置的具体实例是为了以简化的方式传达本发明为目的。当然，这些仅仅为实例而非用以限制。举例来说，于以下描述中，在第一特征上方或在第一特征上形成第二特征可包括第二特征与第一特征形成为直接接触的实施例，且亦可包括第二特征与第一特征之间可形成有额外特征使得第二特征与第一特征可不直接接触的实施例。此外，本发明在各种实例中可使用相同的器件符号及/或字母来指代相同或类似的部件。器件符号的重复使用是为了简单及清楚起见，且并不表示所欲讨论的各个实施例及/或配置本身之间的关系。
另外，为了易于描述附图中所绘示的一个构件或特征与另一器件或特征的关系，本文中可使用例如「在…下」、「在…下方」、「下部」、「在…上」、「在…上方」、「上部」及类似术语的空间相对术语。除了附图中所绘示的定向之外，所述空间相对术语意欲涵盖器件在使用或操作时的不同定向。设备可被另外定向(旋转90度或在其他定向)，而本文所用的空间相对术语相应地做出解释。
本发明的实施例中所揭露的半导体器件的制作方法，而前述的半导体器件包括至少一个长通道的鳍式场效晶体管以及至少一个短通道的鳍式场效晶体管。在本发明的某些实施例中，半导体器件可形成块状硅衬底(bulk silicon substrates)上。当然，半导体器件亦可以选择地形成在绝缘体上硅(silicon-on-insulator，SOI)衬底或绝缘体上锗(germanium-on-insulator，GOI)衬底上。此外，根据实施例，硅衬底可以包括其它导电层或其它半导体器件，例如晶体管、二极管或类似物。上述的实施例并不限于此。
请参考图1，其依据本发明的一些实施例绘示出一种半导体器件的制作方法的流程图。所述的制作方法至少包括步骤S10、步骤S12、步骤S14、步骤S16、步骤S18、步骤S20、步骤S22、步骤S24以及步骤S26。首先，在步骤S10中，提供衬底，接着，图案化衬底以形成多个沟槽以及多个位于沟槽之间的半导体鳍片。在步骤S12中，于沟槽内形成多个绝缘体。前述的绝缘体例如是用以绝缘半导体鳍片的浅沟槽隔离(shallow trench isolation，STI)结构。在步骤S14中，形成第一介电层以覆盖半导体鳍片以及绝缘体。在步骤S16中，于第一介电层上形成至少一第一拟栅极条与至少一第二拟栅极条，其中第一拟栅极条的长度方向与第二拟栅极条的长度方向不同，而第一拟栅极条的宽度小于第二拟栅极条的宽度。第一拟栅极条与第二拟栅极条为导电条，例如是多晶硅条。在步骤S18中，于第一拟栅极条与第二拟栅极条上分别形成一对第一间隙物与一对第二间隙物。在步骤S20中，移除第一拟栅极条而形成第一凹槽。在步骤S22中，移除第二拟栅极条与位于其下方的第一介电层直到暴露出第二间隙物的侧壁、半导体鳍片的部分以及绝缘体的部份而形成第二凹槽。在步骤S24中，于第二凹槽内形成第二介电层，以选择性地覆盖半导体鳍片被暴露出来的部分，其中第一介电层的厚度小于第二介电层的厚度。前述的第二介电层例如是透过原子层沉积(ALD)、化学气相沉积(CVD)或物理气相沉积(PVD)所形成。在步骤S26中，于第一凹槽内形成第一栅极以及于第二凹槽内形成第二栅极，以覆盖第二介电层、第二间隙物被暴露出来的侧壁以及绝缘体被暴露出来的部分。如图1所示，第一拟栅极条的移除是在第二拟栅极条的移除之前进行。然而，移除第一拟栅极条与第二拟栅极条的顺序并不限于此。
图2A绘示为半导体器件于制作方法的不同阶段中的一个阶段的透视图。在图1的步骤S10与图2A中，提供衬底200。于一实施例中，衬底200包括结晶硅衬底(如晶圆)。衬底200可依据设计需求而包括多种掺杂区(例如是p型衬底或n型衬底)。于其他实施例中，掺杂区可掺杂有p型与/或n型掺质。举例来说，掺杂区可掺杂有p型掺质，例如是硼或二氟化硼(BF2)；而n型掺质，例如是磷、砷、与/或上述的组合。掺杂区可以被配置为n型的鳍式场效晶体管、p型鳍式场效晶体管或上述的组合。于其他实施例中，衬底200可以由一些其它适合的元素半导体，如钻石或锗；适合的化合物半导体，如砷化镓、碳化硅、砷化铟或磷化铟；或者适合的合金半导体，如碳化硅锗(silicon germanium carbide，SiGeC)、磷化砷镓(galliumarsenic phosphide)或磷化铟镓(gallium indium phosphide)所组成。
于一实施例中，于衬底200上依序形成接垫层202a与掩模层202b。接垫层202a例如是透过热氧化工艺所形成的氧化硅薄膜。接垫层202可以作为衬底200与掩模层202b之间的黏着层。接垫层202a可以作为蚀刻掩模层202b的蚀刻终止层。于至少一实施例中，掩模层202b为氮化硅层，其是通过低压化学气相沉积(PECVD)或等离子增强化学气相沉积(PECVD)所形成。掩模层202b于后续的光刻工艺中被用以作为硬掩模(hard mask)。接着，于掩模层202b上形成具有预定图案的图案化光刻胶层204。
图2B绘示为半导体器件于制作方法的不同阶段中的一个阶段的透视图。在图1的步骤S10以及图2A至图2B中，掩模层202b与接垫层202a没有被图案化光刻胶层204所覆盖的地方依序被蚀刻，而形成图案化掩模层202b'以及图案化接垫层202a'，进而暴露出下面的衬底200。以图案化掩模层202b'、图案化接垫层202a'以及图案化光刻胶层204为掩模，衬底200的部分被暴露出来且被蚀刻而形成多个沟槽206与多个半导体鳍片208。于衬底200被图案化之后，图案化掩模层202b'、图案化接垫层202a'以及图案化光刻胶层204覆盖住半导体鳍片208。两相邻的沟槽206是透过间隙S而隔开。举例来说，位于沟槽206之间的间隙S可小于约30奈米。换言之，两相邻的沟槽206是由对应的半导体鳍片208而隔开。
半导体鳍片208的高度与沟槽206的深度介于约5奈米至约500奈米之间。于形成沟槽206与半导体鳍片208之后，移除图案化光刻胶层204。于一实施例中，可进行清洁工艺以移除半导体衬底200a和半导体鳍片208的原生氧化物。清洁过程可以用氢氟酸稀释溶液或其它适当的清洗液来进行。
图2C绘示为半导体器件于制作方法的不同阶段中的一个阶段的透视图。在图1的步骤S12与图2B至图2C中，于衬底200a上形成绝缘材料210以覆盖半导体鳍片208并且填满沟槽206。除了半导体鳍片208，绝缘材料210更覆盖图案化接垫层202a'与图案化掩模层202b'。绝缘材料210可包括氧化硅、氮化硅、氧氮化硅、旋涂介电材料或低介电常数的介电材料。绝缘材料210可透过高密度等离子化学气相沉积(HDP-CVD)、亚大气压化学气相沉积(ASCVD)或旋转涂布来形成。
图2D绘示为半导体器件于制作方法的不同阶段中的一个阶段的透视图。在图1的步骤S12中与图2C至图2D中，举例而言，进行化学机械研磨工艺以移除绝缘材料210的一部分、图案化掩模层202b'和图案化的接垫层202a'直到半导体鳍片208被暴露出来。如图2D所示，于研磨绝缘材料210之后，研磨后的绝缘材料210的顶表面实质上与半导体鳍片208的顶表面T2共平面。
图2E绘示为半导体器件于制作方法的不同阶段中的一个阶段的透视图。在图1的步骤S12中与图2D至图2E中，透过蚀刻工艺移除部分填充于沟槽206内已被研磨的绝缘材料210，以于衬底200a上形成多个绝缘体210a，而半导体鳍片208位于两相邻的绝缘体210a之间。于一实施例中，蚀刻工艺可以是采用氢氟酸(HF)的湿法蚀刻工艺或者是干式蚀刻工艺。绝缘体210a的上表面T1低于半导体鳍片208的顶表面T2。换言之，半导体鳍片208突出于绝缘体210a的上表面T1，且半导体鳍片208的侧壁SW因而暴露出来。半导体鳍片208的顶表面T2与绝缘体210a的上表面T1之间具有高度差H，而高度差H介于约15奈米至约50奈米之间。
图2F绘示为半导体器件于制作方法的不同阶段中的一个阶段的透视图。在图1的步骤S14与图2E至图2F中，于绝缘体210a形成之后，形成第一介电层212以共形地覆盖绝缘体210a的上表面T1、半导体鳍片208的顶表面T2以及半导体鳍片208的侧壁SW。于一实施例中，第一介电层212可包括氧化硅、氮化硅、氧氮化物或高介电常数的介电材料。高介电常数的介电材料包括金属氧化物。举例来说，用于高介电常数的介电材料的金属氧化物包括氧化物锂、铍、镁、钙、锶、钪、钇、锆、铪、铝、镧、铈、镨、钕、钐、铕、钆、镝、钬、铒、铥、镱、镥、与/或上述的混合物。于一实施例中，第一介电层212为厚度为约0.2奈米至5奈米的高介电常数的介电层。第一介电层212可以透过合适的方法，例如是原子层沉积(ALD)、化学气相沉积(CVD)、物理气相沉积(PVD)、热氧化或UV臭氧氧化来形成。第一介电层212足够薄且具有良好的质量，可作为在短通道的鳍式场效晶体管的栅极介电层。
图2G绘示为半导体器件于制作方法的不同阶段中的一个阶段的透视图。在图1的步骤S16与图2F至图2G中，于第一介电层212上形成至少一第一拟栅极条214a与至少一第二拟栅极条214b，其中第一拟栅极条214a及第二拟栅极条214b的长度方向D1与半导体鳍片208的长度方向D2不同。沿着长度方向D1，第一拟栅极条214a的第一宽度W1小于第二拟栅极条214b的第二宽度W2。第一拟栅极条214a与第二拟栅极条214b的长度方向D1例如是垂直于半导体鳍片208的长度方向D2。图2G中的第一拟栅极条214a与第二拟栅极条214b的数量仅为示意，于其他实施例中，可根据实际的设计需求来形成两个或更多的第一拟栅极条214a与第二拟栅极条214b。第一拟栅极条214a与第二拟栅极条214b包括含硅材料，例如是多晶硅、非晶硅或上述的组合。于一实施例中，第一拟栅极条214a的第一宽度W1介于5奈米至50奈米之间，而第二拟栅极条214b的第二宽度W2则大于50奈米。
在图1的步骤S18与图2G中，于形成第一拟栅极条214a与第二拟栅极条214b之后，于第一拟栅极条214a的侧壁与第二拟栅极条214b的侧壁上分别形成一对第一间隙物216a与一对第二间隙物216b。如图2H所示，第一间隙物216a形成在第一介电层212上且沿着第一拟栅极条214a的侧壁延伸，而第二间隙物216b形成在第一介电层212上且沿着第二拟栅极条214b的侧壁延伸。第一间隙物216a与第二间隙物216b是由介电材料所形成，例如是氮化硅或碳氮氧化硅(SiCON)。第一间隙物216a与第二间隙物216b可包括单层或多层结构。由于第一间隙物216a是由第一拟栅极条214a隔开，因此第一间隙物216a之间的第一间隙G1实质上等于第一拟栅极条214a的第一宽度W1。同样地，第二间隙物216b之间的第二间隙G2实质上等于第二拟栅极条214b的第二宽度W2。
图2H绘示为半导体器件于制作方法的不同阶段中的一个阶段的透视图。如图2H所示，于第一介电层212上形成多个层间介电层218。层间介电层218的上表面实质上与第一拟栅极条214a的上表面以及第二拟栅极条214b的上表面实质上共平面。于其他实施例中，于层间介电层218形成以前，可以先进行一些工艺(例如是第一介电层212的图案化工艺、鳍片凹槽(fin recessing)工艺、半导体鳍片上的应变源极/漏极外延(strained source/drainepitaxial)工艺以及硅化(silicidation)工艺等)。上述工艺的细节被省略。
图2I至2J绘示为半导体器件于制作方法的不同阶段的透视图。在图1的步骤S20及步骤S22与图2H至图2J中，移除第一拟栅极条214a与第二拟栅极条214b。于一实施例中，移除第一拟栅极条214a与第二拟栅极条214b的方法例如是蚀刻工艺。透过选择适当的蚀刻液，层间介电层218、第一介电层212、第一间隙物216a以及第二间隙物216b在第一拟栅极条214a和第二拟栅极条214b的移除过程中便不会被显着地损坏。于移除第一拟栅极条214a之后，第一间隙物216a之间形成第一凹槽C1，而第一介电层212的部分因此而被暴露出来。半导体鳍片208对应第一凹槽C1的此部分(绘示在于图2J的右侧部分)仍然被第一介电层212所覆盖。
如图2J所示，移除第一介电层212的部分以及位于第二拟栅极条214b的部分绝缘体210a直到第二间隙物216b的侧壁、半导体鳍片208的部分以及绝缘体210a的部分被暴露出来而形成第二凹槽C2。于第二凹槽C2的形成过程中，被第一凹槽C1所暴露出的第一介电层212例如是被良好地保护以免于被移除。于一实施例中，被第一凹槽C1所暴露出的第一介电层212可被光刻胶层所保护及覆盖以免于被移除。
于第二凹槽C2的形成过程中，第一介电层212会被蚀刻且稍微过度蚀刻。于其他实施例中，于形成第二凹槽C2的过程中，绝缘体210a可以作为蚀刻终止层，以便控制第二凹槽C2的轮廓。于第二凹槽C2形成之后，半导体鳍片208对应第二凹槽C2的部分(绘示在图2J的左侧部分)会被暴露出来。值得注意的是，沿着半导体鳍片208的长度方向D2，半导体鳍片208对应于第二凹槽C2的部份(绘示在图2J的左侧部分)具有较大尺寸，而半导体鳍片208对应于第一凹槽C1的部分(绘示在图2J的右侧部分)具有较小尺寸。
图2K绘示为半导体器件于制作方法的不同阶段中的一个阶段的透视图。在图1的步骤S24与图2J至图2K中，于形成第二凹槽C2之后，于第二凹槽C2内形成第二介电层220以选择性地覆盖住半导体鳍片208被暴露出来的部分，其中第一介电层212的厚度小于第二介电层220的厚度。第二介电层220选择性地成长于半导体鳍片208被暴露出来的部分上，据此，形成在第二凹槽C2内的第二介电层220没有完全覆盖住绝缘体210a所被暴露出来的部分，而第二间隙物216b的侧壁仅仅一部分与第二介电层220接触。于一实施例中，第二介电层220可以包括氧化硅、氮化硅、氧氮化物或高介电常数的介电材料。高介电常数的介电材料包括金属氧化物。举例来说，用于高介电常数的介电材料的金属氧化物包括氧化物锂、铍、镁、钙、锶、钪、钇、锆、铪、铝、镧、铈、镨、钕、钐、铕、钆、镝、钬、铒、铥、镱、镥、与/或上述的混合物。于一实施例中，第二介电层220为具有厚度在大约5奈米到50奈米的高介电常数的介电层。第二介电层220可透过合适的方法如热氧化来形成。第二介电层220比第一介电层212更厚，适合用作在长通道的鳍式场效晶体管的栅极介电层。
如图2K至图2L所示，于第一凹槽C1内形成第一栅极222a，并且于第二凹槽C2内形成第二栅极222b以覆盖第二介电层220、第二间隙物216b的侧壁以及绝缘体210a被暴露出来的部分。第二介电层220配置于第二栅极222b与半导体鳍片208被暴露出的部分之间。第二介电层220不存在于第二栅极222b与第二间隙物216b之间。于一些实施例中，第一栅极222a与第二栅极222b可包括一层或多层结构。于一些实施例中，第一栅极222a与第二栅极222b可包括金属，例如是铝、铜、钨、钛、钽、氮化钛、铝化钛、氮化铝钛、氮化钽、硅化镍、硅化钴、其他具有功函数且与基底材料兼容的导电材料，或上述材料的组合。于一些实施例中，第一栅极222a与第二栅极222b的厚度例如是介于约30奈米至约60奈米之间。第一栅极222a与第二栅极222b可透过合适的方法，例如原子层沉积(ALD)、化学气相沉积(CVD)、物理气相沉积(PVD)、电镀或上述工艺的组合来形成。
于一实施例中，第一栅极222a的宽度W3为5奈米至50奈米，而第二栅极222b的宽度W4大于50奈米。与第一栅极222重叠且被第一栅极222a覆盖的部分半导体鳍片208可作为短通道鳍式场效晶体管的通道，而与第二栅极222b重叠且被第二栅极222b覆盖的部分半导体鳍片208可作为长通道鳍式场效晶体管的通道。
如图2G与图2L所示，第一栅极222a的宽度W3、第一拟栅极条214a的宽度W1以及第一间隙物216a之间的第一间隙G1实质上相同(即W3＝W1＝G1)。第二栅极222b的宽度W4、第二拟栅极条214b的宽度W2以及第二间隙物216b之间的第二间隙G2实质上相同(即W4＝W2＝G2)。
在短通道的鳍式场效晶体管中(绘示于图2L的右侧部分)，较薄的第一介电层212被形成以用作栅极介电层；在长通道的鳍式场效晶体管中(绘示于图2L的左侧部分)，较薄的第一介电层212被移除，且被选择性地成长以及较厚的第二介电层220所取代。由于第二介电层220具有较大的厚度，半导体鳍片208被暴露出来的部分会被良好地包覆以防止第二栅极222b的漏电路径(leakage path)和挤出路径(extrusion path)的形成。因此，栅极置换工艺的工艺窗口可被放大。据此，可提高半导体器件的良率(yield)和可靠性。
根据一些实施方案中，鳍式场效应晶体的制造方法包括至少以下步骤。图案化衬底以形成多个位于衬底内的沟槽以及位于沟槽之间的半导体鳍片。于沟槽内形成多个绝缘体。形成第一介电层以覆盖半导体鳍片与绝缘体。于第一介电层上形成拟栅极条，拟栅极条的长度方向不同于半导体鳍片的长度方向。于拟栅极条的多个侧壁上形成一对间隙物。移除拟栅极条与位于拟栅极条下方的第一介电层直到间隙物的多个侧壁、半导体鳍片的一部分以及绝缘体的多个部分被暴露出来。形成第二介电层以选择性地覆盖半导体鳍片被暴露出来的部分，其中第一介电层的厚度小于第二介电层的厚度。于间隙物之间形成栅极以覆盖第二介电层、间隙物被暴露出的侧壁以及绝缘体被暴露出来的部分。
在所述鳍式场效应晶体的制造方法中，于拟栅极条移除之前，于第一介电层上形成间隙物，且间隙物沿着拟栅极条的侧壁延伸。
在所述鳍式场效应晶体的制造方法中，移除拟栅极条与第一介电层以形成位于间隙物之间的凹槽，而第二介电层形成于凹槽所暴露出的半导体鳍片的部分上。
在所述鳍式场效应晶体的制造方法中，拟栅极条、第一介电层以及部分的绝缘体是在形成凹槽的蚀刻工艺中被移除。
在所述鳍式场效应晶体的制造方法中，第二介电层是透过热氧化而形成。
在所述鳍式场效应晶体的制造方法中，具有宽度大于50奈米的栅极形成于间隙物之间以覆盖第二介电层、间隙物被暴露出的侧壁以及绝缘体被暴露出的部分。
在所述鳍式场效应晶体的制造方法中，鳍式场效晶体管的制作方法，更包括:于移除拟栅极条之前，形成源极与漏极于半导体鳍片上。
根据其他实施例中，半导体器件的制作方法至少包括以下步骤。图案化衬底以形成多个位于衬底内的沟槽以及多个位于沟槽之间的半导体鳍片。形成多个绝缘体于沟槽内。形成第一介电层以覆盖半导体鳍片与绝缘体。形成至少一第一拟栅极条与至少一第二拟栅极条于第一介电层上，其中第一拟栅极条与第二拟栅极条的长度方向不同于半导体鳍片的长度方向，且第一拟栅极条的宽度小于第二拟栅极条的宽度。分别形成一对第一间隙物以及一对第二间隙物于第一拟栅极条的多个侧壁上以及第二拟栅极条的多个侧壁上。移除第一拟栅极条以形成第一凹槽。移除第二拟栅极条与位于第二拟栅极条下方的第一介电层直到第二间隙物的多个侧壁、半导体鳍片的一部分以及绝缘体的多个部分被暴露出来，而形成第二凹槽。形成第二介电层于第二凹槽内以选择性地覆盖半导体鳍片被暴露出来的部分，其中第一介电层的厚度小于第二介电层的厚度。形成第一栅极于第一凹槽内。形成第二栅极于第二凹槽内以覆盖第二介电层，第二间隙物被暴露出来的侧壁以及绝缘体被暴露出来的部分。
在所述半导体器件的制造方法中，第一拟栅极条与第二拟栅极条于同一步骤中移除。
在所述半导体器件的制造方法中，形成第一拟栅极条与第二拟栅极条的方法，包括:形成导电层于第一介电层上；以及图案化导电层以形成具有第一宽度的第一导电条以及具有第二宽度的第二导电条，第一宽度小于第二宽度。
在所述半导体器件的制造方法中，第一间隙物形成于第一介电层上且沿着第一拟栅极条的侧壁延伸，第二间隙物形成于第一介电层上且沿着第二拟栅极条的侧壁延伸。
在所述半导体器件的制造方法中，移除第二拟栅极条，位于第二拟栅极条下方的第一介电层以及部分的绝缘体是在形成第二凹槽的蚀刻工艺中。
在所述半导体器件的制造方法中，第二介电层是透过热氧化而形成。
在所述半导体器件的制造方法中，具有宽度介于5奈米至50奈米的第一栅极形成于第一凹槽内，而具有宽度大于50奈米的第二栅极形成于第二凹槽内，以覆盖第二介电层、第二间隙物的被暴露出来的侧壁以及绝缘体被暴露出来的部分。
在所述半导体器件的制造方法中，半导体器件的制作方法，更包括:于移除第一拟栅极条与第二拟栅极条之前，形成多个源极与多个漏极于半导体鳍片上。
根据其他实施例，半导体器件包括衬底、多个绝缘体、第一介电层、一对第一间隙物、第一栅极、一对第二间隙物、第二介电层和第二栅极。衬底包括多个沟槽以及多个位于沟槽之间的半导体鳍片。绝缘体位于沟槽内。第一介电层覆盖半导体鳍片与绝缘体，且暴露出半导体鳍片的一部分以及绝缘体的部分。第一间隙物配置于第一介电层上。第一栅极配置于第一介电层上且位于第一间隙物之间。第二间隙物配置于第一介电层上。第二介电层配置于第二间隙物之间，其中第二介电层选择性覆盖半导体鳍片被暴露出来的部分，而第一介电层的厚度小于第二介电层的厚度。第二栅极配置于第二间隙物之间以覆盖第二介电层、第二间隙物被暴露出的侧壁以及绝缘体被暴露出来的部分，其中第一栅极的宽度小于第二栅极的宽度。
在所述半导体器件中，第一介电层的厚度介于0.2奈米至5奈米之间，且第二介电层的厚度介于5奈米至50奈米之间。
在所述半导体器件中，第一栅极的宽度介于5奈米至50奈米之间，而第二栅极的宽度大于50奈米。
在所述半导体器件中，第二栅极的宽度实质上等于第二间隙物之间的一间隙。
在所述半导体器件中，第二介电层配置于半导体鳍片被暴露出出来的部分与第二栅极之间。
以上概述了数个实施例的特征，使本领域具有通常知识者可更佳了解本发明的态样。本领域具有通常知识者应理解，其可轻易地使用本发明作为设计或修改其他工艺与结构的依据，以实行本文所介绍的实施例的相同目的及/或达到相同优点。本领域具有通常知识者还应理解，这种等效的配置并不悖离本发明的精神与范畴，且本领域具有通常知识者在不悖离本发明的精神与范畴的情况下可对本文做出各种改变、置换以及变更。

Claims (1)

1.一种鳍式场效晶体管的制作方法，其特征在于，包括：
图案化衬底以形成多个位于所述衬底内的沟槽以及位于所述多个沟槽之间的半导体鳍片；
于所述多个沟槽内形成多个绝缘体；
形成第一介电层以覆盖所述半导体鳍片与所述多个绝缘体；
于所述第一介电层上形成拟栅极条，所述拟栅极条的长度方向不同于所述半导体鳍片的长度方向；
于所述拟栅极条的多个侧壁上形成一对间隙物；
移除所述拟栅极条与位于所述拟栅极条下方的所述第一介电层直到所述一对间隙物的多个侧壁、所述半导体鳍片的一部分以及所述多个绝缘体的多个部分被暴露出来；
形成第二介电层以选择性地覆盖所述半导体鳍片被暴露出来的所述部分，其中所述第一介电层的厚度小于所述第二介电层的厚度；以及
于所述一对间隙物之间形成栅极以覆盖所述第二介电层、所述一对间隙物被暴露出的所述多个侧壁以及所述多个绝缘体被暴露出来的部分。
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