JP5989538B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- JP5989538B2 JP5989538B2 JP2012281681A JP2012281681A JP5989538B2 JP 5989538 B2 JP5989538 B2 JP 5989538B2 JP 2012281681 A JP2012281681 A JP 2012281681A JP 2012281681 A JP2012281681 A JP 2012281681A JP 5989538 B2 JP5989538 B2 JP 5989538B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- region
- field effect
- effect transistor
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 192
- 238000004519 manufacturing process Methods 0.000 title claims description 77
- 230000015654 memory Effects 0.000 claims description 134
- 238000000034 method Methods 0.000 claims description 58
- 239000012535 impurity Substances 0.000 claims description 52
- 239000000758 substrate Substances 0.000 claims description 49
- 230000005669 field effect Effects 0.000 claims description 47
- 230000008569 process Effects 0.000 claims description 30
- 230000015572 biosynthetic process Effects 0.000 claims description 25
- 239000004020 conductor Substances 0.000 claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 12
- 229910021332 silicide Inorganic materials 0.000 claims description 12
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 7
- 230000003213 activating effect Effects 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 5
- 238000005468 ion implantation Methods 0.000 description 37
- 238000001459 lithography Methods 0.000 description 13
- 238000005229 chemical vapour deposition Methods 0.000 description 11
- 238000005530 etching Methods 0.000 description 11
- 229920005591 polysilicon Polymers 0.000 description 11
- 238000001312 dry etching Methods 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 238000000137 annealing Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 7
- 229910052814 silicon oxide Inorganic materials 0.000 description 7
- 238000009826 distribution Methods 0.000 description 6
- 238000009413 insulation Methods 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- PCLURTMBFDTLSK-UHFFFAOYSA-N nickel platinum Chemical compound [Ni].[Pt] PCLURTMBFDTLSK-UHFFFAOYSA-N 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 235000011114 ammonium hydroxide Nutrition 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000007888 film coating Substances 0.000 description 1
- 238000009501 film coating Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 1
- 229910021334 nickel silicide Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021339 platinum silicide Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
- H01L29/42344—Gate electrodes for transistors with charge trapping gate insulator with at least one additional gate, e.g. program gate, erase gate or select gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
Description
本実施の形態1の半導体装置は、例えば、不揮発性メモリとプレーナ型のコア(Core)トランジスタとを同一の半導体基板に設けたMCU等のようなメモリロジック混載型の半導体装置である。
本実施の形態2においては、メモリ領域Mのメモリゲートの抵抗を低くするため、そのメモリゲートの高さを前記実施の形態1よりも高くする場合の半導体装置の製造方法の一例について図26〜図41を参照して説明する。なお、図26〜図41は本実施の形態2の半導体装置の製造工程中の要部断面図である。
本実施の形態3においては、メモリ領域Mのメモリゲートの抵抗を低くするため、そのメモリゲートの上部をシリサイド化する場合の半導体装置の製造方法の一例について図42、図43を参照して説明する。なお、図42、図43は本実施の形態3の半導体装置の製造工程中の要部断面図である。
図44は本実施の形態4の半導体装置の要部断面図である。
C コア領域
HV 高電圧領域
SUB 基板
ST 分離部
Gia ゲート絶縁膜
Gib ゲート絶縁膜
Gic ゲート絶縁膜
Gid ゲート絶縁膜
Gie ゲート絶縁膜
DG ダミーゲート膜
HM ハードマスク膜
Qcp pチャネル型のMOSFET
Qcn nチャネル型のMOSFET
Qhp pチャネル型のMOSFET
Qhn nチャネル型のMOSFET
GF ゲート膜
G ゲート電極
CLp p−型の半導体領域
CLn n−型の半導体領域
CHp p+型の半導体領域
CHn n+型の半導体領域
HLp p−型の半導体領域
HLn n−型の半導体領域
HHp p+型の半導体領域
HHn n+型の半導体領域
MC メモリセル
CG コントロールゲート
Mi メモリ絶縁膜
MGF メモリゲート膜
MG メモリゲート
MLm,MLc n−型の半導体領域
MHm,MHc n+型の半導体領域
LF1 絶縁膜
LF2 絶縁膜
GH 凹部
SF スペーサ膜
SW サイドウォール
SC 導体膜
SS シリサイド
Claims (8)
- (a)第1の電源電圧で駆動する第1の電界効果トランジスタの形成領域と前記第1の電源電圧よりも高い第2の電源電圧で駆動する第2の電界効果トランジスタの形成領域とを備える半導体基板上に第1の絶縁膜を形成する工程と、
(b)前記第1の絶縁膜上にダミーゲート膜を堆積する工程と、
(c)前記ダミーゲート膜上にハードマスク膜を堆積する工程と、
(d)前記第2の電界効果トランジスタの形成領域の前記ハードマスク膜の厚さが、前記第1の電界効果トランジスタの形成領域の前記ハードマスク膜の厚さよりも厚くなるように前記ハードマスク膜を加工する工程と、
(e)前記(d)工程後の前記ダミーゲート膜および前記ハードマスク膜をパターニングする工程と、
(f)前記(e)工程後、前記第1の電界効果トランジスタのソースおよびドレイン用の半導体領域を形成する工程と、
(g)前記(e)工程後、前記第2の電界効果トランジスタのソースおよびドレイン用の半導体領域を形成する工程と、
(h)前記(f)および(g)工程後、前記第1の電界効果トランジスタおよび前記第2の電界効果トランジスタのソースおよびドレイン用の半導体領域を活性化するための熱処理を施す工程と、
(i)前記(h)工程後、前記半導体基板上に第2の絶縁膜を堆積した後、前記ダミーゲート膜が露出するまで前記第2の絶縁膜を除去する工程と、
(j)前記(i)工程後、前記第2の絶縁膜から露出された前記ダミーゲート膜を除去する工程と、
(k)前記(j)工程後、前記ダミーゲート膜の除去領域に前記第1の絶縁膜よりも誘電率が高い第3の絶縁膜を形成する工程と、
(l)前記(k)工程後、前記ダミーゲート膜の除去領域に前記第3の絶縁膜を介して金属を主成分とする導体膜により形成されるゲート電極を形成する工程と、
を有する半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(f)工程は、
前記第1の電界効果トランジスタのソースおよびドレイン用の相対的に低不純物濃度の半導体領域を形成する工程と、
前記第1の電界効果トランジスタのソースおよびドレイン用の相対的に高不純物濃度の半導体領域を形成する工程と、
を有し、
前記(g)工程は、
前記第2の電界効果トランジスタのソースおよびドレイン用の相対的に低不純物濃度の半導体領域を形成する工程と、
前記第2の電界効果トランジスタのソースおよびドレイン用の相対的に高不純物濃度の半導体領域を形成する工程と、
を有する半導体装置の製造方法。 - 請求項2記載の半導体装置の製造方法において、
前記第2の電界効果トランジスタの前記低不純物濃度の半導体領域の深さが、前記第1の電界効果トランジスタの前記低不純物濃度の半導体領域の深さよりも深く、
前記第2の電界効果トランジスタの前記高不純物濃度の半導体領域の深さが、前記第1の電界効果トランジスタの前記高不純物濃度の半導体領域の深さよりも深い、
半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記半導体基板は、コントロールゲートとメモリゲートとがメモリ絶縁膜を介して前記半導体基板の上面に沿って並ぶ不揮発性メモリセルが配置されるメモリ領域を有しており、
前記(b)工程後、前記(c)工程前に、前記メモリ領域の前記ダミーゲート膜の厚さが、前記第1の電界効果トランジスタの形成領域および前記第2の電界効果トランジスタの形成領域の前記ダミーゲート膜の厚さよりも薄くなるように、前記メモリ領域の前記ダミーゲート膜を加工する工程、
を有する半導体装置の製造方法。 - 請求項4記載の半導体装置の製造方法において、
前記ダミーゲート膜が多結晶シリコンにより形成されており、
前記コントロールゲートを前記ダミーゲート膜により形成する工程、
を有する半導体装置の製造方法。 - 請求項4記載の半導体装置の製造方法において、
前記メモリゲートの上面の高さが、前記ダミーゲート膜により形成される前記コントロールゲートの上面上の前記ハードマスク膜の上面の高さになるように前記メモリゲートを加工する工程、
を有する半導体装置の製造方法。 - 請求項6記載の半導体装置の製造方法において、
前記メモリゲートの上部にシリサイド層を形成する工程、
を有する半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記半導体基板は、コントロールゲートとメモリゲートとがメモリ絶縁膜を介して前記半導体基板の上面に沿って並ぶ不揮発性メモリセルが配置されるメモリ領域を有しており、
前記(i)工程において、前記メモリ領域、前記第1の電界効果トランジスタの形成領域および前記第2の電界効果トランジスタの形成領域の前記ダミーゲート膜が露出するまで前記第2の絶縁膜を除去する工程と、
前記(j)工程において、前記メモリ領域、前記第1の電界効果トランジスタの形成領域および前記第2の電界効果トランジスタの形成領域の前記ダミーゲート膜を除去する工程と、
前記(k)工程において、前記メモリ領域、前記第1の電界効果トランジスタの形成領域および前記第2の電界効果トランジスタの形成領域の前記ダミーゲート膜の除去領域内に前記第3の絶縁膜を形成する工程と、
前記(l)工程において、前記メモリ領域、前記第1の電界効果トランジスタの形成領域および前記第2の電界効果トランジスタの形成領域の前記ダミーゲート膜の除去領域内に埋め込まれるように前記半導体基板上に前記導体膜を堆積した後、前記導体膜の上部を除去することにより、前記メモリ領域の前記ダミーゲート膜の除去領域内に前記第3の絶縁膜を介して前記導体膜で形成されるコントロールゲートを形成し、かつ、前記第1の電界効果トランジスタの形成領域および前記第2の電界効果トランジスタの形成領域の前記ダミーゲート膜の除去領域内に前記第3の絶縁膜を介して前記導体膜で形成されるゲート電極を形成する工程と、
を有する半導体装置の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012281681A JP5989538B2 (ja) | 2012-12-25 | 2012-12-25 | 半導体装置の製造方法 |
US14/133,605 US9177807B2 (en) | 2012-12-25 | 2013-12-18 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012281681A JP5989538B2 (ja) | 2012-12-25 | 2012-12-25 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2014127527A JP2014127527A (ja) | 2014-07-07 |
JP5989538B2 true JP5989538B2 (ja) | 2016-09-07 |
Family
ID=50975092
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2012281681A Expired - Fee Related JP5989538B2 (ja) | 2012-12-25 | 2012-12-25 | 半導体装置の製造方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US9177807B2 (ja) |
JP (1) | JP5989538B2 (ja) |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130237046A1 (en) * | 2012-03-09 | 2013-09-12 | Chien-Ting Lin | Semiconductor process |
JP6026914B2 (ja) * | 2013-02-12 | 2016-11-16 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US9054135B2 (en) * | 2013-07-31 | 2015-06-09 | Globalfoundries Singapore Pte. Ltd. | Methods for fabricating integrated circuits with a high-voltage MOSFET |
US9368605B2 (en) * | 2013-08-28 | 2016-06-14 | Globalfoundries Inc. | Semiconductor structure including a split gate nonvolatile memory cell and a high voltage transistor, and method for the formation thereof |
US9111867B2 (en) * | 2013-08-30 | 2015-08-18 | Freescale Semiconductor, Inc. | Split gate nanocrystal memory integration |
US9659953B2 (en) * | 2014-07-07 | 2017-05-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | HKMG high voltage CMOS for embedded non-volatile memory |
US9190272B1 (en) * | 2014-07-15 | 2015-11-17 | Samsung Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
JP2016051745A (ja) * | 2014-08-29 | 2016-04-11 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
US9793281B2 (en) * | 2015-07-21 | 2017-10-17 | Silicon Storage Technology, Inc. | Non-volatile split gate memory cells with integrated high K metal gate logic device and metal-free erase gate, and method of making same |
JP2017041614A (ja) * | 2015-08-21 | 2017-02-23 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
US10020304B2 (en) * | 2015-11-16 | 2018-07-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fin field effect transistor, semiconductor device and fabricating method thereof |
US9985042B2 (en) * | 2016-05-24 | 2018-05-29 | Silicon Storage Technology, Inc. | Method of integrating FinFET CMOS devices with embedded nonvolatile memory cells |
JP2018056175A (ja) | 2016-09-26 | 2018-04-05 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
CN108091651B (zh) | 2016-11-23 | 2021-03-30 | 中芯国际集成电路制造(北京)有限公司 | 半导体装置及其制造方法 |
JP6787798B2 (ja) | 2017-01-19 | 2020-11-18 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP6889001B2 (ja) * | 2017-03-30 | 2021-06-18 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US10475895B2 (en) * | 2017-05-25 | 2019-11-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method for manufacturing the same |
JP7053388B2 (ja) | 2018-06-28 | 2022-04-12 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US11217596B2 (en) | 2018-09-20 | 2022-01-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Flash memory with improved gate structure and a method of creating the same |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09312380A (ja) * | 1996-05-23 | 1997-12-02 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
JP3895069B2 (ja) | 1999-02-22 | 2007-03-22 | 株式会社東芝 | 半導体装置とその製造方法 |
JP3906005B2 (ja) * | 2000-03-27 | 2007-04-18 | 株式会社東芝 | 半導体装置の製造方法 |
JP2006245167A (ja) * | 2005-03-02 | 2006-09-14 | Toshiba Corp | 半導体装置及びその製造方法 |
JP4928825B2 (ja) * | 2006-05-10 | 2012-05-09 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP4607850B2 (ja) | 2006-11-30 | 2011-01-05 | 株式会社東芝 | 半導体装置の製造方法 |
JP5151303B2 (ja) * | 2007-08-07 | 2013-02-27 | ソニー株式会社 | 半導体装置の製造方法 |
JP4458129B2 (ja) * | 2007-08-09 | 2010-04-28 | ソニー株式会社 | 半導体装置およびその製造方法 |
JP5550286B2 (ja) * | 2009-08-26 | 2014-07-16 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP2012238630A (ja) * | 2011-05-10 | 2012-12-06 | Panasonic Corp | 半導体装置及びその製造方法 |
-
2012
- 2012-12-25 JP JP2012281681A patent/JP5989538B2/ja not_active Expired - Fee Related
-
2013
- 2013-12-18 US US14/133,605 patent/US9177807B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US9177807B2 (en) | 2015-11-03 |
JP2014127527A (ja) | 2014-07-07 |
US20140179076A1 (en) | 2014-06-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5989538B2 (ja) | 半導体装置の製造方法 | |
US8502299B2 (en) | Strained semiconductor device and method of making same | |
US20210288163A1 (en) | Polysilicon Design for Replacement Gate Technology | |
US9099334B2 (en) | Method of manufacturing semiconductor device and semiconductor device | |
JP5550286B2 (ja) | 半導体装置の製造方法 | |
JP4524995B2 (ja) | 半導体装置 | |
US20100187613A1 (en) | Method of Setting a Work Function of a Fully Silicided Semiconductor Device, and Related Device | |
US10186518B2 (en) | Method of manufacturing semiconductor device | |
JP2004165553A (ja) | 半導体記憶装置 | |
TWI469262B (zh) | 半導體裝置之製造方法及半導體裝置 | |
JP6778607B2 (ja) | 半導体装置の製造方法 | |
US9754955B2 (en) | High-K-last manufacturing process for embedded memory with metal-oxide-nitride-oxide-silicon (MONOS) memory cells | |
CN102376538A (zh) | 形成多晶硅电阻装置的方法以及半导体装置 | |
US20160126327A1 (en) | Method of making a split gate memory cell | |
US9837427B2 (en) | Semiconductor device and method of manufacturing the same | |
US20120056268A1 (en) | Semiconductor device and manufacturing method thereof | |
TW201916179A (zh) | 半導體裝置及其製造方法 | |
JP2007109860A (ja) | 半導体装置の製造方法 | |
JP2017183304A (ja) | 半導体装置およびその製造方法 | |
JP2006108355A (ja) | 半導体装置およびその製造方法 | |
JP2010062499A (ja) | 半導体装置および半導体装置の製造方法 | |
TWI782941B (zh) | 製作p型場效電晶體的方法 | |
JP2004221170A (ja) | 半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20150812 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20160725 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20160802 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20160810 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5989538 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
LAPS | Cancellation because of no payment of annual fees |