JP4458129B2 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP4458129B2 JP4458129B2 JP2007207418A JP2007207418A JP4458129B2 JP 4458129 B2 JP4458129 B2 JP 4458129B2 JP 2007207418 A JP2007207418 A JP 2007207418A JP 2007207418 A JP2007207418 A JP 2007207418A JP 4458129 B2 JP4458129 B2 JP 4458129B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/82385—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
その製造方法の一例を、図25〜図33の製造工程断面図によって説明する。
Claims (6)
- 半導体基板に、第1トランジスタ群と、前記第1トランジスタ群の動作電圧よりも低い動作電圧の第2トランジスタ群と、抵抗とを備え、
前記第1トランジスタ群は、前記半導体基板上に第1ゲート絶縁膜を介してシリコン系材料層で形成された第1ゲート電極を有し、
前記第2トランジスタ群は、前記半導体基板上の層間絶縁膜に形成したゲート形成溝内に第2ゲート絶縁膜を介して金属系ゲート材料を埋め込むように形成された第2ゲート電極を有し、
前記抵抗は、前記半導体基板上に絶縁膜を介して形成され、前記シリコン系材料層の下層部で形成された抵抗本体部と、該シリコン系材料層の上層部で形成されていて、絶縁層である抵抗保護層とを有し、
前記抵抗保護層は、N型不純物とP型不純物とが補償されている前記シリコン系材料層の上層部で形成された補償層からなる
半導体装置。 - 前記補償層は、前記シリコン系材料層の上層部に打ち込まれている不純物の導電型を打ち消す逆導電型の不純物が打ち込まれていて、絶縁層となっている
請求項1記載の半導体装置。 - 半導体基板に、第1トランジスタ群と、前記第1トランジスタ群の動作電圧よりも低い動作電圧の第2トランジスタ群と、抵抗とを有し、
前記第1トランジスタ群は、前記半導体基板上に第1ゲート絶縁膜を介してシリコン系材料層で形成された第1ゲート電極を有し、
前記第2トランジスタ群は、前記半導体基板上に形成されたダミーゲート部を除去して形成したゲート形成溝内に、第2ゲート絶縁膜を介して埋め込むように形成された金属系ゲート電極の第2ゲート電極を有し、
前記抵抗は、前記第1ゲート絶縁膜と同一層で形成された絶縁膜を介して形成され、前記シリコン系材料層の下層部で形成された抵抗本体部を有する
半導体装置の製造方法において、
前記シリコン系材料層から前記第1ゲート電極を形成する前に、前記抵抗本体部が形成される前記シリコン系材料層の上層部を絶縁層にして抵抗保護層を形成してから、
前記抵抗保護層を上層部に形成した前記シリコン系材料層の下層部で前記抵抗本体部を形成し、それと同時に前記シリコン系材料層で前記第1ゲート電極を形成し、
その後、前記第2ゲート電極を形成する
半導体装置の製造方法。 - 前記第2ゲート電極を形成した後、前記第2ゲート電極上に保護膜を形成し、該保護膜と前記抵抗保護層とをシリサイド化工程を行うためのマスクとして用いてシリサイド化工程を行い、前記第1ゲート電極上にシリサイド層を形成する
ことを特徴とする請求項3記載の半導体装置の製造方法。 - 前記抵抗保護層は、前記シリコン系材料層の上層部に酸素もしくは二酸化炭素をクラス
ターイオン注入した酸化層で形成される
請求項3記載の半導体装置の製造方法。 - 前記抵抗保護層は、前記シリコン系材料層の上層部にイオン注入もしくはクラスターイオン注入してN型不純物とP型不純物とを補償した補償層で形成される
請求項3記載の半導体装置の製造方法。
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007207418A JP4458129B2 (ja) | 2007-08-09 | 2007-08-09 | 半導体装置およびその製造方法 |
TW097127964A TWI447898B (zh) | 2007-08-09 | 2008-07-23 | 半導體裝置及其製造方法 |
US12/182,614 US8436424B2 (en) | 2007-08-09 | 2008-07-30 | Semiconductor device and method of manufacturing the same |
KR1020080077815A KR101521948B1 (ko) | 2007-08-09 | 2008-08-08 | 반도체 장치 및 그 제조 방법 |
CN2008101457146A CN101364598B (zh) | 2007-08-09 | 2008-08-11 | 半导体装置及其制造方法 |
US13/027,655 US8557655B2 (en) | 2007-08-09 | 2011-02-15 | Semiconductor device and method of manufacturing the same |
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JP2007207418A JP4458129B2 (ja) | 2007-08-09 | 2007-08-09 | 半導体装置およびその製造方法 |
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JP2009043944A JP2009043944A (ja) | 2009-02-26 |
JP4458129B2 true JP4458129B2 (ja) | 2010-04-28 |
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US (2) | US8436424B2 (ja) |
JP (1) | JP4458129B2 (ja) |
KR (1) | KR101521948B1 (ja) |
CN (1) | CN101364598B (ja) |
TW (1) | TWI447898B (ja) |
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KR101095741B1 (ko) * | 2006-05-31 | 2011-12-21 | 르네사스 일렉트로닉스 가부시키가이샤 | 반도체 장치 |
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KR100760634B1 (ko) * | 2006-10-02 | 2007-09-20 | 삼성전자주식회사 | 낸드형 비휘발성 기억 소자 및 그 형성 방법 |
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KR100849716B1 (ko) * | 2006-12-28 | 2008-08-01 | 주식회사 하이닉스반도체 | 화학적, 기계적 연마용 슬러리와, 화학적, 기계적 연마장치 및 방법 |
US7812414B2 (en) * | 2007-01-23 | 2010-10-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid process for forming metal gates |
US7808028B2 (en) * | 2007-04-18 | 2010-10-05 | International Business Machines Corporation | Trench structure and method of forming trench structure |
JP4458129B2 (ja) * | 2007-08-09 | 2010-04-28 | ソニー株式会社 | 半導体装置およびその製造方法 |
US20090166555A1 (en) * | 2007-12-28 | 2009-07-02 | Olson Joseph C | RF electron source for ionizing gas clusters |
US7932146B2 (en) * | 2008-03-20 | 2011-04-26 | United Microelectronics Corp. | Metal gate transistor and polysilicon resistor and method for fabricating the same |
US7879666B2 (en) * | 2008-07-23 | 2011-02-01 | Freescale Semiconductor, Inc. | Semiconductor resistor formed in metal gate stack |
US8071437B2 (en) * | 2009-11-19 | 2011-12-06 | United Microelectronics Corp. | Method of fabricating efuse, resistor and transistor |
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US20090039423A1 (en) | 2009-02-12 |
US20110143515A1 (en) | 2011-06-16 |
US8557655B2 (en) | 2013-10-15 |
KR101521948B1 (ko) | 2015-05-20 |
TW200913229A (en) | 2009-03-16 |
JP2009043944A (ja) | 2009-02-26 |
US8436424B2 (en) | 2013-05-07 |
TWI447898B (zh) | 2014-08-01 |
CN101364598B (zh) | 2011-07-27 |
KR20090015858A (ko) | 2009-02-12 |
CN101364598A (zh) | 2009-02-11 |
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