JP6778607B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP6778607B2 JP6778607B2 JP2016249185A JP2016249185A JP6778607B2 JP 6778607 B2 JP6778607 B2 JP 6778607B2 JP 2016249185 A JP2016249185 A JP 2016249185A JP 2016249185 A JP2016249185 A JP 2016249185A JP 6778607 B2 JP6778607 B2 JP 6778607B2
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Description
<半導体装置の構造について>
本実施の形態および以下の実施の形態の半導体装置は、不揮発性メモリ(不揮発性記憶素子、フラッシュメモリ、不揮発性半導体記憶装置)を備えた半導体装置である。本実施の形態および以下の実施の形態では、不揮発性メモリは、nチャネル型MISFET(MISFET:Metal Insulator Semiconductor Field Effect Transistor)を基本としたメモリセルをもとに説明を行う。また、本実施の形態および以下の実施の形態での極性(書込・消去・読出時の印加電圧の極性やキャリアの極性)は、nチャネル型MISFETを基本としたメモリセルの場合の動作を説明するためのものであり、pチャネル型MISFETを基本とする場合は、印加電位やキャリアの導電型等の全ての極性を反転させることで、原理的には同じ動作を得ることができる。
本実施の形態の半導体装置の製造方法を、図面を参照して説明する。
次に、不揮発性メモリの動作例について、図36を参照して説明する。
本発明者は、スプリットゲート型のメモリセルについて検討してきた。スプリットゲート型のメモリセルを構成するメモリゲート電極(メモリゲート電極MGに対応)と制御ゲート電極(制御ゲート電極CGに対応)のうち、制御ゲート電極については、メタルゲート電極を適用することで、制御ゲート電極の空乏化現象を抑制し、寄生容量をなくすことができるという利点を得られる。また、制御ゲート電極のゲート長が小さくなったときの短チャネル効果を改善できるという利点も得られる。また、メタルゲート電極と高誘電率ゲート絶縁膜の各材料の選択で、制御トランジスタのしきい値電圧の調整が可能になる。
本実施の形態では、メモリセルを構成するメモリゲート電極MGおよび制御ゲート電極CGのうち、メモリゲート電極MGは、いわゆるゲートファーストプロセスで形成し、制御ゲート電極CGは、いわゆるゲートラストプロセスで形成する。
図42〜図52は、本実施の形態2における半導体装置の製造工程中の要部断面図である。本実施の形態2では、上記実施の形態1との相違点を中心に説明し、上記実施の形態1と同様な点については、その繰り返しの説明は省略する。
IL1 層間絶縁膜
MG メモリゲート電極
Claims (15)
- 不揮発性メモリのメモリセルを備える半導体装置の製造方法であって、
(a)半導体基板を用意する工程、
(b)前記半導体基板上に、第1絶縁膜を介して、ダミーゲート電極と前記ダミーゲート電極上の第1キャップ絶縁膜とを有する第1積層体を形成する工程、
(c)前記第1積層体と第2絶縁膜を介して隣り合うように、前記半導体基板上に、前記第2絶縁膜を介して、前記メモリセル用の第1ゲート電極と前記第1ゲート電極上の第2キャップ絶縁膜とを有する第2積層体を形成する工程、
ここで、前記第2絶縁膜は、内部に電荷蓄積部を有し、
(d)前記第1積層体および前記第2積層体を覆うように、第1層間絶縁膜を形成する工程、
(e)前記第1層間絶縁膜と前記第1および第2キャップ絶縁膜とを研磨して、前記ダミーゲート電極および前記第1ゲート電極を露出させる工程、
(f)前記(e)工程後、前記ダミーゲート電極をエッチングにより除去する工程、
(g)前記(f)工程で前記ダミーゲート電極が除去された領域である第1溝内に、前記メモリセル用の第2ゲート電極を形成する工程、
を有し、
前記ダミーゲート電極は、ノンドープまたはn型のシリコン膜からなり、
前記第1ゲート電極は、p型のシリコン膜からなり、
前記(f)工程では、前記ダミーゲート電極と前記第1ゲート電極とが露出された状態で、前記ダミーゲート電極に比べて前記第1ゲート電極がエッチングされにくい条件でエッチングを行って、前記ダミーゲート電極を除去する、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記ダミーゲート電極は、n型のシリコン膜からなる、半導体装置の製造方法。 - 請求項2記載の半導体装置の製造方法において、
前記ダミーゲート電極のn型不純物濃度は、1×1020/cm3以上である、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記第1ゲート電極のp型不純物濃度は、1×1020/cm3以上である、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(f)工程では、ウェットエッチングにより前記ダミーゲート電極を除去する、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(f)工程では、アンモニア水を用いたウェットエッチングにより前記ダミーゲート電極を除去する、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(f)工程では、APMを用いた第1ウェットエッチング処理と、前記第1ウェットエッチング処理の後のアンモニア水を用いた第2ウェットエッチング処理とにより、前記ダミーゲート電極を除去する、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(f)工程では、前記ダミーゲート電極と前記第1ゲート電極とが露出された状態で、前記ダミーゲート電極に比べて前記第1ゲート電極、前記第1絶縁膜、前記第2絶縁膜および前記第1層間絶縁膜がエッチングされにくい条件でエッチングを行って、前記ダミーゲート電極を除去する、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記第2ゲート電極は、メタルゲート電極である、半導体装置の製造方法。 - 請求項9記載の半導体装置の製造方法において、
前記(g)工程では、前記第1溝に、高誘電率絶縁膜を介して前記第2ゲート電極が形成される、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(c)工程後で、前記(d)工程前に、
(c1)イオン注入法により、前記半導体基板に前記メモリセルのソースまたはドレイン用の第1半導体領域を形成する工程、
を更に有する、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(a)工程後で、前記(b)工程前に、
(a1)前記半導体基板の上面に、前記半導体基板の一部からなり、前記半導体基板の上面に沿う第1方向に延在する突出部を形成する工程、
(a2)前記半導体基板上に、前記突出部を囲むように、素子分離膜を形成する工程、
を更に有し、
前記(b)工程では、前記半導体基板の前記突出部上に、前記第1絶縁膜を介して、前記第1積層体が形成され、
前記(c)工程では、前記第1積層体と前記第2絶縁膜を介して隣り合うように、前記半導体基板の前記突出部上に前記第2絶縁膜を介して前記第2積層体が形成される、半導体装置の製造方法。 - 不揮発性メモリのメモリセルを備える半導体装置の製造方法であって、
(a)半導体基板を用意する工程、
(b)前記半導体基板上に、第1絶縁膜を介して、ダミーゲート電極を形成する工程、
(c)前記ダミーゲート電極と隣り合うように、前記半導体基板上に、内部に電荷蓄積部を有する第2絶縁膜を介して前記メモリセル用の第1ゲート電極を形成する工程、
(d)前記ダミーゲート電極および前記第1ゲート電極を覆うように、第1層間絶縁膜を形成する工程、
(e)前記第1層間絶縁膜を研磨して、前記ダミーゲート電極および前記第1ゲート電極を露出させる工程、
(f)前記(e)工程後、前記ダミーゲート電極をエッチングにより除去する工程、
(g)前記(f)工程で前記ダミーゲート電極が除去された領域である第1溝内に、前記メモリセル用の第2ゲート電極を形成する工程、
を有し、
前記ダミーゲート電極は、ノンドープまたはn型のシリコン膜からなり、
前記第1ゲート電極は、n型の第1シリコン膜と前記第1シリコン膜上のp型の第2シリコン膜との積層膜からなり、
前記(f)工程では、前記ダミーゲート電極と前記第1ゲート電極の前記第2シリコン膜とが露出された状態で、前記ダミーゲート電極に比べて前記第1ゲート電極の前記第2シリコン膜がエッチングされにくい条件でエッチングを行って、前記ダミーゲート電極を除去する、半導体装置の製造方法。 - 請求項13記載の半導体装置の製造方法において、
前記ダミーゲート電極は、n型のシリコン膜からなる、半導体装置の製造方法。 - 請求項13記載の半導体装置の製造方法において、
(h)前記(g)工程後、前記第1ゲート電極の前記第2シリコン膜の上部に金属シリサイド層を形成する工程、
を更に有する、半導体装置の製造方法。
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JP6297860B2 (ja) | 2014-02-28 | 2018-03-20 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
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JP5937172B2 (ja) * | 2014-11-05 | 2016-06-22 | ルネサスエレクトロニクス株式会社 | 半導体装置および半導体装置の製造方法 |
JP6220479B2 (ja) | 2015-03-17 | 2017-10-25 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
CN113314537A (zh) * | 2015-12-18 | 2021-08-27 | 株式会社佛罗迪亚 | 存储器单元、非易失性半导体存储装置及非易失性半导体存储装置的制造方法 |
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