TWI782941B - 製作ｐ型場效電晶體的方法 - Google Patents

製作ｐ型場效電晶體的方法 Download PDF

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TWI782941B
TWI782941B TW107101053A TW107101053A TWI782941B TW I782941 B TWI782941 B TW I782941B TW 107101053 A TW107101053 A TW 107101053A TW 107101053 A TW107101053 A TW 107101053A TW I782941 B TWI782941 B TW I782941B
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substrate
layer
gate
gate structure
germanium
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TW201931443A (zh
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劉仕佑
温在宇
李靜宜
蕭雅茵
吳誌強
劉毓鈞
陳俤彬
陳紹平
馬煥淇
游建文
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聯華電子股份有限公司
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Priority to US15/893,681 priority patent/US10651275B2/en
Publication of TW201931443A publication Critical patent/TW201931443A/zh
Priority to US16/836,953 priority patent/US11271078B2/en
Priority to US17/580,622 priority patent/US11664425B2/en
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Abstract

本發明揭露一種製作P型場效電晶體的方法，其主要先提供一基底，然後形成一襯墊層於基底上，形成一井區於基底內，進行一離子佈植製程將鍺離子植入基底內以形成一通道區，再進行一退火製程將該通道區分隔為一上半部以及一下半部。隨後去除襯墊層，形成一閘極結構於基底上，再形成一輕摻雜汲極於閘極結構兩側。

Description

製作P型場效電晶體的方法
本發明是關於一種金氧半導體元件及其製作方法，尤指一種利用離子佈植製程於基底內形成通道層的方法。
在習知半導體產業中，多晶矽係廣泛地應用於半導體元件如金氧半導體(metal-oxide-semiconductor，MOS)電晶體中，作為標準的閘極填充材料選擇。然而，隨著MOS電晶體尺寸持續地微縮，傳統多晶矽閘極因硼穿透(boron penetration)效應導致元件效能降低，及其難以避免的空乏效應(depletion effect)等問題，使得等效的閘極介電層厚度增加、閘極電容值下降，進而導致元件驅動能力的衰退等困境。因此，半導體業界更嘗試以新的閘極填充材料，例如利用功函數(work function)金屬來取代傳統的多晶矽閘極，用以作為匹配高介電常數(High-K)閘極介電層的控制電極。
然而，隨著半導體技術急速微縮到奈米等級，即便是功函數(work function)金屬閘極結構也將達到其物理與電性限制，因此可能衍生出例如閘極結構的電性不穩定，負偏壓溫度不穩定性(negative bias temperature instability,NBTI)效應等問題。
NBTI效應主要因為電荷在矽基底與矽氧化物層間介面累積，而在施加負電壓於閘極時造成影響。由於P型金氧半導體電晶體主要施加負閘極偏壓，使靠近閘極氧化物的金屬閘極面上產生電子，進而排斥N型基底表面的電子，並於N型基底表面形成電洞及閘極結構下形成電洞通道，使源極/汲極的電洞流過這個通道來傳導電流，因此NBTI對於PMOS電晶體或者包含PMOS結構的CMOS長期穩定性會造成顯著影響。
本發明一實施例揭露一種製作P型場效電晶體的方法，其主要先提供一基底，然後形成一襯墊層於基底上，形成一井區於基底內，進行一離子佈植製程將鍺離子植入基底內以形成一通道區，再進行一退火製程將該通道區分隔為一上半部以及一下半部。隨後去除襯墊層，形成一閘極結構於基底上，再形成一輕摻雜汲極於閘極結構兩側。
本發明另一實施例揭露一種P型場效電晶體，其主要包含一閘極結構設於基底上，一通道區設於閘極結構正下方之基底內以及一源極/汲極區域設於閘極結構兩側。在本實施例中，通道區較佳包含一 上半部以及一下半部，其中下半部之鍺濃度低於上半部之鍺濃度，另外上半部的深度較佳等於下半部的深度。
12:基底
14:襯墊層
16:N井
18:離子佈植製程
20:通道區
22:上半部
24:下半部
26:閘極結構
28:閘極介電層
30:閘極材料層
32:輕摻雜汲極
34:側壁子
36:源極/汲極區域
38:接觸洞蝕刻停止層
40:層間介電層
42:介質層
44:高介電常數介電層
46:功函數金屬層
48:低阻抗金屬層
第1圖至第6圖為本發明一實施例製作半導體元件之方法示意圖。
請參照第1圖至第6圖，第1圖至第6圖為本發明一實施例製作半導體元件之方法示意圖。如第1圖所示，首先提供一基底12，例如一半導體或更具體而言一矽基底或矽覆絕緣(silicon-on-insulator,SOI)基底。基底12上可定義有一電晶體區，例如本實施例用來製備一P型場效電晶體之PMOS電晶體區，且基底12中可設有例如由氧化矽所構成的淺溝隔離(shallow trench isolation,STI)隔開電晶體區。
需注意的是，本實施例雖以製作平面型(planar)場效電晶體為例，但不侷限於此，本發明又可應用至一般非平面型場效電晶體(non-planar)鰭狀結構場效電晶體，例如可於基底12上形成至少一鰭狀結構，而鰭狀結構的底部則較佳被淺溝隔離所圍繞，此實施例也屬本發明所涵蓋的範圍。
依據本發明一實施例，鰭狀結構較佳透過側壁圖案轉移(sidewall image transfer,SIT)技術製得，其程序大致包括：提供一佈局 圖案至電腦系統，並經過適當地運算以將相對應之圖案定義於光罩中。後續可透過光微影及蝕刻製程，以形成多個等距且等寬之圖案化犧牲層於基底上，使其個別外觀呈現條狀。之後依序施行沉積及蝕刻製程，以於圖案化犧牲層之各側壁形成側壁子。繼以去除圖案化犧牲層，並在側壁子的覆蓋下施行蝕刻製程，使得側壁子所構成之圖案被轉移至基底內，再伴隨鰭狀結構切割製程(fin cut)而獲得所需的圖案化結構，例如條狀圖案化鰭狀結構。
除此之外，鰭狀結構之形成方式又可包含先形成一圖案化遮罩(圖未示)於基底12上，再經過一蝕刻製程，將圖案化遮罩之圖案轉移至基底12中以形成鰭狀結構。另外，鰭狀結構之形成方式也可以先形成一圖案化硬遮罩層(圖未示)於基底12上，並利用磊晶製程於暴露出於圖案化硬遮罩層之基底12上成長出例如包含矽鍺的半導體層，而此半導體層即可作為相對應的鰭狀結構。這些形成鰭狀結構的實施例均屬本發明所涵蓋的範圍。
然後形成一襯墊層14於基底12表面。在本實施例中，襯墊層14較佳為單層結構，其中襯墊層14可選自例如由氧化矽所構成的介電材料，但不侷限於此。需注意的是，本實施例所揭露的襯墊層14雖較佳以單層結構為例，但襯墊層14的層數又可依據製程或產品需求調整，例如可於基底12表面形成複數個襯墊層，其中襯墊層可選自由氧化矽以及氮化矽所構成的群組，此實施例也屬本發明所涵蓋的範圍。
然後進行一離子佈植製程，將離子穿過襯墊層14植入基底12 內以形成一井區。以本實施例用來製備一P型場效電晶體元件為例，離子佈植製程較佳將N型摻質植入基底12內以形成一N井16。
如第2圖所示，接著進行另一離子佈植製程18，將鍺離子穿過襯墊層14植入基底12內形成一由鍺化矽所構成的通道區20。值得注意的是，本實施例將鍺離子植入基底12內的當下所形成的通道區20中鍺離子較佳呈現一梯度分佈(gradient distribution)，例如靠近襯墊層14以及通道區20交界處的鍺離子濃度較佳高於靠近通道區20以及基底12交界處的鍺離子濃度，但在此階段較高濃度區以及較低濃度區之間並無明顯分隔。
另外在本實施例中，離子佈植製程18所植入鍺離子的濃度較佳介於5x1013離子/平方公分至1x1017離子/平方公分，離子佈植製程18的能量較佳介於0.5KeV至20KeV，且離子佈植製程18較佳為一低溫離子佈植製程，例如其溫度較佳介於攝氏0度至120度。
隨後如第3圖所示，進行一退火製程活化通道區20內的鍺離子，並同時將通道區20更明顯地分隔為上半部22以及下半部24，其中上半部22的深度較佳等於下半部24的深度，例如上半部22以及下半部24的深度各較佳介於13埃至17埃或最佳約15埃，但不侷限於此。
另外在本實施例中，退火製程的溫度較佳大於攝氏1000度或更具體而言介於攝氏1000度至1200度，下半部24的鍺濃度經由退火製程擴散後較佳略低於上半部22的鍺濃度，其中上半部22的鍺濃度較佳 介於0.9x1022離子/立方公分至1.1x1022離子/立方公分或最佳約1.0x1022離子/立方公分，下半部24的鍺濃度則較佳介於0.9x1018離子/立方公分至1.1x1018離子/立方公分或最佳約1.0x1018離子/立方公分。
然後如第4圖所示，進行一蝕刻製程去除襯墊層14並暴露出基底12或通道區20表面。在本實施例中，用來去除襯墊層14的蝕刻製程較佳利用例如稀釋氫氟酸(diluted hydrofluoric acid,dHF)來去除基底12表面的襯墊層14，並可同時去除基底12表面的雜質或不純物。
如第5圖所示，接著於基底12表面上形成閘極結構26或虛置閘極。在本實施例中，閘極結構26之製作方式可依據製程需求以先閘極(gate first)製程、後閘極(gate last)製程之先高介電常數介電層(high-k first)製程以及後閘極製程之後高介電常數介電層(high-k last)製程等方式製作完成。以本實施例之後高介電常數介電層製程為例，可先依序形成一閘極介電層或介質層、一由多晶矽所構成之閘極材料層以及一選擇性硬遮罩於基底12上，並利用一圖案化光阻(圖未示)當作遮罩進行一圖案轉移製程，以單次蝕刻或逐次蝕刻步驟，去除部分閘極材料層與部分閘極介電層，然後剝除圖案化光阻，以於基底12表面上形成各由圖案化之閘極介電層28與圖案化之閘極材料層30所構成的閘極結構26。
然後在閘極結構26兩側的基底12內形成輕摻雜汲極32，於閘極結構26側壁形成至少一側壁子34，接著於側壁子34兩側的基底12中形成源極/汲極區域36及/或磊晶層，並可選擇性於源極/汲極區域36及/ 或磊晶層的表面形成一金屬矽化物(圖未示)。在本實施例中，側壁子34可為單一側壁子或複合式側壁子，例如可細部包含一偏位側壁子以及一主側壁子。其中偏位側壁子與主側壁子可包含相同或不同材料，且兩者均可選自由氧化矽、氮化矽、氮氧化矽以及氮碳化矽所構成的群組。輕摻雜汲極32以及源極/汲極區域36可依據所置備電晶體的導電型式而包含不同摻質，例如以本實施例製備P型場效電晶體為例輕摻雜汲極32以及源極/汲極區域36較佳包含P型摻質。
接著先形成一接觸洞蝕刻停止層38並覆蓋閘極結構26，再形成一層間介電層40於接觸洞蝕刻停止層38上。然後進行一平坦化製程，例如利用化學機械研磨(chemical mechanical polishing,CMP)去除部分層間介電層40以及部分接觸洞蝕刻停止層38並暴露出由多晶矽材料所構成的閘極材料層30，使閘極材料層30上表面與層間介電層40上表面齊平。
如第6圖所示，隨後進行一金屬閘極置換製程將閘極結構26轉換為金屬閘極。舉例來說，可先進行一選擇性之乾蝕刻或濕蝕刻製程，例如利用氨水(ammonium hydroxide,NH4OH)或氫氧化四甲銨(Tetramethylammonium Hydroxide,TMAH)等蝕刻溶液來去除閘極結構26中的閘極材料層30甚至閘極介電層28，以於層間介電層40中形成凹槽(圖未示)。
接著依序形成一選擇性的介質層42或閘極介電層、一高介電常數介電層44、一功函數金屬層46以及一低阻抗金屬層48於凹槽內， 然後進行一平坦化製程，例如利用CMP去除部分低阻抗金屬層48、部分功函數金屬層46以及部分高介電常數介電層44以形成由金屬閘極所構成的閘極結構26。以本實施例利用後高介電常數介電層製程所製作的閘極結構26為例，所形成的金屬閘極較佳包含一介質層42或閘極介電層、一U型的高介電常數介電層44、一U型的功函數金屬層46以及一低阻抗金屬層48。
在本實施例中，高介電常數介電層44包含介電常數大於4的介電材料，例如選自氧化鉿(hafnium oxide，HfO2)、矽酸鉿氧化合物(hafnium silicon oxide,HfSiO4)、矽酸鉿氮氧化合物(hafnium silicon oxynitride,HfSiON)、氧化鋁(aluminum oxide,Al2O3)、氧化鑭(lanthanum oxide,La2O3)、氧化鉭(tantalum oxide,Ta2O5)、氧化釔(yttrium oxide,Y2O3)、氧化鋯(zirconium oxide,ZrO2)、鈦酸鍶(strontium titanate oxide,SrTiO3)、矽酸鋯氧化合物(zirconium silicon oxide,ZrSiO4)、鋯酸鉿(hafnium zirconium oxide,HfZrO4)、鍶鉍鉭氧化物(strontium bismuth tantalate,SrBi2Ta2O9,SBT)、鋯鈦酸鉛(lead zirconate titanate,PbZrxTi1-xO3,PZT)、鈦酸鋇鍶(barium strontium titanate,BaxSr1-xTiO3,BST)、或其組合所組成之群組。
功函數金屬層46較佳用以調整形成金屬閘極之功函數，使其適用於N型電晶體(NMOS)或P型電晶體(PMOS)。若電晶體為N型電晶體，功函數金屬層46可選用功函數為3.9電子伏特(eV)~4.3eV的金屬材料，如鋁化鈦(TiAl)、鋁化鋯(ZrAl)、鋁化鎢(WAl)、鋁化鉭(TaAl)、鋁化鉿(HfAl)或TiAlC(碳化鈦鋁)等，但不以此為限；若電晶體為P型 電晶體，功函數金屬層46可選用功函數為4.8eV~5.2eV的金屬材料，如氮化鈦(TiN)、氮化鉭(TaN)或碳化鉭(TaC)等，但不以此為限。功函數金屬層46與低阻抗金屬層48之間可包含另一阻障層(圖未示)，其中阻障層的材料可包含鈦(Ti)、氮化鈦(TiN)、鉭(Ta)、氮化鉭(TaN)等材料。低阻抗金屬層48則可選自銅(Cu)、鋁(Al)、鎢(W)、鈦鋁合金(TiAl)、鈷鎢磷化物(cobalt tungsten phosphide，CoWP)等低電阻材料或其組合。
請繼續參照第6圖，第6圖又揭露本發明一實施例之P型場效電晶體之結構示意圖。如第6圖所示，P型場效電晶體主要包含一由金屬閘極所構成的閘極結構26設於基底12上、一通道區20設於閘極結構26正下方的基底12內、一輕摻雜汲極32設於閘極結構26兩側的基底12內以及源極/汲極區域36設於側壁子34兩側的基底12內。
從細部來看，通道區20較佳由鍺化矽所構成且又包含一上半部22以及一下半部24，其中下半部24的鍺濃度較佳低於上半部22的鍺濃度，例如上半部22的鍺濃度較佳介於0.9x1022離子/立方公分至1.1x1022離子/立方公分或最佳約1.0x1022離子/立方公分，下半部24的鍺濃度則較佳介於0.9x1018離子/立方公分至1.1x1018離子/立方公分或最佳約1.0x1018離子/立方公分。另外上半部22的深度也較佳等於下半部24的深度，例如本實施例所揭露的上半部22以及下半部24的深度各較佳介於13埃至17埃或最佳約15埃，但不侷限於此。
綜上所述，本發明主要揭露一種製作矽鍺通道的方法，其主要於基底表面形成由氧化矽所構成的襯墊層之後利用離子佈植製程將 鍺離子植入基底內以形成一通道區，接著利用退火製程將通道區內的鍺離子分隔為上半部以及下半部，其中下半部的鍺濃度較佳低於上半部的鍺濃度。藉由此製作方式將通道區內的鍺離子進行濃度分離(segregate)，本發明可藉此改善P型場效電晶體施加負閘極偏壓時因NBTI效應對元件穩定性產生的影響。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
12:基底
16:N井
20:通道區
22:上半部
24:下半部
26:閘極結構
32:輕摻雜汲極
34:側壁子
36:源極/汲極區域
38:接觸洞蝕刻停止層
40:層間介電層
42:介質層
44:高介電常數介電層
46:功函數金屬層
48:低阻抗金屬層

Claims (7)

  1. 一種製作P型場效電晶體的方法，包含：提供一基底；形成一襯墊層於該基底上；進行一離子佈植製程將鍺離子通過該襯墊層植入該基底內以形成一通道區；進行一退火製程，以將該通道區分隔為一上半部以及一下半部；以及形成一閘極結構於該基底上。
  2. 如申請專利範圍第1項所述之方法，另包含：於進行該離子佈植製程之前形成一井區於該基底內。
  3. 如申請專利範圍第2項所述之方法，其中該襯墊層包含氧化矽。
  4. 如申請專利範圍第2項所述之方法，另包含於進行該退火製程之後去除該襯墊層。
  5. 如申請專利範圍第4項所述之方法，另包含：於去除該襯墊層之後形成該閘極結構於該基底上；以及形成一輕摻雜汲極於該閘極結構兩側。
  6. 如申請專利範圍第1項所述之方法，其中該下半部之鍺濃度低於該上半部之鍺濃度。
  7. 如申請專利範圍第1項所述之方法，其中該上半部之深度等於該下半部之深度。
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7176530B1 (en) * 2004-03-17 2007-02-13 National Semiconductor Corporation Configuration and fabrication of semiconductor structure having n-channel channel-junction field-effect transistor
CN102446855A (zh) * 2010-09-30 2012-05-09 富士通半导体股份有限公司 半导体器件的制造方法
US20140103429A1 (en) * 2012-10-15 2014-04-17 Taiwan Semiconductor Manufacturing Company, Ltd. Method and Structure to Boost MOSFET Performance and NBTI

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1286157C (zh) * 2002-10-10 2006-11-22 松下电器产业株式会社 半导体装置及其制造方法
US6897118B1 (en) 2004-02-11 2005-05-24 Chartered Semiconductor Manufacturing Ltd. Method of multiple pulse laser annealing to activate ultra-shallow junctions
US8471244B2 (en) * 2006-12-05 2013-06-25 Atmel Corporation Method and system for providing a metal oxide semiconductor device having a drift enhanced channel
US8946035B2 (en) * 2012-09-27 2015-02-03 Taiwan Semiconductor Manufacturing Co., Ltd. Replacement channels for semiconductor devices and methods for forming the same using dopant concentration boost
US9209181B2 (en) * 2013-06-14 2015-12-08 Globalfoundries Inc. Methods of forming transistors with retrograde wells in CMOS applications and the resulting device structures
US9680014B2 (en) * 2015-04-17 2017-06-13 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including Fin structures and manufacturing method thereof
KR102497125B1 (ko) * 2015-12-22 2023-02-07 에스케이하이닉스 주식회사 반도체장치 및 그 제조 방법
US9876015B1 (en) * 2017-02-16 2018-01-23 International Business Machines Corporation Tight pitch inverter using vertical transistors
US10510889B2 (en) * 2017-11-29 2019-12-17 Taiwan Semiconductor Manufacturing Co., Ltd. P-type strained channel in a fin field effect transistor (FinFET) device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7176530B1 (en) * 2004-03-17 2007-02-13 National Semiconductor Corporation Configuration and fabrication of semiconductor structure having n-channel channel-junction field-effect transistor
CN102446855A (zh) * 2010-09-30 2012-05-09 富士通半导体股份有限公司 半导体器件的制造方法
US20140103429A1 (en) * 2012-10-15 2014-04-17 Taiwan Semiconductor Manufacturing Company, Ltd. Method and Structure to Boost MOSFET Performance and NBTI

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