TWI776911B - 半導體元件及其製作方法 - Google Patents

半導體元件及其製作方法 Download PDF

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TWI776911B
TWI776911B TW107122765A TW107122765A TWI776911B TW I776911 B TWI776911 B TW I776911B TW 107122765 A TW107122765 A TW 107122765A TW 107122765 A TW107122765 A TW 107122765A TW I776911 B TWI776911 B TW I776911B
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single diffusion
diffusion isolation
gate
fin
region
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TW107122765A
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TW202006790A (zh
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李志成
李凱霖
陳威任
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聯華電子股份有限公司
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Priority to TW107122765A priority Critical patent/TWI776911B/zh
Priority to US16/052,600 priority patent/US10566244B2/en
Priority to US16/726,201 priority patent/US11011430B2/en
Publication of TW202006790A publication Critical patent/TW202006790A/zh
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Abstract

本發明揭露一種製作半導體元件的方法。首先提供一基底，該基底上具有一第一區域以及一第二區域，然後形成一第一鰭狀結構於基底上，形成一第一閘極結構以及一第二閘極結構於第一鰭狀結構上，利用一圖案化遮罩去除第一閘極結構以及部分第一鰭狀結構以形成一第一凹槽，接著再形成一第一介電層於第一凹槽內以形成一第一單擴散隔離結構並環繞第二閘極結構。

Description

半導體元件及其製作方法
本發明是關於一種製作半導體元件的方法，尤指一種分隔鰭狀結構以形成單擴散隔離(single diffusion break,SDB)結構的方法。
近年來，隨著場效電晶體(field effect transistors,FETs)元件尺寸持續地縮小，習知平面式(planar)場效電晶體元件之發展已面臨製程上之極限。為了克服製程限制，以非平面(non-planar)之場效電晶體元件，例如鰭狀場效電晶體(fin field effect transistor,Fin FET)元件來取代平面電晶體元件已成為目前之主流發展趨勢。由於鰭狀場效電晶體元件的立體結構可增加閘極與鰭狀結構的接觸面積，因此，可進一步增加閘極對於載子通道區域的控制，從而降低小尺寸元件面臨的汲極引發能帶降低(drain induced barrier lowering,DIBL)效應，並可以抑制短通道效應(short channel effect,SCE)。再者，由於鰭狀場效電晶體 元件在同樣的閘極長度下會具有更寬的通道寬度，因而可獲得加倍的汲極驅動電流。甚而，電晶體元件的臨界電壓(threshold voltage)亦可藉由調整閘極的功函數而加以調控。
在現行的鰭狀場效電晶體元件製程中，鰭狀結構周圍形成淺溝隔離後通常會以蝕刻方式去除部分鰭狀結構與淺溝隔離形成凹槽，然後填入絕緣物以形成單擴散隔離結構並將鰭狀結構分隔為兩部分。然而現今單擴散隔離結構與金屬閘極的製程在搭配上仍存在許多問題，因此如何改良現有鰭狀場效電晶體製程與架構即為現今一重要課題。
本發明揭露一種製作半導體元件的方法。首先提供一基底，該基底上具有一第一區域以及一第二區域，然後形成一第一鰭狀結構於基底上，形成一第一閘極結構以及一第二閘極結構於第一鰭狀結構上，利用一圖案化遮罩去除第一閘極結構以及部分第一鰭狀結構以形成一第一凹槽，接著再形成一第一介電層於第一凹槽內以形成一第一單擴散隔離結構並環繞第二閘極結構。
依據本發明一實施例又包含形成第一鰭狀結構於第一區域上以及一第二鰭狀結構於第二區域上，去除部分第二鰭狀結構以形成一第二凹槽，形成一第二介電層於第二凹槽內，平坦化第二介電層以形成第二單擴散隔離結構，形成第一閘極結構以及第二閘極結構於第 一區域以及一第三閘極結構於第二單擴散隔離結構上，形成該圖案化遮罩於第一區域以及第二區域，利用圖案化遮罩去除第一閘極結構以及部分第一鰭狀結構以形成第一凹槽，形成第一介電層於第一凹槽內並環繞第二閘極結構以及第三閘極結構，最後再進行一金屬閘極置換製程將第二閘極結構以及第三閘極結構轉換為金屬閘極。
本發明另一實施例揭露一種半導體元件，其主要包含：一基底，該基底上具有一第一區域以及一第二區域；一第一鰭狀結構設於第一區域上以及一第二鰭狀結構設於第二區域上；一第一單擴散隔離結構設於第一區域內；以及一第二單擴散隔離結構設於第二區域內，其中該第一單擴散隔離結構以及該第二單擴散隔離結構包含不同高度。
12:基底
14:NMOS區域
16:PMOS區域
18:鰭狀結構
20:鰭狀結構
22:淺溝隔離
24:單擴散隔離結構
26:單擴散隔離結構
28:凹槽
30:第一部分
32:第二部分
34:介電層
36:閘極結構
38:閘極結構
40:閘極結構
42:閘極結構
44:閘極結構
46:閘極結構
48:閘極介電層
50:閘極材料層
52:側壁子
54:源極/汲極區域
56:層間介電層
58:圖案化遮罩
60:介質層
62:高介電常數介電層
64:功函數金屬層
66:功函數金屬層
68:阻障層
70:低阻抗金屬層
72:閘極結構
74:閘極結構
76:閘極結構
78:閘極結構
80:硬遮罩
82:凹槽
84:介電層
第1圖為本發明一實施例之一半導體元件之上視圖。
第2圖至第6圖為本發明一實施例製作半導體元件之方法示意圖。
請參照第1圖至第2圖，其中第1圖為本發明一實施例製作一半導體元件之上視圖，第2圖至第6圖為本發明一實施例製作第1圖之半導體元件之方法示意圖，其中第2圖至第6圖左半部為第1圖中沿著切線AA'方向製作半導體元件之剖面示意圖，第2圖至第6圖右半部則為第1 圖中沿著切線BB'製作半導體元件之剖面示意圖。如第1圖至第2圖所示，首先提供一基底12，例如一矽基底或矽覆絕緣(SOI)基板，並於基底12上定義一第一電晶體區例如一NMOS區域14以及一第二電晶體區例如一PMOS區域16。然後分別於NMOS區域14以及PMOS區域16形成至少一鰭狀結構18於基底12上。在本實施例中，設於各電晶體區的鰭狀結構18雖以四根為例，但所設置的鰭狀結構18數量均可依據產品需求任意調整，並不侷限於此。
依據本發明之較佳實施例，鰭狀結構18較佳透過側壁圖案轉移(sidewall image transfer,SIT)等技術製得，其程序大致包括：提供一佈局圖案至電腦系統，並經過適當地運算以將相對應之圖案定義於光罩中。後續可透過光微影及蝕刻製程，以形成多個等距且等寬之圖案化犧牲層於基底上，使其個別外觀呈現條狀。之後依序施行沉積及蝕刻製程，以於圖案化犧牲層之各側壁形成側壁子。繼以去除圖案化犧牲層，並在側壁子的覆蓋下施行蝕刻製程，使得側壁子所構成之圖案被轉移至基底內，再伴隨鰭狀結構切割製程(fin cut)而獲得所需的圖案化結構，例如條狀圖案化鰭狀結構。
除此之外，鰭狀結構18之形成方式又可包含先形成一圖案化遮罩(圖未示)於基底12上，再經過一蝕刻製程，將圖案化遮罩之圖案轉移至基底12中以形成鰭狀結構18。另外，鰭狀結構18之形成方式也可以先形成一圖案化硬遮罩層(圖未示)於基底12上，並利用磊晶製程於暴露出於圖案化硬遮罩層之基底12上成長出例如包含矽鍺的半導體層，而此半導體層即可作為相對應的鰭狀結構18。這些形成鰭狀結構 18的實施例均屬本發明所涵蓋的範圍。
然後形成一淺溝隔離(shallow trench isolation,STI)22環繞鰭狀結構18。在本實施例中，形成淺溝隔離22的方式可先利用一可流動式化學氣相沉積(flowable chemical vapor deposition,FCVD)製程形成一氧化矽層於基底12上並完全覆蓋鰭狀結構18。接著利用化學機械研磨(chemical mechanical polishing,CMP)製程並搭配蝕刻製程去除部分氧化矽層，使剩餘的氧化矽層低於鰭狀結構18表面以形成淺溝隔離22。
接著於PMOS區域16形成至少一單擴散隔離結構(single diffusion break,SDB)26橫跨鰭狀結構20。在本實施例中，形成單擴散隔離結構26的步驟可先形成一圖案化遮罩(圖未示)於基底12上並覆蓋所有NMOS區域14以及部分PMOS區域16，然後利用圖案化遮罩(圖未示)進行一蝕刻製程，沿著與鰭狀結構20垂直的方向去除PMOS區域16中部分鰭狀結構20與淺溝隔離22以形成凹槽28並同時將PMOS電晶體區16的各鰭狀結構20分隔為兩部分。以第1圖中PMOS區域16所形成的凹槽28為例，凹槽28較佳將各鰭狀結構20分隔為位於單擴散隔離結構26左側的第一部分30與位於右側的第二部分32，其中所形成的凹槽28即用來定義出後續單擴散隔離結構所形成的位置。
隨後形成一介電層34於PMOS區域的凹槽28內並填滿各凹槽28，再利用一平坦化製程，例如以回蝕刻或化學機械研磨製程去除部分介電層34，使剩餘的介電層34約略切齊各鰭狀結構20的頂面以形成單擴散隔離結構26。在本實施例中，NMOS區域14與PMOS區域16 的鰭狀結構18、20較佳沿著一第一方向(例如X方向)延伸而於PMOS電晶體區16所形成的單擴散隔離結構26則沿著一與第一方向垂直的第二方向(例如Y方向)延伸。
然後分別於NMOS區域14與PMOS區域16的鰭狀結構18、20上形成閘極結構36、38、40、42、44、46。在本實施例中，閘極結構36、38、40、42、44、46之製作方式可依據製程需求以先閘極(gate first)製程、後閘極(gate last)製程之先高介電常數介電層(high-k first)製程以及後閘極製程之後高介電常數介電層(high-k last)製程等方式製作完成。以本實施例之後高介電常數介電層製程為例，可先依序形成一閘極介電層或介質層、一由多晶矽所構成之閘極材料層以及一選擇性硬遮罩於基底12上，並利用一圖案化光阻(圖未示)當作遮罩進行一圖案轉移製程，以單次蝕刻或逐次蝕刻步驟，去除部分閘極材料層與部分閘極介電層，然後剝除圖案化光阻，以於基底12上形成由圖案化之閘極介電層48與圖案化之閘極材料層50所構成的閘極結構36、38、40、42、44、46。
然後在各閘極結構36、38、40、42、44、46側壁形成至少一側壁子52，接著於側壁子52兩側的鰭狀結構18、20以及/或基底12中形成一源極/汲極區域54及/或磊晶層(圖未示)，並選擇性於源極/汲極區域54及/或磊晶層的表面形成一金屬矽化物(圖未示)。在本實施例中，各側壁子52可為單一側壁子或複合式側壁子，例如可細部包含一偏位側壁子以及一主側壁子。其中偏位側壁子與主側壁子可包含相同或不同材料，且兩者均可選自由氧化矽、氮化矽、氮氧化矽以及氮碳化矽 所構成的群組。源極/汲極區域54可依據所置備電晶體的導電型式而包含不同摻質與磊晶材料，例如NMOS區域14的源極/汲極區域54可包含碳化矽(SiC)或磷化矽(SiP)而PMOS區域16的源極/汲極區域54可包含鍺化矽(SiGe)，但均不限於此。
隨後如第3圖所示，形成一圖案化遮罩58於NMOS區域14以及PMOS區域16，其中圖案化遮罩58較佳覆蓋NMOS區域14的閘極結構38以及PMOS區域16的所有閘極結構42、44、46並暴露出NMOS區域14的閘極結構36、40頂部。然後利用圖案化遮罩58在不去除側壁子52的情況下去除閘極結構36、40以及部分鰭狀結構18以形成凹槽82。如同第2圖於PMOS區域16形成單擴散隔離結構26前所形成的凹槽28，本階段於NMOS區域14所形成的凹槽82較佳將各鰭狀結構18分隔為各凹槽82左側的第一部分30與右側的第二部分32，其中所形成的凹槽82即用來定義出後續單擴散隔離結構的位置。
如第4圖所示，接著去除圖案化遮罩58，並形成一介電層84於NMOS區域14以及PMOS區域16，其中介電層84較佳填滿凹槽82外又同時覆蓋NMOS區域14以及PMOS區域16的閘極結構38、42、44、46。
隨後如第5圖所示，進行一平坦化製程，例如利用CMP去除部分介電層84，使填入凹槽82的介電層84頂部約略切齊側壁子52頂部形成單擴散隔離結構24並同時形成層間介電層56環繞NMOS區域14以及PMOS區域16的閘極結構38、42、44、46周圍。需注意的是，由於單擴散隔離結構24與層間介電層56較佳在同一道製程形成因此兩者較 佳包含相同材料，但NMOS區域14的單擴散隔離結構24以及PMOS區域16的單擴散隔離結構26可依據製程需求包含相同或不同材料。例如在本實施例中，NMOS區域14的單擴散隔離結構24與層間介電層56較佳由氧化矽所構成而PMOS區域16的單擴散隔離結構26則由氮化矽或氮碳化矽所構成。但不侷限於此，依據本發明其他實施例NMOS區域14的單擴散隔離結構24、層間介電層56以及PMOS區域16的單擴散隔離結構26均可選自由氧化矽、氮化矽、氮碳化矽以及碳氧化矽(silicon oxycarbonitride,SiOCN)所構成的群組。
此外，本實施例於NMOS區域14所形成的單擴散隔離結構24底部雖較佳切齊PMOS區域16中單擴散隔離結構26的底部同時單擴散隔離結構24頂部又切齊層間介電層56，但不侷限於此，依據本發明其他實施例NMOS區域14的單擴散隔離結構24又可在其頂部切齊層間介電層56的情況下調整其底部深度，例如單擴散隔離結構24底部又可選擇略低或略高於PMOS區域16的單擴散隔離結構26底部，這些變化型均屬本發明所涵蓋的範圍。
如第6圖所示，然後進行一金屬閘極置換製程將NMOS區域14的閘極結構38與PMOS區域16的閘極結構42、44、46轉換為金屬閘極。舉例來說，可先利用圖案化遮罩為遮罩進行一乾蝕刻或濕蝕刻製程，例如利用氨水(ammonium hydroxide,NH4OH)或氫氧化四甲銨(Tetramethylammonium Hydroxide,TMAH)等蝕刻溶液來去除NMOS區域14閘極結構38與PMOS區域16閘極結構42、44、46中的閘極材料層50甚至閘極介電層48，以於NMOS區域14與PMOS區域16的層間介電層 56中形成複數個凹槽(圖未示)。之後依序形成另一選擇性介質層60或閘極介電層、一高介電常數介電層62、一選擇性阻障層(圖未示)以及一功函數金屬層64於NMOS區域14與PMOS區域16的凹槽內，形成另一圖案化遮罩(圖未示)例如圖案化光阻覆蓋NMOS區域14，利用蝕刻去除PMOS區域16的功函數金屬層64，去除圖案化遮罩後再形成另一功函數金屬層66於NMOS區域14與PMOS區域16。然後再依序形成另一阻障層68例如上阻障層以及一低阻抗金屬層70於凹槽內並填滿凹槽。
在本實施例中，高介電常數介電層62包含介電常數大於4的介電材料，例如選自氧化鉿(hafnium oxide，HfO2)、矽酸鉿氧化合物(hafnium silicon oxide,HfSiO4)、矽酸鉿氮氧化合物(hafnium silicon oxynitride,HfSiON)、氧化鋁(aluminum oxide,Al2O3)、氧化鑭(lanthanum oxide,La2O3)、氧化鉭(tantalum oxide,Ta2O5)、氧化釔(yttrium oxide,Y2O3)、氧化鋯(zirconium oxide,ZrO2)、鈦酸鍶(strontium titanate oxide,SrTiO3)、矽酸鋯氧化合物(zirconium silicon oxide,ZrSiO4)、鋯酸鉿(hafnium zirconium oxide,HfZrO4)、鍶鉍鉭氧化物(strontium bismuth tantalate,SrBi2Ta2O9,SBT)、鋯鈦酸鉛(lead zirconate titanate,PbZrxTi1-xO3,PZT)、鈦酸鋇鍶(barium strontium titanate,BaxSr1-xTiO3,BST)、或其組合所組成之群組。
功函數金屬層64較佳用以調整形成金屬閘極之功函數，使其適用於N型電晶體(NMOS)或P型電晶體(PMOS)。在本實施例中，功函數金屬層64較佳為N型功函數金屬層，其可選用功函數為3.9電子伏特(eV)~4.3eV的金屬材料，如鋁化鈦(TiAl)、鋁化鋯(ZrAl)、鋁化鎢 (WAl)、鋁化鉭(TaAl)、鋁化鉿(HfAl)或TiAlC(碳化鈦鋁)等，但不以此為限。功函數金屬層66則較佳為P型功函數金屬層，其可選用功函數為4.8eV~5.2eV的金屬材料，如氮化鈦(TiN)、氮化鉭(TaN)或碳化鉭(TaC)等，但不以此為限。另外設於高介電常數介電層62與功函數金屬層64之間的阻障層以及設於功函數金屬層66與低阻抗金屬層70之間的阻障層68可包含鈦(Ti)、氮化鈦(TiN)、鉭(Ta)、氮化鉭(TaN)等材料。低阻抗金屬層70則可選自銅(Cu)、鋁(Al)、鎢(W)、鈦鋁合金(TiAl)、鈷鎢磷化物(cobalt tungsten phosphide,CoWP)等低電阻材料或其組合。
接著進行一平坦化製程，例如利用CMP去除NMOS區域14與PMOS區域16的部分低阻抗金屬層70、部分阻障層68、部分功函數金屬層66、部分功函數金屬層64、部分高介電常數介電層62以及設於PMOS區域16的圖案化遮罩58，以於NMOS區域14單擴散隔離結構24之間的鰭狀結構18上形成由金屬閘極72所構成的閘極結構38並同時於PMOS區域16的單擴散隔離結構24正上方與鰭狀結構20上方形成由金屬閘極74、76、78所構成的閘極結構42、44、46。
之後可去除部分由金屬閘極與多晶矽閘極所構成的閘極結構38、42、44、46，再進行一沉積製程以及一平坦化製程，以於各閘極結構38、42、44、46上形成由例如氮化矽所構成的硬遮罩80。然後可依據製程需求進行後續接觸插塞製程與金屬內連線製程，例如可於NMOS區域14與PMOS區域16的層間介電層56內形成接觸插塞電連接源極/汲極區域54，並於層間介電層56上形成金屬內連線電連接接觸插塞。至此即完成本發明之半導體元件的製作。
請繼續參照第6圖，第6圖另揭露本發明一實施例之半導體元件之結構示意圖。如第6圖所示，半導體元件主要包含一NMOS區域14以及PMOS區域16定義於基底12上，鰭狀結構18設於NMOS區域14以及鰭狀結構20設於PMOS區域16，單擴散隔離結構24設於NMOS區域14內以及單擴散隔離結構26設於PMOS區域16內，閘極結構38設於NMOS區域14的鰭狀結構18上，閘極結構42、44、46設於PMOS區域16的鰭狀結構20上以及層間介電層56環繞閘極結構38、42、44、46。
在本實施例中，單擴散隔離結構24以及單擴散隔離結構26較佳包含不同高度，其中單擴散隔離結構24以及單擴散隔離結構26底部較佳彼此切齊於基底12內，同時單擴散隔離結構24上表面較佳切齊層間介電層56以及閘極結構38、42、44、46上表面而單擴散隔離結構26上表面則切齊基底12或鰭狀結構20上表面。另外單擴散隔離結構24較佳與層間介電層56包含相同材料但與單擴散隔離結構26包含不同材料，例如本實施例中單擴散隔離結構24較佳與層間介電層56較佳由氧化矽所構成而單擴散隔離結構26則由氮化矽或氮碳化矽所構成。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
12:基底
14:NMOS區域
16:PMOS區域
18:鰭狀結構
20:鰭狀結構
24:單擴散隔離結構
26:單擴散隔離結構
34:介電層
38:閘極結構
42:閘極結構
44:閘極結構
46:閘極結構
52:側壁子
54:源極/汲極區域
56:層間介電層
60:介質層
62:高介電常數介電層
64:功函數金屬層
66:功函數金屬層
68:阻障層
70:低阻抗金屬層
72:閘極結構
74:閘極結構
76:閘極結構
78:閘極結構
80:硬遮罩
84:介電層

Claims (18)

  1. 一種製作半導體元件的方法，包含：提供一基底，該基底上具有一第一區域以及一第二區域；形成一第一鰭狀結構於該第一區域及一第二鰭狀結構於該第二區域；形成一第二單擴散隔離結構於該第二鰭狀結構中；形成一第一閘極結構以及一第二閘極結構於該第一鰭狀結構上；利用一圖案化遮罩去除該第一閘極結構以及部分該第一鰭狀結構以形成一第一凹槽；以及形成一第一介電層於該第一凹槽內以形成一第一單擴散隔離結構並環繞該第二閘極結構，其中該第一單擴散隔離結構的上表面切齊該第二閘極結構的上表面，且該第二單擴散隔離結構的上表面切齊該第二鰭狀結構的上表面。
  2. 如申請專利範圍第1項所述之方法，另包含：去除部分該第二鰭狀結構以形成一第二凹槽；形成一第二介電層於該第二凹槽內；以及平坦化該第二介電層以形成該第二單擴散隔離結構。
  3. 如申請專利範圍第2項所述之方法，其中該第一鰭狀結構以及該第二鰭狀結構係沿著一第一方向延伸且該第一單擴散隔離結構以及該第二單擴散隔離結構係沿著一第二方向延伸。
  4. 如申請專利範圍第3項所述之方法，其中該第一方向垂直該第二方向。
  5. 如申請專利範圍第2項所述之方法，其中該第一單擴散隔離結構以及該第二單擴散隔離結構包含不同材料。
  6. 如申請專利範圍第2項所述之方法，另包含：形成該第一閘極結構以及該第二閘極結構於該第一區域以及一第三閘極結構於該第二單擴散隔離結構上；形成該圖案化遮罩於該第一區域以及該第二區域；利用該圖案化遮罩去除該第一閘極結構以及部分第一鰭狀結構以形成該第一凹槽；形成該第一介電層於該第一凹槽內並環繞該第二閘極結構以及該第三閘極結構；以及進行一金屬閘極置換製程將該第二閘極結構以及該第三閘極結構轉換為金屬閘極。
  7. 如申請專利範圍第1項所述之方法，另包含進行一流動式化學氣相沉積(flowable chemical vapor deposition,FCVD)製程以形成該第一介電層。
  8. 如申請專利範圍第1項所述之方法，另包含平坦化該第一介電層以形成該第一單擴散隔離結構以及一層間介電層於該第二閘極結構周圍。
  9. 如申請專利範圍第1項所述之方法，其中該第一區域包含一NMOS區域且該第二區域包含一PMOS區域。
  10. 如申請專利範圍第1項所述之方法，其中形成該第二單擴散隔離結構於該第二鰭狀結構中後，再形成該第一閘極結構以及該第二閘極結構於該第一鰭狀結構上，之後再形成該第一單擴散隔離結構。
  11. 一種半導體元件，包含：一基底，該基底上具有一第一區域以及一第二區域；一第一鰭狀結構設於該第一區域上以及一第二鰭狀結構設於該第二區域上；一第一閘極結構設於該第一區域之該第一鰭狀結構上；一第一單擴散隔離結構設於該第一區域內；以及一第二單擴散隔離結構設於該第二區域內，其中該第一單擴散隔離結構以及該第二單擴散隔離結構包含不同高度，該第一單擴散隔離結構的上表面切齊該第一閘極結構的上表面，且該第二單擴散隔離結構的上表面切齊該第二鰭狀結構的上表面。
  12. 如申請專利範圍第11項所述之半導體元件，其中該第一鰭狀結構以及該第二鰭狀結構係沿著一第一方向延伸且該第一單擴散隔離結構以及該第二單擴散隔離結構係沿著一第二方向延伸。
  13. 如申請專利範圍第12項所述之半導體元件，其中該第一方 向垂直該第二方向。
  14. 如申請專利範圍第11項所述之半導體元件，其中該第一單擴散隔離結構以及該第二單擴散隔離結構包含不同材料。
  15. 如申請專利範圍第11項所述之半導體元件，另包含：一第二閘極結構設於該第二區域之該第二鰭狀結構上；一第三閘極結構設於該第二區域之該第二單擴散隔離結構上；以及一層間介電層環繞該第一閘極結構、該第二閘極結構以及該第三閘極結構。
  16. 如申請專利範圍第15項所述之半導體元件，其中該層間介電層的上表面切齊該第一閘極結構、該第二閘極結構以及該第三閘極結構上表面。
  17. 如申請專利範圍第15項所述之半導體元件，其中該第一單擴散隔離結構的上表面切齊該層間介電層的上表面。
  18. 如申請專利範圍第15項所述之半導體元件，其中該第一單擴散隔離結構的上表面切齊該第二閘極結構以及該第三閘極結構的上表面。
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