TW202135227A - 半導體元件及其製作方法 - Google Patents

半導體元件及其製作方法 Download PDF

Info

Publication number
TW202135227A
TW202135227A TW109107840A TW109107840A TW202135227A TW 202135227 A TW202135227 A TW 202135227A TW 109107840 A TW109107840 A TW 109107840A TW 109107840 A TW109107840 A TW 109107840A TW 202135227 A TW202135227 A TW 202135227A
Authority
TW
Taiwan
Prior art keywords
work function
metal layer
function metal
dielectric layer
layer
Prior art date
Application number
TW109107840A
Other languages
English (en)
Inventor
謝天宇
王冠迪
陳漢珍
李坤憲
Original Assignee
聯華電子股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 聯華電子股份有限公司 filed Critical 聯華電子股份有限公司
Priority to TW109107840A priority Critical patent/TW202135227A/zh
Priority to US16/843,880 priority patent/US11488870B2/en
Publication of TW202135227A publication Critical patent/TW202135227A/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/82345—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823456—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Composite Materials (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

本發明揭露一種製作半導體元件的方法。首先提供一基底，該基底包含第一區域、第二區域以及第三區域，然後形成第一閘極結構於第一區域上、第二閘極結構於第二區域上以及第三閘極結構於第三區域上，形成一層間介電層環繞第一閘極結構、第二閘極結構以及第三閘極結構，去除第一閘極結構、第二閘極結構以及第三閘極結構以形成第一凹槽、第二凹槽以及第三凹槽，形成第一介質層於第一凹槽、第二凹槽以及第三凹槽內，去除第二凹槽內之第一介質層，再形成第二介質層於第二凹槽內。

Description

半導體元件及其製作方法
本發明是關於製作一種半導體元件的方法，尤指一種形成不同厚度介質層的方法。
在習知半導體產業中，多晶矽係廣泛地應用於半導體元件如金氧半導體(metal-oxide-semiconductor, MOS)電晶體中，作為標準的閘極填充材料選擇。然而，隨著MOS電晶體尺寸持續地微縮，傳統多晶矽閘極因硼穿透(boron penetration)效應導致元件效能降低，及其難以避免的空乏效應(depletion effect)等問題，使得等效的閘極介電層厚度增加、閘極電容值下降，進而導致元件驅動能力的衰退等困境。因此，半導體業界更嘗試以新的閘極填充材料，例如利用功函數(work function)金屬來取代傳統的多晶矽閘極，用以作為匹配高介電常數(High-K)閘極介電層的控制電極。
然而在現今金屬閘極電晶體製作過程中，特別是輸入/輸出區與核心區因預設介質層厚度的影響在電性表現上均有其不理想之處，例如輸入/輸出區因介質層厚度高容易造成元件運作速度降低而核心區的部分則因介質層厚度低導致嚴重漏電流。因此如何改良現行金屬閘極製程以解決此問題即為現今一重要課題。
本發明一實施例揭露一種製作半導體元件的方法。首先提供一基底，該基底包含第一區域、第二區域以及第三區域，然後形成第一閘極結構於第一區域上、第二閘極結構於第二區域上以及第三閘極結構於第三區域上，形成一層間介電層環繞第一閘極結構、第二閘極結構以及第三閘極結構，去除第一閘極結構、第二閘極結構以及第三閘極結構以形成第一凹槽、第二凹槽以及第三凹槽，形成第一介質層於第一凹槽、第二凹槽以及第三凹槽內，去除第二凹槽內之第一介質層，再形成第二介質層於第二凹槽內。
本發明另一實施例揭露一種半導體元件，其主要包含第一區域、第二區域以及第三區域設於基底上、第一金屬閘極設於第一區域以及第二金屬閘極設於第二區域。第一金屬閘極包含第一介質層以及第一功函數金屬層設於第一介質層上，第二金屬閘極則包含第二介質層以及第二功函數金屬層設於第二介質層上，其中第一介質層及第二介質層包含不同厚度且第一功函數金屬層及第二功函數金屬層包含不同功函數。
請參照第1圖至第8圖，第1圖至第8圖為本發明較佳實施例製作一半導體元件之方法示意圖。如第1圖所示，首先提供一基底12，例如一矽基底或矽覆絕緣(SOI)基板，其上定義有三個或三個以上的電晶體區，例如包括區域14、區域16及區域18。在本實施例中，三個區域14、16、18較佳為相同導電型式之電晶體區，例如均為PMOS電晶體區或均為NMOS電晶體區，且三個區域14、16、18分別預定為後續製作不同臨界電壓(threshold voltage)之閘極結構。更具體而言，區域14包含一輸入/輸出區，區域16較佳為中等閘極區，而區域18則包含一核心區。基底12的各電晶體區上皆具有至少一鰭狀結構20及一絕緣層(圖未示)，其中鰭狀結構20之底部係被絕緣層，例如氧化矽所包覆而形成淺溝隔離。需注意的是，本實施例雖以製作鰭狀結構場效電晶體為例，但不侷限於此，本發明又可應用至一般平面型場效電晶體，此實施例也屬本發明所涵蓋的範圍。
依據本發明之較佳實施例，鰭狀結構20較佳透過側壁圖案轉移(sidewall image transfer, SIT)技術製得，其程序大致包括：提供一佈局圖案至電腦系統，並經過適當地運算以將相對應之圖案定義於光罩中。後續可透過光微影及蝕刻製程，以形成多個等距且等寬之圖案化犧牲層於基底上，使其個別外觀呈現條狀。之後依序施行沉積及蝕刻製程，以於圖案化犧牲層之各側壁形成側壁子。繼以去除圖案化犧牲層，並在側壁子的覆蓋下施行蝕刻製程，使得側壁子所構成之圖案被轉移至基底內，再伴隨鰭狀結構切割製程(fin cut)而獲得所需的圖案化結構，例如條狀圖案化鰭狀結構。
除此之外，鰭狀結構20之形成方式又可包含先形成一圖案化遮罩(圖未示)於基底12上，再經過一蝕刻製程，將圖案化遮罩之圖案轉移至基底12中以形成鰭狀結構20。另外，鰭狀結構20之形成方式另也可以是先製作一圖案化硬遮罩層(圖未示)於基底12上，並利用磊晶製程於暴露出於圖案化硬遮罩層之基底12上成長出例如包含矽鍺的半導體層，而此半導體層即可作為相對應的鰭狀結構20。這些形成鰭狀結構20的實施例均屬本發明所涵蓋的範圍。
接著可於基底12上形成閘極結構或虛置閘極22。在本實施例中，形成虛置閘極22的方式較佳依序形成一閘極介電層、一閘極材料層以及一選擇性硬遮罩於基底12上，並利用一圖案化光阻(圖未示)當作遮罩進行一圖案轉移製程，以單次蝕刻或逐次蝕刻步驟，去除部分閘極材料層與部分閘極介電層，然後剝除圖案化光阻，以於區域14、16、18的鰭狀結構20上形成至少一由圖案化之閘極介電層24與圖案化之閘極材料層26所構成的虛置閘極22或閘極結構。在本實施例中，閘極介電層24可包含氧化矽而閘極材料層26可包含多晶矽，但不侷限於此。
然後在各虛置閘極22側壁形成至少一側壁子28，於側壁子28兩側的鰭狀結構20以及/或基底12中形成一源極/汲極區域30及/或磊晶層(圖未示)，並選擇性於源極/汲極區域30及/或磊晶層的表面形成一金屬矽化物(圖未示)。在本實施例中，側壁子28可為單一側壁子或複合式側壁子，例如可細部包含一偏位側壁子(圖未示)以及一主側壁子(圖未示)，且側壁子28可選自由氧化矽、氮化矽、氮氧化矽以及氮碳化矽所構成的群組，但不侷限於此。源極/汲極區域30與磊晶層可依據所置備電晶體的導電型式而包含不同摻質或不同材料。例如源極/汲極區域30可包含P型摻質或N型摻質，而磊晶層則可包含鍺化矽、碳化矽或磷化矽。
然後如第2圖所示，可選擇性形成一由氮化矽所構成的接觸洞蝕刻停止層(contact etch stop layer, CESL)32於基底12上並覆蓋虛置閘極22，再形成一層間介電層34於CESL 32上。接著進行一平坦化製程，例如利用化學機械研磨(chemical mechanical polishing, CMP)去除部分層間介電層34與部分接觸洞蝕刻停止層32並暴露出由多晶矽材料所構成的閘極材料層26，使各區域14、16、18的閘極材料層26上表面與層間介電層34上表面齊平。
隨後進行一金屬閘極置換製程將閘極結構22轉換為金屬閘極。例如第3圖所示，可先進行一選擇性之乾蝕刻或濕蝕刻製程，例如利用氨水(ammonium hydroxide, NH4 OH)或氫氧化四甲銨(Tetramethylammonium Hydroxide, TMAH)等蝕刻溶液來去除虛置閘極22或閘極結構中的閘極材料層26，以於層間介電層34中形成凹槽52、54、56。
然後如第4圖所示，形成一介質層58於各凹槽52、54、56內，其中介質層58較佳包含氧化矽，且在此階段形成於各凹槽52、54、56中的介質層58均具有相同厚度例如但不侷限於5-10埃。
如第5圖所示，接著先形成一圖案化遮罩(圖未示)於區域14、18上，以圖案化遮罩為遮罩利用蝕刻去除凹槽54內的介質層58，去除圖案化光阻，再形成一介質層60於三個凹槽52、54、56內。需注意的，由於凹槽52及凹槽56內均堆疊兩層介質層58、60而凹槽54內僅堆疊一層介質層60，因此凹槽52、56內的總介質層厚度較佳大於或更具體而言約略凹槽54內總介質層厚度的兩倍。
隨後如第6圖所示，形成另一圖案化遮罩(圖未示)並覆蓋區域14與區域16，再以圖案化遮罩為遮罩利用蝕刻去除區域18下凹槽56內的所有介質層包括介質層60及介質層58。接著去除圖案化遮罩，再形成一介質層62於三個凹槽52、54、56內，其中介質層58、60、62較佳包含相同材料例如均包含氧化矽。在此階段，由於區域14的凹槽52內總共堆疊三層介質層58、60、62、區域16的凹槽54內總共堆疊兩層介質層60、62而區域18的凹槽56內則總共堆疊一層介質層62且每一層介質層的厚度均約略相等，因此凹槽52內的總介質層厚度較佳大於凹槽54內的總介質層厚度且凹槽54內的總介質層厚度又大於凹槽56內的總介質層厚度。在本實施例中，凹槽52內的總介質層厚度約介於30-60埃，凹槽54內的總介質層厚度約介於10-20埃，而凹槽56內的總介質層厚度則介於5-10埃。
之後如第7圖所示，依序形成一高介電常數介電層38、一選擇性底部金屬阻隔層(bottom barrier metal, BBM)40、一功函數金屬層42以及一低阻抗金屬層44於各凹槽52、54、56內，然後進行一平坦化製程，例如利用CMP去除部分低阻抗金屬層44、部分功函數金屬層42、部分底部金屬阻隔層40以及部分高介電常數介電層38以形成金屬閘極46於各區域14、16、18。
需注意的是，除了前述於各區域14、16、18形成具有不同厚度的介質層之外，本發明又可同時於各區域14、16、18中形成具有不同功函數的功函數金屬層42，其中所謂不同功函數可包含功函數金屬層42之間具有不同材料以及/或不同厚度且當功函數金屬層42之間具有不同厚度時所謂不同厚度又可包含其中一者小於或大於另一者。舉例來說，區域14的三層介質層58、60、62上可搭配具有第一功函數的功函數金屬層42，區域16的介質層60、62上可搭配具有第二功函數的功函數金屬層42，而區域18的介質層62上可搭配具有第三功函數的功函數金屬層42，其中第一功函數可不同於第二功函數但其中一者又可相同於第三功函數或第一功函數、第二功函數及第三功函數三者均不同。
在上述實施例中，於各區域14、16、18中形成不同功函數包括不同材料或不同厚度之功函數金屬層42的方法可選擇先沉積一功函數金屬層於各凹槽52、54、56後再分別以蝕刻去除特定區域的部分功函數金屬層42，藉此調整功函數金屬層42於各區域14、16、18的厚度。舉例來說，可先沉積一功函數金屬層於區域14、16、18中的各凹槽52、54、56，然後形成一圖案化遮罩，例如圖案化光阻於區域18，接著去除未被圖案化光阻所遮蔽之區域14與區域16上的部分功函數金屬層42，使區域18上的功函數金屬層厚度大於區域14、16上的功函數金屬層42厚度。隨後可再形成另一圖案化光阻覆蓋區域16、18，並利用另一道蝕刻去除區域14上的部分功函數金屬層42，如此便可得到三種不同厚度的功函數金屬層42，即區域18上的功函數金屬層42厚度大於區域16上的功函數金屬層42，同時區域16上的功函數金屬層42厚度又大於區域14上的功函數金屬層42。
在本實施例中，高介電常數介電層38包含介電常數大於4的介電材料，例如選自氧化鉿(hafnium oxide，HfO2 )、矽酸鉿氧化合物(hafnium silicon oxide, HfSiO4 )、矽酸鉿氮氧化合物(hafnium silicon oxynitride, HfSiON)、氧化鋁(aluminum oxide, Al2 O3 )、氧化鑭(lanthanum oxide, La2 O3 )、氧化鉭(tantalum oxide, Ta2 O5 )、氧化釔(yttrium oxide, Y2 O3 )、氧化鋯(zirconium oxide, ZrO2 )、鈦酸鍶（strontium titanate oxide, SrTiO3 ）、矽酸鋯氧化合物(zirconium silicon oxide, ZrSiO4 )、鋯酸鉿(hafnium zirconium oxide, HfZrO4 )、鍶鉍鉭氧化物(strontium bismuth tantalate, SrBi2 Ta2 O9 , SBT)、鋯鈦酸鉛(lead zirconate titanate, PbZrx Ti1-x O3 , PZT)、鈦酸鋇鍶(barium strontium titanate, Bax Sr1-x TiO3 , BST)、或其組合所組成之群組。底部金屬阻隔層40可選自由氮化鈦(TiN)以及氮化鉭(TaN)所構成的群組，但不侷限於此。
功函數金屬層42較佳用以調整形成金屬閘極之功函數，使其適用於N型電晶體(NMOS)或P型電晶體(PMOS)。若電晶體為N型電晶體，功函數金屬層42可選用功函數為3.9電子伏特(eV)～4.3 eV的金屬材料，如鋁化鈦(TiAl)、鋁化鋯(ZrAl)、鋁化鎢(WAl)、鋁化鉭(TaAl)、鋁化鉿(HfAl)或TiAlC (碳化鈦鋁)等，但不以此為限；若電晶體為P型電晶體，功函數金屬層42可選用功函數為4.8 eV～5.2 eV的金屬材料，如氮化鈦(TiN)、氮化鉭(TaN)或碳化鉭(TaC)等，但不以此為限。功函數金屬層42與低阻抗金屬層44之間可包含另一阻障層(圖未示)，其中阻障層的材料可包含鈦(Ti)、氮化鈦(TiN)、鉭(Ta)、氮化鉭(TaN)等材料。低阻抗金屬層44則可選自銅(Cu)、鋁(Al)、鎢(W)、鈦鋁合金(TiAl)、鈷鎢磷化物(cobalt tungsten phosphide，CoWP)等低電阻材料或其組合。
之後可選擇性去除部分高介電常數介電層38、部分底部金屬阻隔層40、部分功函數金屬層42以及部分低阻抗金屬層44形成凹槽(圖未示)，然後再填入一硬遮罩(圖未示)於凹槽內並使硬遮罩與層間介電層34表面齊平，其中硬遮罩可選自由氧化矽、氮化矽、氮氧化矽以及氮碳化矽所構成的群組。
隨後如第8圖所示，可進行一接觸插塞製程形成接觸插塞48分別電連接源極/汲極區域30。在本實施例中，形成接觸插塞48的方式可先去除部分層間介電層34與部分接觸洞蝕刻停止層32形成接觸洞(圖未示)，然後依序沉積一阻障層(圖未示)與一金屬層50於基底12上並填滿接觸洞。接著利用一平坦化製程，例如CMP去除部分金屬層50、部分阻障層甚至部分層間介電層34，以於接觸洞中形成接觸插塞48，其中接觸插塞48上表面較佳與層間介電層34上表面切齊。在本實施例中，阻障層較佳選自由鈦、鉭、氮化鈦、氮化鉭以及氮化鎢所構成的群組，金屬層50較佳選自由鋁、鈦、鉭、鎢、鈮、鉬以及銅所構成的群組，但不侷限於此。
請繼續參照第9圖，第9圖另揭露本發明一實施例之一半導體元件之結構示意圖。如第9圖所示，依據本發明又一實施例當區域14上的總介質層厚度不同於區域16上的總介質層厚度且區域16上的總介質層厚度又不同於區域18上的總介質層厚度時，位於區域14上的功函數金屬層42可與區域16上的功函數金屬層42包含不同功函數同時兩個區域14、16上的功函數金屬層42又分別與區域18上的功函數金屬層42具有不同功函數，亦即第一功函數、第二功函數及第三功函數三者均不同。其中所謂不同功函數可包含功函數金屬層42之間具有不同材料以及/或不同厚度且當功函數金屬層42之間具有不同厚度時所謂不同厚度又可包含其中一者可小於或大於另一者。
換句話說，相較於前述實施例中在區域14內將總厚度最高的介質層58、60、62搭配厚度最低的功函數金屬層42，在區域16內將總厚度中等的介質層60、62搭配厚度中等的功函數金屬層42，以及在區域18內將總厚度最低的介質層62搭配厚度最高的功函數金屬層42，依據本發明其他實施例又可在維持上述各區域14、16、18之間總介質層厚度關係的情況下任意變換所搭配的功函數金屬層42厚度，例如可在區域14內將總厚度最高的介質層58、60、62搭配厚度最高的功函數金屬層42，在區域16內將總厚度中等的介質層60、62搭配厚度中等的功函數金屬層42，以及在區域18內將總厚度最低的介質層62搭配厚度最低的功函數金屬層42，此這些化形均屬本發明所涵蓋的範圍。
一般而言，現行半導體元件中各元件區包括輸入/輸出區(如前述實施例中區域14)與核心區(如前述區域18)因預設介質層厚度的影響在電性表現上均有其不理想之處，例如輸入/輸出區因介質層厚度高容易造成元件運作速度降低而核心區的部分則因介質層厚度低導致嚴重漏電流。為了改善此現象本發明較佳於輸入/輸出區與核心區之間額外定義出一個中等閘極區(如前述實施例中的區域16)並將該區域中閘極結構的總介質層厚度控制在輸入/輸出區的總介質層厚度與核心區的總介質層厚度之間，藉此提供一相較於輸入/輸出區與核心區更平衡的電壓輸出。除此之外，本發明又可調整各區域上的總介質層厚度外同時調整後續介質層上方功函數金屬層的功函數，並藉由不同介質層的厚度搭配不同功函數組合出不同的臨界電壓輸出，其中所謂不同功函數可包含功函數金屬層之間具有不同材料以及/或不同厚度。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
12:基底 14:區域 16:區域 18:區域 20:鰭狀結構 22:虛置閘極 24:閘極介電層 26:閘極材料層 28:側壁子 30:源極/汲極區域 32:接觸洞蝕刻停止層 34:層間介電層 38:高介電常數介電層 40:底部金屬阻隔層 42:功函數金屬層 44:低阻抗金屬層 46:金屬閘極 48:接觸插塞 50:金屬層 52:凹槽 54:凹槽 56:凹槽 58:介質層 60:介質層 62:介質層
第1圖至第8圖為本發明一實施例製作一半導體元件之方法示意圖。 第9圖為本發明一實施例之一半導體元件之結構示意圖。
12:基底
14:區域
16:區域
18:區域
20:鰭狀結構
28:側壁子
30:源極/汲極區域
32:接觸洞蝕刻停止層
34:層間介電層
38:高介電常數介電層
40:底部金屬阻隔層
42:功函數金屬層
44:低阻抗金屬層
46:金屬閘極
48:接觸插塞
50:金屬層
58:介質層
60:介質層
62:介質層

Claims (16)

  1. 一種製作半導體元件的方法，其特徵在於，包含： 提供一基底，該基底包含一第一區域、一第二區域以及一第三區域； 形成一第一閘極結構於該第一區域上、一第二閘極結構於該第二區域上以及一第三閘極結構於該第三區域上； 形成一層間介電層環繞該第一閘極結構、該第二閘極結構以及該第三閘極結構； 去除該第一閘極結構、該第二閘極結構以及該第三閘極結構以形成一第一凹槽、一第二凹槽以及一第三凹槽； 形成一第一介質層於該第一凹槽、該第二凹槽以及該第三凹槽內； 去除該第二凹槽內之該第一介質層；以及 形成一第二介質層於該第二凹槽內。
  2. 如申請專利範圍第1項所述之方法，另包含： 形成該第二介質層於該第一凹槽、該第二凹槽以及該第三凹槽內； 去除該第三凹槽內之該第一介質層以及該第二介質層；以及 形成一第三介質層於該第一凹槽、該第二凹槽以及該第三凹槽內。
  3. 如申請專利範圍第2項所述之方法，其中該第二介質層以及該第三介質層包含相同材料。
  4. 如申請專利範圍第1項所述之方法，另包含： 形成一第一功函數金屬層於該第一凹槽； 形成一第二功函數金屬層於該第二凹槽； 形成一第三功函數金屬層於該第三凹槽；以及 形成一低阻抗金屬層於該第一功函數金屬層、該第二功函數金屬層以及該第三功函數金屬層上。
  5. 如申請專利範圍第4項所述之方法，其中該第一功函數金屬層、該第二功函數金屬層以及該第三功函數金屬層包含不同功函數。
  6. 如申請專利範圍第5項所述之方法，其中該第一功函數金屬層、該第二功函數金屬層以及該第三功函數金屬層包含不同材料。
  7. 如申請專利範圍第5項所述之方法，其中該第一功函數金屬層、該第二功函數金屬層以及該第三功函數金屬層包含不同厚度。
  8. 如申請專利範圍第1項所述之方法，其中該第一介質層以及該第二介質層包含相同材料。
  9. 一種半導體元件，其特徵在於，包含： 一基底包含一第一區域、一第二區域以及一第三區域； 一第一金屬閘極設於該第一區域，其中該第一金屬閘極包含： 一第一介質層；以及 一第一功函數金屬層設於該第一介質層上； 一第二金屬閘極設於該第二區域，其中該第二金屬閘極包含： 該第一介質層； 一第二介質層設於該第一介質層上；以及 一第二功函數金屬層設於該第二介質層上，其中該第一功函數金屬層以及該第二功函數金屬層包含不同功函數。
  10. 如申請專利範圍第9項所述之半導體元件，另包含一第三金屬閘極設於該第三區域，該第三金屬閘極包含： 該第一介質層； 該第二介質層設於該第一介質層上； 一第三介質層設於該第二介質層上；以及 一第三功函數金屬層設於該第三介質層上。
  11. 如申請專利範圍第10項所述之半導體元件，其中該第一功函數金屬層、該第二功函數金屬層以及該第三功函數金屬層包含不同功函數。
  12. 如申請專利範圍第11項所述之半導體元件，其中該第一功函數金屬層、該第二功函數金屬層以及該第三功函數金屬層包含不同材料。
  13. 如申請專利範圍第11項所述之半導體元件，其中該第一功函數金屬層、該第二功函數金屬層以及該第三功函數金屬層包含不同厚度。
  14. 如申請專利範圍第9項所述之半導體元件，其中該第一功函數金屬層以及該第二功函數金屬層包含不同功函數。
  15. 如申請專利範圍第14項所述之半導體元件，其中該第一功函數金屬層以及該第二功函數金屬層包含不同材料。
  16. 如申請專利範圍第14項所述之半導體元件，其中該第一功函數金屬層以及該第二功函數金屬層包含不同厚度。
TW109107840A 2020-03-10 2020-03-10 半導體元件及其製作方法 TW202135227A (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW109107840A TW202135227A (zh) 2020-03-10 2020-03-10 半導體元件及其製作方法
US16/843,880 US11488870B2 (en) 2020-03-10 2020-04-08 Semiconductor device and method for fabricating the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW109107840A TW202135227A (zh) 2020-03-10 2020-03-10 半導體元件及其製作方法

Publications (1)

Publication Number Publication Date
TW202135227A true TW202135227A (zh) 2021-09-16

Family

ID=77663771

Family Applications (1)

Application Number Title Priority Date Filing Date
TW109107840A TW202135227A (zh) 2020-03-10 2020-03-10 半導體元件及其製作方法

Country Status (2)

Country Link
US (1) US11488870B2 (zh)
TW (1) TW202135227A (zh)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7115947B2 (en) 2004-03-18 2006-10-03 International Business Machines Corporation Multiple dielectric finfet structure and method
KR102373622B1 (ko) * 2015-05-11 2022-03-11 삼성전자주식회사 반도체 장치
US10510621B2 (en) * 2018-04-13 2019-12-17 Taiwan Semiconductor Manufacturing Co., Ltd. Methods for threshold voltage tuning and structures formed thereby
US11158644B2 (en) * 2018-07-31 2021-10-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with field effect transistors of differing gate dielectric thickness on the same substrate and method of manufacturing the same

Also Published As

Publication number Publication date
US11488870B2 (en) 2022-11-01
US20210287942A1 (en) 2021-09-16

Similar Documents

Publication Publication Date Title
US9685337B2 (en) Method for fabricating semiconductor device
TWI726128B (zh) 半導體元件及其製作方法
TWI728139B (zh) 半導體元件及其製作方法
CN106803484B (zh) 半导体元件及其制作方法
TWI624863B (zh) 半導體元件及其製作方法
CN106684041B (zh) 半导体元件及其制作方法
TWI716601B (zh) 半導體元件及其製作方法
CN107808849B (zh) 半导体元件及其制作方法
CN109216191B (zh) 半导体元件及其制作方法
TWI729181B (zh) 半導體元件及其製作方法
US20170309520A1 (en) Semiconductor device and method for fabricating the same
TWI761529B (zh) 半導體元件及其製作方法
TWI728174B (zh) 半導體元件及其製作方法
CN110473784B (zh) 半导体元件及其制作方法
TWI728162B (zh) 半導體元件及其製作方法
CN112436004A (zh) 半导体元件及其制作方法
US10090398B2 (en) Manufacturing method of patterned structure of semiconductor
TWI776911B (zh) 半導體元件及其製作方法
CN112736079A (zh) 具有连接pmos区域栅极结构的接触插塞的半导体元件
US10566327B2 (en) Method for enlarging tip portion of a fin-shaped structure
TWI695420B (zh) 一種製作半導體元件的方法
CN110828377B (zh) 一种具有不对称功函数金属层的半导体元件
TW202135227A (zh) 半導體元件及其製作方法
TWI821535B (zh) 一種製作半導體元件的方法
CN109545747B (zh) 半导体元件及其制作方法