TWI716601B - 半導體元件及其製作方法 - Google Patents

半導體元件及其製作方法 Download PDF

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TWI716601B
TWI716601B TW106118681A TW106118681A TWI716601B TW I716601 B TWI716601 B TW I716601B TW 106118681 A TW106118681 A TW 106118681A TW 106118681 A TW106118681 A TW 106118681A TW I716601 B TWI716601 B TW I716601B
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metal layer
work function
dielectric layer
layer
function metal
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TW201903856A (zh
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李皞明
林勝豪
陳信宇
謝守偉
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聯華電子股份有限公司
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Priority to US15/642,324 priority patent/US10008578B1/en
Priority to US15/984,426 priority patent/US10211311B2/en
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Abstract

本發明揭露一種製作半導體元件的方法。首先形成一金屬閘極於一基底上以及一側壁子環繞金屬閘極，其中金屬閘極包含一高介電常數介電層、一功函數金屬層以及一低阻抗金屬層。然後去除部分高介電常數介電層以形成一氣孔於功函數金屬層以及側壁子之間。

Description

半導體元件及其製作方法
本發明是關於一種半導體元件，尤指一種於功函數金屬層與側壁子之間具有氣孔的半導體元件。
近年來，隨著場效電晶體(field effect transistors,FETs)元件尺寸持續地縮小，習知平面式(planar)場效電晶體元件之發展已面臨製程上之極限。為了克服製程限制，以非平面(non-planar)之場效電晶體元件，例如鰭狀場效電晶體(fin field effect transistor,Fin FET)元件來取代平面電晶體元件已成為目前之主流發展趨勢。由於鰭狀場效電晶體元件的立體結構可增加閘極與鰭狀結構的接觸面積，因此，可進一步增加閘極對於載子通道區域的控制，從而降低小尺寸元件面臨的汲極引發能帶降低(drain induced barrier lowering,DIBL)效應，並可以抑制短通道效應(short channel effect,SCE)。再者，由於鰭狀場效電晶體 元件在同樣的閘極長度下會具有更寬的通道寬度，因而可獲得加倍的汲極驅動電流。甚而，電晶體元件的臨界電壓(threshold voltage)亦可藉由調整閘極的功函數而加以調控。
一般而言，半導體製程在進入10奈米世代後金屬閘極的電阻值對整個鰭狀場效電晶體的效能扮演了一重要腳色。由於現今的金屬閘極電晶體架構對整個電阻值的表現仍不盡理想，因此如何在現今場效電晶體的架構下改良此問題即為現今一重要課題。
本發明一實施例揭露一種製作半導體元件的方法。首先形成一金屬閘極於一基底上以及一側壁子環繞金屬閘極，其中金屬閘極包含一高介電常數介電層、一功函數金屬層以及一低阻抗金屬層。然後去除部分高介電常數介電層以形成一氣孔於功函數金屬層以及側壁子之間。
本發明又一實施例揭露一種半導體元件，其主要包含一金屬閘極設於一基底上以及一側壁子環繞金屬閘極。其中金屬閘極包含：一高介電常數介電層、一功函數金屬層設於高介電常數介電層上以及一低阻抗金屬層設於功函數金屬層上。此外，半導體元件又包含一氣孔設於功函數金屬層及側壁子之間。
12:基底
14:鰭狀結構
16:閘極結構
18:閘極介電層
20:閘極材料層
22:側壁子
24:源極/汲極區域
26:偏位側壁子
28:主側壁子
30:接觸洞蝕刻停止層
32:層間介電層
34:介質層
36:高介電常數介電層
38:功函數金屬層
40:低阻抗金屬層
42:金屬閘極
44:硬遮罩
46:氣孔
第1圖至第9圖為本發明較佳實施例製作一半導體元件之方法示意圖。
請參照第1圖至第9圖，第1圖至第9圖為本發明較佳實施例製作一半導體元件之方法示意圖。如第1圖所示，首先提供一基底12，例如一矽基底或矽覆絕緣(SOI)基板，其上可定義有一電晶體區，例如一PMOS電晶體區或一NMOS電晶體區。基底12上具有至少一鰭狀結構14及一絕緣層(圖未示)，其中鰭狀結構14之底部係被絕緣層，例如氧化矽所包覆而形成淺溝隔離。需注意的是，本實施例雖以製作非平面型場效電晶體(non-planar)例如鰭狀結構場效電晶體為例，但不侷限於此，本發明又可應用至一般平面型(planar)場效電晶體，此實施例也屬本發明所涵蓋的範圍。
依據本發明一實施例，鰭狀結構14較佳透過側壁圖案轉移(sidewall image transfer,SIT)技術製得，其程序大致包括：提供一佈局圖案至電腦系統，並經過適當地運算以將相對應之圖案定義於光罩中。後續可透過光微影及蝕刻製程，以形成多個等距且等寬之圖案化犧牲層於基底上，使其個別外觀呈現條狀。之後依序施行沉積及蝕刻製程，以於圖案化犧牲層之各側壁形成側壁子。繼以去除圖案化犧牲層，並在側壁子的覆蓋下施行蝕刻製程，使得側壁子所構成之圖案被轉移至基底內，再伴隨鰭狀結構切割製程(fin cut)而獲得所需的圖案化 結構，例如條狀圖案化鰭狀結構。
除此之外，鰭狀結構14之形成方式又可包含先形成一圖案化遮罩(圖未示)於基底12上，再經過一蝕刻製程，將圖案化遮罩之圖案轉移至基底12中以形成鰭狀結構。另外，鰭狀結構之形成方式也可以先形成一圖案化硬遮罩層(圖未示)於基底12上，並利用磊晶製程於暴露出於圖案化硬遮罩層之基底12上成長出例如包含矽鍺的半導體層，而此半導體層即可作為相對應的鰭狀結構。這些形成鰭狀結構的實施例均屬本發明所涵蓋的範圍。
接著可於基底12上形成至少一閘極結構16或虛置閘極。在本實施例中，閘極結構16之製作方式可依據製程需求以先閘極(gate first)製程、後閘極(gate last)製程之先高介電常數介電層(high-k first)製程以及後閘極製程之後高介電常數介電層(high-k last)製程等方式製作完成。以本實施例之後高介電常數介電層製程為例，可先依序形成一閘極介電層或介質層、一由多晶矽所構成之閘極材料層以及一選擇性硬遮罩於基底12上，並利用一圖案化光阻(圖未示)當作遮罩進行一圖案轉移製程，以單次蝕刻或逐次蝕刻步驟，去除部分閘極材料層與部分閘極介電層，然後剝除圖案化光阻，以於基底12上形成由圖案化之閘極介電層18與圖案化之閘極材料層20所構成的閘極結構16。
然後在閘極結構16側壁形成至少一側壁子22，接著於側壁子22兩側的鰭狀結構14以及/或基底12中形成一源極/汲極區域24及/或磊晶層(圖未示)，並選擇性於源極/汲極區域24及/或磊晶層的表面形成一 金屬矽化物(圖未示)。在本實施例中，側壁子22可為單一側壁子或複合式側壁子，例如可細部包含一偏位側壁子26以及一主側壁子28。其中偏位側壁子26與主側壁子28可包含相同或不同材料，且兩者均可選自由氧化矽、氮化矽、氮氧化矽以及氮碳化矽所構成的群組。源極/汲極區域24可依據所置備電晶體的導電型式而包含不同摻質，例如可包含P型摻質或N型摻質。
接著如第2圖所示，先形成一接觸洞蝕刻停止層30於基底12表面與閘極結構16上，再形成一層間介電層32於接觸洞蝕刻停止層30上。然後進行一平坦化製程，例如利用化學機械研磨(chemical mechanical polishing,CMP)去除部分層間介電層32與部分接觸洞蝕刻停止層30並暴露出由多晶矽材料所構成的閘極材料層20，使各閘極材料層20上表面與層間介電層32上表面齊平。
如第3圖所示，隨後進行一金屬閘極置換製程將閘極結構16轉換為金屬閘極。舉例來說，可先進行一選擇性之乾蝕刻或濕蝕刻製程，例如利用氨水(ammonium hydroxide,NH4OH)或氫氧化四甲銨(Tetramethylammonium Hydroxide,TMAH)等蝕刻溶液來去除閘極結構16中的閘極材料層20甚至閘極介電層18，以於層間介電層32中形成凹槽(圖未示)。之後依序形成一介質層34或閘極介電層、一高介電常數介電層36、一功函數金屬層38以及一低阻抗金屬層40於凹槽內，然後進行一平坦化製程，例如利用CMP去除部分低阻抗金屬層40、部分功函數金屬層38與部分高介電常數介電層36以形成金屬閘極42。以本實施例利用後高介電常數介電層製程所製作的閘極結構為例，閘極結構 16較佳包含一介質層34或閘極介電層、一U型高介電常數介電層36、一U型功函數金屬層38以及一低阻抗金屬層40。
在本實施例中，高介電常數介電層36包含介電常數大於4的介電材料，例如選自氧化鉿(hafnium oxide，HfO2)、矽酸鉿氧化合物(hafnium silicon oxide,HfSiO4)、矽酸鉿氮氧化合物(hafnium silicon oxynitride,HfSiON)、氧化鋁(aluminum oxide,Al2O3)、氧化鑭(lanthanum oxide,La2O3)、氧化鉭(tantalum oxide,Ta2O5)、氧化釔(yttrium oxide,Y2O3)、氧化鋯(zirconium oxide,ZrO2)、鈦酸鍶(strontium titanate oxide,SrTiO3)、矽酸鋯氧化合物(zirconium silicon oxide,ZrSiO4)、鋯酸鉿(hafnium zirconium oxide,HfZrO4)、鍶鉍鉭氧化物(strontium bismuth tantalate,SrBi2Ta2O9,SBT)、鋯鈦酸鉛(lead zirconate titanate,PbZrxTi1-xO3,PZT)、鈦酸鋇鍶(barium strontium titanate,BaxSr1-xTiO3,BST)、或其組合所組成之群組。
功函數金屬層38較佳用以調整形成金屬閘極之功函數，使其適用於N型電晶體(NMOS)或P型電晶體(PMOS)。若電晶體為N型電晶體，功函數金屬層46可選用功函數為3.9電子伏特(eV)~4.3eV的金屬材料，如鋁化鈦(TiAl)、鋁化鋯(ZrAl)、鋁化鎢(WAl)、鋁化鉭(TaAl)、鋁化鉿(HfAl)或TiAlC(碳化鈦鋁)等，但不以此為限；若電晶體為P型電晶體，功函數金屬層46可選用功函數為4.8eV~5.2eV的金屬材料，如氮化鈦(TiN)、氮化鉭(TaN)或碳化鉭(TaC)等，但不以此為限。功函數金屬層46與低阻抗金屬層48之間可包含另一阻障層(圖未示)，其中阻障層的材料可包含鈦(Ti)、氮化鈦(TiN)、鉭(Ta)、氮化鉭(TaN)等材 料。低阻抗金屬層48則可選自銅(Cu)、鋁(Al)、鎢(W)、鈦鋁合金(TiAl)、鈷鎢磷化物(cobalt tungsten phosphide，CoWP)等低電阻材料或其組合。
隨後如第4圖所示，進行一第一蝕刻製程去除部分功函數金屬層38。更具體而言，本階段所進行的第一蝕刻製程較佳在不形成任何圖案化遮罩的情況下利用功函數金屬層38與低阻抗金屬層40之間的選擇比來去除部分功函數金屬層38但不損耗兩旁的低阻抗金屬層40與高介電常數金屬層36，使剩餘的功函數金屬層38上表面略低於低阻抗金屬層40上表面或低阻抗金屬層40上表面高於功函數金屬層38上表面。
如第5圖所示，然後進行一第二蝕刻製程去除部分低阻抗金屬層40。如同前述第一蝕刻製程，本階段所進行的第二蝕刻製程較佳在不形成任何圖案化遮罩的情況下利用功函數金屬層38與低阻抗金屬層40之間的選擇比來去除部分低阻抗金屬層40但不損耗任何功函數金屬層38與高介電常數金屬層36。換句話說，在此階段功函數金屬層38與高介電常數介電層36的上表面較佳維持與第4圖相同的高度。在進行第二蝕刻製程後，低阻抗金屬層40上表面較佳略低於功函數金屬層38或功函數金屬層38上表面高於低阻抗金屬層40上表面。
接著如第6圖所示，進行一第三蝕刻製程再次去除部分功函數金屬層38。如同前述第一蝕刻製程，本階段所進行的第三蝕刻製程較佳在不形成任何圖案化遮罩的情況下利用功函數金屬層38與低阻抗金屬層40之間的選擇比來去除部分功函數金屬層38但不損耗任何兩旁 的低阻抗金屬層40與高介電常數介電層36，使功函數金屬層38上表面再次低於低阻抗金屬層40上表面或低阻抗金屬層40上表面高於功函數金屬層38上表面。此時剩餘的功函數金屬層38與低阻抗金屬層40上表面均低於高介電常數介電層36與層間介電層32上表面。
然後如第7圖所示，進行一第四蝕刻製程去除部分高介電常數介電層36。更具體而言，本階段所進行的第四蝕刻製程較佳在不形成任何圖案化遮罩的情況下選用例如氯氣(Cl2)以及/或三氯化硼(BCl3)等蝕刻氣體在不耗損兩旁例如側壁子22、功函數金屬層38以及低阻抗金屬層40的情況下來僅去除部分高介電常數介電層36，並使剩餘的高介電常數介電層36上表面約略切齊功函數金屬層38上表面。
隨後如第8圖所示，進行一第五蝕刻製程再次去除部分該高介電常數介電層36並使高介電常數介電層36上表面低於功函數金屬層38上表面，例如停在約略功函數金屬層38一半高度的位置。在本實施例中，第五蝕刻製程所使用的氣體成分可與前述第四蝕刻製程用來去除部分高介電常數介電層36的氣體相同，但不侷限於此。
如第9圖所示，接著填入一硬遮罩44於凹槽內的功函數金屬層38與低阻抗金屬層40上，並使硬遮罩44上表面切齊層間介電層32上表面。值得注意的是，由於形成硬遮罩44之前高介電常數介電層36的高度已被特別降低至約略側壁子22高度的一半以下，因此後續填入硬遮罩44之後在硬遮罩44不填滿功函數金屬層38與側壁子22間的情況下本實施例在形成硬遮罩44的同時較佳於功函數金屬層38與側壁子22之 間形成氣孔46。換句話說，氣孔46係位於硬遮罩44與高介電常數介電層36之間，或從另一角度來看氣孔46是同時由高介電常數介電層36、側壁子22、硬遮罩44以及功函數金屬層38等四種元件同時環繞而成。在本實施例中，硬遮罩44可選自由例如氧化矽、氮化矽、氮氧化矽以及氮碳化矽所構成的群組。
之後可依據製程需求進行接觸插塞製程，例如可於層間介電層32中形成接觸插塞(圖未示)電連接側壁子22兩側的源極/汲極區域24。至此即完成本發明一實施例之半導體元件的製作。
請再參照第9圖，第9圖又揭露一本發明一實施例之半導體元件之結構示意圖。如第9圖所示，半導體元件較佳包含一金屬閘極42設於基底12上、至少一側壁子22環繞金屬閘極42、源極/汲極區域24設於側壁子22兩側的基底12或鰭狀結構14內、接觸洞蝕刻停止層30設於側壁子22上、層間介電層32環繞側壁子22與接觸洞蝕刻停止層30以及一硬遮罩44設於金屬閘極42上。
更具體而言，金屬閘極42包含一高介電常數介電層36、一功函數金屬層38設於高介電常數介電層36上以及一低阻抗金屬層40設於功函數金屬層38上，其中高介電常數介電層36與功函數金屬層38均為U型，低阻抗金屬層上40表面較佳高於功函數金屬層38上表面，且U型功函數金屬層38上表面又高於U型高介電常數介電層36上表面。
在本實施中，功函數金屬層38與兩側的側壁子22之間各包含 一氣孔46，其中各氣孔46為完全中空且氣孔46的上表面較佳切齊功函數金屬層38的上表面，氣孔46的下表面則約略切齊功函數金屬層38高度的一半。從另一角度來看，功函數金屬層38兩側的氣孔46分別由高介電常數介電層36、側壁子22、硬遮罩44以及功函數金屬層38等四種元件同時環繞而成。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
12:基底
14:鰭狀結構
22:側壁子
24:源極/汲極區域
26:偏位側壁子
28:主側壁子
30:接觸洞蝕刻停止層
32:層間介電層
34:介質層
36:高介電常數介電層
38:功函數金屬層
40:低阻抗金屬層
42:金屬閘極
44:硬遮罩
46:氣孔

Claims (18)

  1. 一種製作半導體元件的方法，包含：形成一金屬閘極於一基底上以及一側壁子環繞該金屬閘極，該金屬閘極包含一高介電常數介電層、一功函數金屬層以及一低阻抗金屬層；以及去除部分該高介電常數介電層以形成一氣孔於該功函數金屬層以及該側壁子之間。
  2. 如申請專利範圍第1項所述之方法，另包含：形成一閘極結構於該基底上；形成該側壁子環繞該閘極結構；形成一層間介電層環繞該側壁子；以及進行一金屬閘極置換製程將該閘極結構轉換為該金屬閘極。
  3. 如申請專利範圍第2項所述之方法，另包含：進行一第一蝕刻製程去除部分該功函數金屬層；進行一第二蝕刻製程去除部分該低阻抗金屬層；進行一第三蝕刻製程去除部分該功函數金屬層；以及進行一第四蝕刻製程去除部分該高介電常數介電層。
  4. 如申請專利範圍第3項所述之方法，另包含進行該第一蝕刻製程使該低阻抗金屬層上表面高於該功函數金屬層上表面。
  5. 如申請專利範圍第3項所述之方法，另包含進行該第二蝕刻製程使該功函數金屬層上表面高於該低阻抗金屬層上表面。
  6. 如申請專利範圍第3項所述之方法，另包含進行該第三蝕刻製程使該低阻抗金屬層上表面高於該功函數金屬層上表面。
  7. 如申請專利範圍第3項所述之方法，另包含進行該第四蝕刻製程使該功函數金屬層上表面切齊該高介電常數介電層上表面。
  8. 如申請專利範圍第3項所述之方法，另包含進行一第五蝕刻製程去除部分該高介電常數介電層使該功函數金屬層上表面高於該高介電常數介電層上表面。
  9. 如申請專利範圍第2項所述之方法，另包含形成一硬遮罩於該功函數金屬層及該低阻抗金屬層上。
  10. 如申請專利範圍第9項所述之方法，其中該氣孔係位於該硬遮罩及該高介電常數介電層之間。
  11. 一種半導體元件，包含：一金屬閘極設於一基底上，該金屬閘極包含：一高介電常數介電層；一功函數金屬層設於該高介電常數介電層上；以及一低阻抗金屬層設於該功函數金屬層上； 一側壁子環繞該金屬閘極；以及一氣孔設於該功函數金屬層及該側壁子之間。
  12. 如申請專利範圍第11項所述之半導體元件，其中該高介電常數介電層及該功函數金屬層係為U型。
  13. 如申請專利範圍第11項所述之半導體元件，其中該低阻抗金屬層上表面高於該功函數金屬層上表面。
  14. 如申請專利範圍第11項所述之半導體元件，其中該功函數金屬層上表面高於該高介電常數介電層上表面。
  15. 如申請專利範圍第11項所述之半導體元件，另包含一硬遮罩設於該功函數金屬層及該低阻抗金屬層上。
  16. 如申請專利範圍第15項所述之半導體元件，其中該氣孔係位於該硬遮罩及該高介電常數介電層之間。
  17. 如申請專利範圍第15項所述之半導體元件，另包含一層間介電層環繞該側壁子。
  18. 如申請專利範圍第17項所述之半導體元件，其中該硬遮罩上表面切齊該層介電層上表面。
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