TW202109625A - 一種製作半導體元件的方法 - Google Patents

一種製作半導體元件的方法 Download PDF

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TW202109625A
TW202109625A TW108129117A TW108129117A TW202109625A TW 202109625 A TW202109625 A TW 202109625A TW 108129117 A TW108129117 A TW 108129117A TW 108129117 A TW108129117 A TW 108129117A TW 202109625 A TW202109625 A TW 202109625A
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layer
forming
contact hole
barrier layer
method described
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邱勁硯
蔡緯撰
易延才
陳立涵
柯賢文
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聯華電子股份有限公司
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Abstract

本發明揭露一種製作半導體元件的方法。首先形成一閘極結構於一基底上，然後形成一源極/汲極區域於該閘極結構兩側，形成一層間介電層於該閘極結構上；形成一接觸洞於該層間介電層內並暴露出該源極/汲極區域；形成一阻障層於該接觸洞內；進行一退火製程；以及進行一電漿處理製程將氮氣植入該接觸洞內。

Description

一種製作半導體元件的方法
本發明是關於一種製作半導體元件的方法，尤指一種於閘極結構兩側形成接觸洞後進行電漿處理製程將氮氣植入接觸洞內之方法。
近年來，隨著場效電晶體(field effect transistors, FETs)元件尺寸持續地縮小，習知平面式(planar)場效電晶體元件之發展已面臨製程上之極限。為了克服製程限制，以非平面(non-planar)之場效電晶體元件，例如鰭狀場效電晶體(fin field effect transistor, Fin FET)元件來取代平面電晶體元件已成為目前之主流發展趨勢。由於鰭狀場效電晶體元件的立體結構可增加閘極與鰭狀結構的接觸面積，因此，可進一步增加閘極對於載子通道區域的控制，從而降低小尺寸元件面臨的汲極引發能帶降低(drain induced barrier lowering, DIBL)效應，並可以抑制短通道效應(short channel effect, SCE)。再者，由於鰭狀場效電晶體元件在同樣的閘極長度下會具有更寬的通道寬度，因而可獲得加倍的汲極驅動電流。甚而，電晶體元件的臨界電壓(threshold voltage)亦可藉由調整閘極的功函數而加以調控。
然而，在現行鰭狀場效電晶體元件製程中，特別是接觸插塞的製備階段時常發生阻障層與金屬層之間附著不佳的問題進而影響整個元件的運作與電性表現。因此如何改良現有鰭狀場效電晶體製程以解決此問題即為現今一重要課題。
本發明一實施例揭露一種製作半導體元件的方法。首先形成一閘極結構於一基底上，然後形成一源極/汲極區域於該閘極結構兩側，形成一層間介電層於該閘極結構上；形成一接觸洞於該層間介電層內並暴露出該源極/汲極區域；形成一阻障層於該接觸洞內；進行一退火製程；以及進行一電漿處理製程將氮氣植入該接觸洞內。
請參照第1圖至第6圖，第1圖至第6圖為本發明一實施例製作一半導體元件之方法示意圖。如第1圖所示，首先提供一基底12，然後於基底12上形成至少一閘極結構14、16。在本實施例中，形成閘極結構14、16的方式較佳依序形成一閘極介電層、一閘極材料層以及一硬遮罩於基底12上，並利用一圖案化光阻(圖未示)當作遮罩進行一圖案轉移製程，以單次蝕刻或逐次蝕刻步驟，去除部分硬遮罩、部分閘極材料層以及部分閘極介電層，然後剝除圖案化光阻，以於基底12上形成至少一由圖案化之閘極介電層18、圖案化之閘極材料層20以及圖案化之硬遮罩22所構成的閘極結構14、16。在本實施例中，閘極結構14、16的數量以兩顆為例，但不侷限於此，且為了凸顯後續於兩個閘極結構14、16之間所形成的接觸插塞，本實施例僅顯示部分閘極結構14、16，例如僅顯示閘極結構14的右半部份與閘極結構16的左半部份。
在本實施例中，基底12例如是矽基底、磊晶矽基底、碳化矽基底或矽覆絕緣(silicon-on-insulator, SOI)基底等之半導體基底，但不以此為限。閘極介電層18可包含二氧化矽(SiO2 )、氮化矽(SiN)或高介電常數(high dielectric constant, high-k)材料；閘極材料層20可包含金屬材料、多晶矽或金屬矽化物(silicide)等導電材料；硬遮罩22可選自由氧化矽、氮化矽、碳化矽(SiC)以及氮氧化矽(SiON)所構成的群組，但不侷限於此。
此外，在一實施例中，還可選擇預先在基底12中形成複數個摻雜井(未繪示)或複數個作為電性隔離之用的淺溝渠隔離(shallow trench isolation, STI)。並且，本實施例雖以平面型電晶體為例，但在其他變化實施例中，本發明之半導體製程亦可應用於非平面電晶體，例如是鰭狀電晶體(Fin-FET)，此時，第1圖所標示之基底12即相對應代表為形成於一基底12上的鰭狀結構。
然後在各閘極結構14、16側壁形成至少一側壁子24，於側壁子24兩側的基底12中形成一源極/汲極區域26及/或磊晶層28。在本實施例中，側壁子24可為單一側壁子或複合式側壁子，例如可細部包含一偏位側壁子(圖未示)以及一主側壁子(圖未示)。其中本實施例的側壁子24較佳由氮化矽所構成，但側壁子24又可選自由氧化矽、氮氧化矽以及氮碳化矽所構成的群組。源極/汲極區域26與磊晶層28可依據所置備電晶體的導電型式而包含不同摻質或不同材料。例如源極/汲極區域26可包含P型摻質或N型摻質，而磊晶層28則可包含鍺化矽、碳化矽或磷化矽。
接著如第2圖所示，可選擇性形成一由氮化矽所構成的接觸洞蝕刻停止層(contact etch stop layer, CESL)36於基底12上並覆蓋閘極結構14、16，再形成一層間介電層38於接觸洞蝕刻停止層36上。接著進行一平坦化製程，例如利用化學機械研磨(chemical mechanical polishing, CMP)去除部分層間介電層38與部分接觸洞蝕刻停止層36並使硬遮罩22上表面與層間介電層38上表面齊平。
隨後進行一金屬閘極置換製程將閘極結構14、16轉換為金屬閘極。例如可先進行一選擇性之乾蝕刻或濕蝕刻製程，例如利用氨水(ammonium hydroxide, NH4 OH)或氫氧化四甲銨(Tetramethylammonium Hydroxide, TMAH)等蝕刻溶液來去除閘極結構14、16中的硬遮罩22與閘極材料層20，以於層間介電層38中形成凹槽(圖未示)。之後依序形成一高介電常數介電層40以及至少包含功函數金屬層42與低阻抗金屬層44的導電層於凹槽內，並再搭配進行一平坦化製程使U型高介電常數介電層40、U型功函數金屬層42與低阻抗金屬層44的表面與層間介電層38表面齊平。
在本實施例中，高介電常數介電層40包含介電常數大於4的介電材料，例如選自氧化鉿(hafnium oxide, HfO2 )、矽酸鉿氧化合物(hafnium silicon oxide, HfSiO4 )、矽酸鉿氮氧化合物(hafnium silicon oxynitride, HfSiON)、氧化鋁(aluminum oxide, Al2 O3 )、氧化鑭(lanthanum oxide, La2 O3 )、氧化鉭(tantalum oxide, Ta2 O5 )、氧化釔(yttrium oxide, Y2 O3 )、氧化鋯(zirconium oxide, ZrO2 )、鈦酸鍶（strontium titanate oxide, SrTiO3 ）、矽酸鋯氧化合物(zirconium silicon oxide, ZrSiO4 )、鋯酸鉿(hafnium zirconium oxide, HfZrO4 )、鍶鉍鉭氧化物(strontium bismuth tantalate, SrBi2 Ta2 O9 , SBT)、鋯鈦酸鉛(lead zirconate titanate,  PbZrx Ti1-x O3 , PZT)、鈦酸鋇鍶(barium strontium titanate, Bax Sr1-x TiO3 , BST)、或其組合所組成之群組。
功函數金屬層42較佳用以調整形成金屬閘極之功函數，使其適用於N型電晶體(NMOS)或P型電晶體(PMOS)。若電晶體為N型電晶體，功函數金屬層42可選用功函數為3.9電子伏特(eV)～4.3 eV的金屬材料，如鋁化鈦(TiAl)、鋁化鋯(ZrAl)、鋁化鎢(WAl)、鋁化鉭(TaAl)、鋁化鉿(HfAl)或TiAlC (碳化鈦鋁)等，但不以此為限；若電晶體為P型電晶體，功函數金屬層42可選用功函數為4.8 eV～5.2 eV的金屬材料，如氮化鈦(TiN)、氮化鉭(TaN)或碳化鉭(TaC)等，但不以此為限。功函數金屬層42與低阻抗金屬層44之間可包含另一阻障層(圖未示)，其中阻障層的材料可包含鈦(Ti)、氮化鈦(TiN)、鉭(Ta)、氮化鉭(TaN)等材料。低阻抗金屬層44則可選自銅(Cu)、鋁(Al)、鎢(W)、鈦鋁合金(TiAl)、鈷鎢磷化物(cobalt tungsten phosphide，CoWP)等低電阻材料或其組合。由於依據金屬閘極置換製程將虛置閘極轉換為金屬閘極乃此領域者所熟知技藝，在此不另加贅述。接著可去除部分高介電常數介電層40、部分功函數金屬層42與部分低阻抗金屬層44形成凹槽(圖未示)，然後再填入一硬遮罩46於凹槽內並使硬遮罩46與層間介電層38表面齊平，其中硬遮罩46可選自由氧化矽、氮化矽、氮氧化矽以及氮碳化矽所構成的群組。
如第3圖所示，接著可利用圖案化遮罩進行一蝕刻製程，去除閘極結構14、16旁的部分層間介電層38及部分接觸洞蝕刻停止層36以形成接觸洞48暴露磊晶層28表面。然後依序形成一金屬層50以及一阻障層52於接觸洞48內但不填滿接觸洞48。在本實施例中，金屬層50可選自由鈦、鈷、鎳及鉑等所構成的群組且最佳包含鈦，阻障層52可包含氮化鈦、氮化鉭等金屬化合物且最佳包含氮化鈦。需注意的是，本階段所形成的阻障層52較佳為一具有低氮比例之氮化鈦層，其中所謂低氮比例係指氮化鈦層中氮原子相對於鈦原子之比例較佳約1.08。
如第4圖所示，然後進行一退火製程54以形成一金屬矽化物56。更具體而言，在連續沉積金屬層50與阻障層52之後本階段所進行的退火製程54可包含依序進行一第一熱處理製程與一第二熱處理製程以形成一金屬矽化物56於磊晶層28上。在本實施例中，第一熱處理製程包含一常溫退火(soak anneal)製程，其溫度較佳介於500℃至600℃，且最佳為550℃，而其處理時間則較佳介於10秒至60秒，且最佳為30秒。第二熱處理製程包含一峰值退火(spike anneal)製程，其溫度較佳介於600℃至950℃，且最佳為600℃，而其處理較佳時間則較佳介於100毫秒至5秒，且最佳為5秒。
隨後如第5圖所示，進行一電漿處理製程58將氮原子通入接觸洞48內。從細部來看，本階段所進行的電漿處理製程58較佳由氨氣(NH3 )或任何含可釋放出氮原子的氣體或媒介將氮原子注入阻障層52內，使原本具有低氮比例的阻障層52經由電漿處理製程58提升氮原子比例後改變為一具有高氮比例的氮化鈦層。相較於前述在進行電漿處理製程58前阻障層52中的氮原子相對於鈦原子之比例約1.08，本階段經電漿處理製程58將氮原子植入阻障層52後阻障層52中氮原子相對於鈦原子的比例較佳提升為約1.2。
如第6圖所示，之後形成一導電層60於接觸洞48內並填滿接觸洞48。在本實施例中，導電層60較佳包含鎢，但不侷限於此。最後進行一平坦化製程，例如以CMP製程去除部分導電層60、部分阻障層52及部分金屬層50，甚至可視製程需求接著去除部分層間介電層38，以形成接觸插塞62電連接磊晶層28。至此即完成本發明較佳實施例一半導體元件的製作。
一般而言，現行於接觸插塞階段所進行的矽化金屬製程需先依序沉積一由例如鈦所構成的金屬層以及氮化鈦所構成的阻障層於接觸洞內。然而阻障層中的氮原子含量於沉積後通常會急速衰退，使阻障層與後續沉積的鎢導電層之間產生附著不佳(poor adhesion)現象並造成缺陷。為了改善此問題，本發明主要利用退火製程將金屬層與部分磊晶層反應形成金屬矽化物之後額外進行一電漿處理製程，將氮原子注入阻障層內來提升阻障層中已衰退的氮原子含量，藉此改善阻障層與後續鎢金屬層之間的附著能力。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
12:基底 14:閘極結構 16:閘極結構 18:閘極介電層 20:閘極材料層 22:硬遮罩 24:側壁子 26:源極/汲極區域 28:磊晶層 36:接觸洞蝕刻停止層 38:層間介電層 40:高介電常數介電層 42:功函數金屬層 44:低阻抗金屬層 46:硬遮罩 48:接觸洞 50:金屬層 52:阻障層 54:退火製程 56:金屬矽化物 58:電漿處理製程 60:導電層 62:接觸插塞
第1圖至第6圖為本發明一實施例製作一半導體元件之方法示意圖。
12:基底
14:閘極結構
16:閘極結構
18:閘極介電層
24:側壁子
26:源極/汲極區域
28:磊晶層
36:接觸洞蝕刻停止層
38:層間介電層
40:高介電常數介電層
42:功函數金屬層
44:低阻抗金屬層
46:硬遮罩
50:金屬層
52:阻障層
56:金屬矽化物
60:導電層
62:接觸插塞

Claims (9)

  1. 一種製作半導體元件的方法，其特徵在於，包含： 形成一閘極結構於一基底上； 形成一源極/汲極區域於該閘極結構兩側； 形成一層間介電層於該閘極結構上； 形成一接觸洞於該層間介電層內並暴露出該源極/汲極區域； 形成一阻障層於該接觸洞內； 進行一退火製程；以及 進行一電漿處理製程將氮氣植入該接觸洞內。
  2. 如申請專利範圍第1項所述之方法，另包含於形成該阻障層前形成一金屬層於該接觸洞內。
  3. 如申請專利範圍第2項所述之方法，其中該金屬層包含鈦。
  4. 如申請專利範圍第2項所述之方法，另包含： 於進行該電漿處理製程後形成一導電層於該接觸洞內；以及 平坦化該導電層、該阻障層以及該金屬層以形成一接觸插塞。
  5. 如申請專利範圍第4項所述之方法，其中該導電層包含鎢。
  6. 如申請專利範圍第1項所述之方法，另包含進行該退火製程以形成金屬矽化物於該源極/汲極區域上。
  7. 如申請專利範圍第6項所述之方法，其中該金屬矽化物包含矽化鈦(titanium silicide)。
  8. 如申請專利範圍第1項所述之方法，其中該阻障層包含氮化鈦。
  9. 如申請專利範圍第8項所述之方法，另包含進行該電漿處理製程將氮氣植入該阻障層內。
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