TW201905974A - 半導體元件及其製作方法 - Google Patents

半導體元件及其製作方法

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Publication number
TW201905974A
TW201905974A TW106121517A TW106121517A TW201905974A TW 201905974 A TW201905974 A TW 201905974A TW 106121517 A TW106121517 A TW 106121517A TW 106121517 A TW106121517 A TW 106121517A TW 201905974 A TW201905974 A TW 201905974A
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TW
Taiwan
Prior art keywords
gate
fin
single diffusion
gate structure
diffusion isolation
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Application number
TW106121517A
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English (en)
Other versions
TWI728139B (zh
Inventor
董彥緯
王荏滺
黃正同
陳彥州
Original Assignee
聯華電子股份有限公司
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Application filed by 聯華電子股份有限公司 filed Critical 聯華電子股份有限公司
Priority to TW106121517A priority Critical patent/TWI728139B/zh
Priority to US15/660,970 priority patent/US10483264B2/en
Publication of TW201905974A publication Critical patent/TW201905974A/zh
Priority to US16/594,054 priority patent/US11171137B2/en
Application granted granted Critical
Publication of TWI728139B publication Critical patent/TWI728139B/zh
Priority to US17/492,687 priority patent/US11637103B2/en
Priority to US17/677,983 priority patent/US11699705B2/en

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Engineering & Computer Science (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

本發明揭露一種製作半導體元件的方法。首先形成一第一鰭狀結構於一基底上，然後形成一第一單擴散隔離結構於第一鰭狀結構內，形成一第一閘極結構於第一單擴散隔離結構上以及一第二閘極結構於第一鰭狀結構上，形成一層間介電層於第一閘極結構及第二閘極結構周圍，形成一圖案化遮罩於第一閘極結構上以及進行一金屬閘極置換製程將該第二閘極結構轉換為一金屬閘極。

Description

半導體元件及其製作方法
本發明是關於一種製作半導體元件的方法，尤指一種結合單擴散隔離結構(single diffusion break, SDB)製程與金屬閘極製程的方法。
近年來，隨著場效電晶體(field effect transistors, FETs)元件尺寸持續地縮小，習知平面式(planar)場效電晶體元件之發展已面臨製程上之極限。為了克服製程限制，以非平面(non-planar)之場效電晶體元件，例如鰭狀場效電晶體(fin field effect transistor, Fin FET)元件來取代平面電晶體元件已成為目前之主流發展趨勢。由於鰭狀場效電晶體元件的立體結構可增加閘極與鰭狀結構的接觸面積，因此，可進一步增加閘極對於載子通道區域的控制，從而降低小尺寸元件面臨的汲極引發能帶降低(drain induced barrier lowering, DIBL)效應，並可以抑制短通道效應(short channel effect, SCE)。再者，由於鰭狀場效電晶體元件在同樣的閘極長度下會具有更寬的通道寬度，因而可獲得加倍的汲極驅動電流。甚而，電晶體元件的臨界電壓(threshold voltage)亦可藉由調整閘極的功函數而加以調控。
在現行的鰭狀場效電晶體元件製程中，鰭狀結構周圍形成淺溝隔離後通常會以蝕刻方式去除部分鰭狀結構與淺溝隔離形成凹槽，然後填入絕緣物以形成單擴散隔離結構並將鰭狀結構分隔為兩部分。然而現今單擴散隔離結構與金屬閘極的製程在搭配上仍存在許多問題，因此如何改良現有鰭狀場效電晶體製程與架構即為現今一重要課題。
本發明一實施例揭露一種製作半導體元件的方法。首先形成一第一鰭狀結構於一基底上，然後形成一第一單擴散隔離結構於第一鰭狀結構內，形成一第一閘極結構於第一單擴散隔離結構上以及一第二閘極結構於第一鰭狀結構上，形成一層間介電層於第一閘極結構及第二閘極結構周圍，形成一圖案化遮罩於第一閘極結構上以及進行一金屬閘極置換製程將該第二閘極結構轉換為一金屬閘極。
本發明另一實施例揭露一種半導體元件，其主要包含：一第一鰭狀結構設於一基底上、一第一單擴散隔離結構設於第一鰭狀結構內、一第一閘極結構設於第一單擴散隔離結構上以及一第二閘極結構設於第一鰭狀結構上，其中第一閘極結構及第二閘極結構包含不同材料。
請參照第1圖至第2圖，其中第1圖為本發明較佳實施例之一半導體元件之上視圖，第2圖之左半部為第1圖中沿著切線AA’方向製作半導體元件之剖面示意圖，第2圖之右半部為第1圖中沿著切線BB’方向製作半導體元件之剖面示意圖。如第1圖至第2圖所示，首先提供一基底12，例如一矽基底或矽覆絕緣(SOI)基板，其上可定義有至少一電晶體區，例如一NMOS區域14與一PMOS區域16。然後於基底12上的NMOS區域14形成至少一鰭狀結構18以及於PMOS區域16形成至少一鰭狀結構20，其中鰭狀結構18、20底部係被一絕緣層，例如氧化矽所包覆而形成淺溝隔離22。需注意的是，本實施例雖以製作非平面型場效電晶體(non-planar)例如鰭狀結構場效電晶體為例，但不侷限於此，本發明又可應用至一般平面型(planar)場效電晶體，此實施例也屬本發明所涵蓋的範圍。
依據本發明一實施例，鰭狀結構18、20較佳透過側壁圖案轉移(sidewall image transfer, SIT)技術製得，其程序大致包括：提供一佈局圖案至電腦系統，並經過適當地運算以將相對應之圖案定義於光罩中。後續可透過光微影及蝕刻製程，以形成多個等距且等寬之圖案化犧牲層於基底上，使其個別外觀呈現條狀。之後依序施行沉積及蝕刻製程，以於圖案化犧牲層之各側壁形成側壁子。繼以去除圖案化犧牲層，並在側壁子的覆蓋下施行蝕刻製程，使得側壁子所構成之圖案被轉移至基底內，再伴隨鰭狀結構切割製程(fin cut)而獲得所需的圖案化結構，例如條狀圖案化鰭狀結構。
除此之外，鰭狀結構18、20之形成方式又可包含先形成一圖案化遮罩(圖未示)於基底12上，再經過一蝕刻製程，將圖案化遮罩之圖案轉移至基底12中以形成鰭狀結構。另外，鰭狀結構之形成方式也可以先形成一圖案化硬遮罩層(圖未示)於基底12上，並利用磊晶製程於暴露出於圖案化硬遮罩層之基底12上成長出例如包含矽鍺的半導體層，而此半導體層即可作為相對應的鰭狀結構。這些形成鰭狀結構的實施例均屬本發明所涵蓋的範圍。
接著分別於NMOS區域14與PMOS區域16各形成至少一單擴散隔離結構(single diffusion break, SDB)24、26橫跨鰭狀結構18、20。在本實施例中，形成單擴散隔離結構24、26的步驟可先形成一圖案化遮罩(圖未示)於基底12上，然後利用圖案化遮罩(圖未示)進行一蝕刻製程，沿著與鰭狀結構18、20垂直的方向分別去除NMOS區域14與PMOS區域16中部分鰭狀結構18、20與淺溝隔離22以形成凹槽28並同時將各電晶體區的各鰭狀結構18、20分隔為兩部分。以第1圖中NMOS區域14所形成的凹槽28為例，凹槽28較佳將各鰭狀結構18分隔為位於單擴散隔離結構24左側的第一部分30與位於右側的第二部分32，其中所形成的凹槽28即用來定義出後續單擴散隔離結構所形成的位置。
隨後形成一介電層34於NMOS區域14與PMOS區域的凹槽28內並填滿各凹槽28，再利用一平坦化製程，例如以回蝕刻或化學機械研磨製程去除部分介電層34，使剩餘的介電層34約略切齊各鰭狀結構18、20的頂面以形成單擴散隔離結構24、26。在本實施例中，NMOS區域14與PMOS區域16的鰭狀結構18、20較佳沿著一第一方向(例如X方向)延伸而於各電晶體區所形成的單擴散隔離結構24、26則沿著一與第一方向垂直的第二方向(例如Y方向)延伸。
然後分別於NMOS區域14與PMOS區域16的鰭狀結構18、20與單擴散隔離結構24、26上形成閘極結構36、38、40、42、44、46，其中位於NMOS區域14與PMOS區域16上的閘極結構36、38、40、44較佳為虛置閘極且會於後續製程中轉換為金屬閘極。在本實施例中，閘極結構36、38、40、42、44、46之製作方式可依據製程需求以先閘極(gate first)製程、後閘極(gate last)製程之先高介電常數介電層(high-k first)製程以及後閘極製程之後高介電常數介電層(high-k last)製程等方式製作完成。以本實施例之後高介電常數介電層製程為例，可先依序形成一閘極介電層或介質層、一由多晶矽所構成之閘極材料層以及一選擇性硬遮罩於基底12上，並利用一圖案化光阻(圖未示)當作遮罩進行一圖案轉移製程，以單次蝕刻或逐次蝕刻步驟，去除部分閘極材料層與部分閘極介電層，然後剝除圖案化光阻，以於基底12上形成由圖案化之閘極介電層48與圖案化之閘極材料層50所構成的閘極結構36、38、40、42、44、46。
然後在各閘極結構36、38、40、42、44、46側壁形成至少一側壁子52，接著於側壁子52兩側的鰭狀結構18、20以及/或基底12中形成一源極/汲極區域54及/或磊晶層(圖未示)，並選擇性於源極/汲極區域54及/或磊晶層的表面形成一金屬矽化物(圖未示)。在本實施例中，各側壁子52可為單一側壁子或複合式側壁子，例如可細部包含一偏位側壁子以及一主側壁子。其中偏位側壁子與主側壁子可包含相同或不同材料，且兩者均可選自由氧化矽、氮化矽、氮氧化矽以及氮碳化矽所構成的群組。源極/汲極區域54可依據所置備電晶體的導電型式而包含不同摻質與磊晶材料，例如NMOS區域14的源極/汲極區域54可包含碳化矽(SiC)或磷化矽(SiP)而PMOS區域16的源極/汲極區域54可包含鍺化矽(SiGe)，但均不限於此。
接著如第3圖所示，可先選擇性形成一接觸洞蝕刻停止層(圖未示)於基底12表面與閘極結構36、38、40、42、44、46上，再形成一層間介電層56於接觸洞蝕刻停止層上並覆蓋閘極結構36、38、40、42、44、46。然後進行一平坦化製程，例如利用化學機械研磨(chemical mechanical polishing, CMP)去除部分層間介電層56與部分接觸洞蝕刻停止層並暴露出由多晶矽材料所構成的閘極材料層50，使各閘極材料層50上表面與層間介電層56上表面齊平。
隨後形成一圖案化遮罩58於PMOS區域16的閘極結構42、46上，其中圖案化遮罩58較佳覆蓋PMOS區域16中設於單擴散隔離結構26正上方的閘極結構42、46與部分層間介電層56上但同時暴露出設於鰭狀結構20上方的閘極結構44上表面。值得注意的是，本實施例所形成的圖案化遮罩58較佳僅設置於PMOS區域16且不覆蓋任何NMOS區域14，亦即在PMOS區域16形成圖案化遮罩58的時候NMOS區域14的層間介電層56與所有閘極結構36、38、40，包括單擴散隔離結構24正上方與單擴散隔離結構24旁的閘極結構36、38、40上表面均無任何遮罩覆蓋且呈現裸露的狀態。在本實施例中，圖案化遮罩58較佳由氮化矽所構成，但又可依據製程需求選用任何與閘極材料層及層間介電層56之間具有蝕刻選擇比的材料，例如氮氧化矽或氮碳化矽等介電材料。
如第4圖所示，隨後進行一金屬閘極置換製程將NMOS區域14的閘極結構36、38、40與PMOS區域16的閘極結構44轉換為金屬閘極。舉例來說，可先利用圖案化遮罩為遮罩進行一乾蝕刻或濕蝕刻製程，例如利用氨水(ammonium hydroxide, NH4 OH)或氫氧化四甲銨(Tetramethylammonium Hydroxide, TMAH)等蝕刻溶液來去除NMOS區域14閘極結構36、38、40與PMOS區域16閘極結構44中的閘極材料層50甚至閘極介電層48，以於NMOS區域14與PMOS區域16的層間介電層56中形成複數個凹槽(圖未示)。之後依序形成另一選擇性介質層60或閘極介電層、一高介電常數介電層62、一選擇性阻障層(圖未示)以及一功函數金屬層64於NMOS區域14與PMOS區域16的凹槽內，形成另一圖案化遮罩(圖未示)例如圖案化光阻覆蓋NMOS區域14，利用蝕刻去除PMOS區域16的功函數金屬層64，去除圖案化遮罩後再形成另一功函數金屬層66於NMOS區域14與PMOS區域16。然後再依序形成另一阻障層68例如上阻障層以及一低阻抗金屬層70於凹槽內並填滿凹槽。
在本實施例中，高介電常數介電層62包含介電常數大於4的介電材料，例如選自氧化鉿(hafnium oxide，HfO2 )、矽酸鉿氧化合物(hafnium silicon oxide, HfSiO4 )、矽酸鉿氮氧化合物(hafnium silicon oxynitride, HfSiON)、氧化鋁(aluminum oxide, Al2 O3 )、氧化鑭(lanthanum oxide, La2 O3 )、氧化鉭(tantalum oxide, Ta2 O5 )、氧化釔(yttrium oxide, Y2 O3 )、氧化鋯(zirconium oxide, ZrO2 )、鈦酸鍶（strontium titanate oxide, SrTiO3 ）、矽酸鋯氧化合物(zirconium silicon oxide, ZrSiO4 )、鋯酸鉿(hafnium zirconium oxide, HfZrO4 )、鍶鉍鉭氧化物(strontium bismuth tantalate, SrBi2 Ta2 O9 , SBT)、鋯鈦酸鉛(lead zirconate titanate, PbZrx Ti1-x O3 , PZT)、鈦酸鋇鍶(barium strontium titanate, Bax Sr1-x TiO3 , BST)、或其組合所組成之群組。
功函數金屬層64較佳用以調整形成金屬閘極之功函數，使其適用於N型電晶體(NMOS)或P型電晶體(PMOS)。在本實施例中，功函數金屬層64較佳為N型功函數金屬層，其可選用功函數為3.9電子伏特(eV)～4.3 eV的金屬材料，如鋁化鈦(TiAl)、鋁化鋯(ZrAl)、鋁化鎢(WAl)、鋁化鉭(TaAl)、鋁化鉿(HfAl)或TiAlC (碳化鈦鋁)等，但不以此為限。功函數金屬層66則較佳為P型功函數金屬層，其可選用功函數為4.8 eV～5.2 eV的金屬材料，如氮化鈦(TiN)、氮化鉭(TaN)或碳化鉭(TaC)等，但不以此為限。另外設於高介電常數介電層62與功函數金屬層64之間的阻障層以及設於功函數金屬層66與低阻抗金屬層70之間的阻障層68可包含鈦(Ti)、氮化鈦(TiN)、鉭(Ta)、氮化鉭(TaN)等材料。低阻抗金屬層70則可選自銅(Cu)、鋁(Al)、鎢(W)、鈦鋁合金(TiAl)、鈷鎢磷化物(cobalt tungsten phosphide，CoWP)等低電阻材料或其組合。
請接著參照第5圖至第6圖，其中第5圖為接續第4圖製作半導體元件之上視圖，第6圖左半部為第5圖中沿著切線CC’方向製作半導體元件之剖面示意圖，第6圖右半部則為第5圖中沿著切線DD’方向製作半導體元件之剖面示意圖。如第5圖至第6圖所示，接著進行一平坦化製程，例如利用CMP去除NMOS區域14與PMOS區域16的部分低阻抗金屬層70、部分阻障層68、部分功函數金屬層66、部分功函數金屬層64、部分高介電常數介電層62以及設於PMOS區域16的圖案化遮罩58，以於NMOS區域14的單擴散隔離結構24正上方與旁邊的鰭狀結構18上方形成由金屬閘極所構成的閘極結構72、74、76並同時於PMOS區域16單擴散隔離結構26之間的鰭狀結構20上形成由金屬閘極所構成的閘極結構78。需注意的是，由於圖案化遮罩58的遮蔽，設於PMOS區域16單擴散隔離結構26正上方的閘極結構42、46並不會在金屬閘極置換製程時被轉換為金屬閘極，而是維持多晶矽閘極的態樣。相對地，由於沒有圖案化遮罩58的遮蔽，設於NMOS區域14單擴散隔離結構24正上方的所有閘極結構36、38、40，包括單擴散隔離結構24正上方與單擴散隔離結構24旁的閘極結構36、38、40，則會在此金屬閘極置換製程時全部被轉換為金屬閘極。
之後可去除部分由金屬閘極與多晶矽閘極所構成的閘極結構42、46、72、74、76、78，再進行一沉積製程以及一平坦化製程，以於各閘極結構42、46、72、74、76、78上形成由例如氮化矽所構成的硬遮罩80。然後可依據製程需求進行後續接觸插塞製程與金屬內連線製程，例如可於NMOS區域14與PMOS區域16的層間介電層56內形成接觸插塞電連接源極/汲極區域，並於層間介電層56上形成金屬內連線電連接接觸插塞。至此即完成本發明之半導體元件的製作。
請繼續參照第6圖，第6圖另揭露本發明一實施例之半導體元件之結構示意圖。如第6圖所示，半導體元件主要包含一基底12具有NMOS區域14與PMOS區域16，鰭狀結構18、20分別設於NMOS區域14與PMOS區域16的基底12上、至少一單擴散隔離結構24設於NMOS區域14的鰭狀結構18內、至少一單擴散隔離結構26設於PMOS區域16的鰭狀結構20內以及複數個閘極結構42、46、72、74、76、78設於NMOS區域14與PMOS區域16的單擴散隔離結構24、26與鰭狀結構18、20上。
其中設於NMOS區域14的所有閘極結構，包括設於單擴散隔離結構24正上方的閘極結構72、76與鰭狀結構18上方的閘極結構74均為金屬閘極。相較於NMOS區域14，PMOS區域16中設於單擴散隔離結構26正上方的閘極結構42、46與鰭狀結構20上方的閘極結構78較佳為不同態樣的閘極，例如在本實施例中設於單擴散隔離結構26正上方的閘極結構42、46為多晶矽閘極，而設於鰭狀結構20上方的閘極結構78則為金屬閘極。
以本實施例利用後高介電常數介電層製程所製作的閘極結構為例，NMOS區域14中由金屬閘極所構成的閘極結構72、74、76較佳包含一介質層60或閘極介電層、一U型高介電常數介電層62、一U型功函數金屬層64、一U型功函數金屬層66、一阻障層68以及一低阻抗金屬層70。PMOS區域16由金屬閘極所構成的閘極結構78則較佳包含一介質層60或閘極介電層、一U型高介電常數介電層62、一U型功函數金屬層66、一阻障層68以及一低阻抗金屬層70。
綜上所述，本發明主要在進行金屬閘極置換(RMG)製程時保留PMOS區域內設於單擴散隔離結構正上方的多晶矽閘極而僅將位於單擴散隔離結構旁之鰭狀結構上的多晶矽閘極甚至NMOS區域內的所有多晶矽閘極均轉換為金屬閘極。一般而言，在進行例如上述第4圖金屬閘極置換製程中掏空由多晶矽所構成的虛置閘極或閘極材料層的步驟通常會使設於基底或鰭狀結構內的磊晶層應力被釋放出去，而此情形可發生在掏空設於任何位置的閘極結構，其中在掏空位於單擴散隔離結構正上方的閘極結構時應力的釋放更為顯著且會同時影響並進而降低施加於旁邊通道區的應力。
為了避免PMOS區域通道區因周邊應力的釋放而無法得到足夠的應力，本發明主要如上述在金屬閘極置換製程時藉由圖案化遮罩的覆蓋不將單擴散隔離結構正上方的多晶矽閘極轉換為金屬閘極而僅將旁邊鰭狀結構上的多晶矽閘極轉換金屬閘極，如此即可確保PMOS區域的通道區在RMG製程後仍獲得足夠的應力進而維持電晶體的效能。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
12‧‧‧基底
14‧‧‧NMOS區域
16‧‧‧PMOS區域
18‧‧‧鰭狀結構
20‧‧‧鰭狀結構
22‧‧‧淺溝隔離
24‧‧‧單擴散隔離結構
26‧‧‧單擴散隔離結構
28‧‧‧凹槽
30‧‧‧第一部分
32‧‧‧第二部分
34‧‧‧介電層
36‧‧‧閘極結構
38‧‧‧閘極結構
40‧‧‧閘極結構
42‧‧‧閘極結構
44‧‧‧閘極結構
46‧‧‧閘極結構
48‧‧‧閘極介電層
50‧‧‧閘極材料層
52‧‧‧側壁子
54‧‧‧源極/汲極區域
56‧‧‧層間介電層
58‧‧‧圖案化遮罩
60‧‧‧介質層
62‧‧‧高介電常數介電層
64‧‧‧功函數金屬層
66‧‧‧功函數金屬層
68‧‧‧阻障層
70‧‧‧低阻抗金屬層
72‧‧‧閘極結構
74‧‧‧閘極結構
76‧‧‧閘極結構
78‧‧‧閘極結構
80‧‧‧硬遮罩
第1圖至第6圖為本發明一實施例製作一半導體元件之方法示意圖。

Claims (20)

  1. 一種製作半導體元件的方法，包含： 形成一第一鰭狀結構於一基底上； 形成一第一單擴散隔離結構(single diffusion break, SDB)於該第一鰭狀結構內； 形成一第一閘極結構於該第一單擴散隔離結構上以及一第二閘極結構於該第一鰭狀結構上； 形成一層間介電層於該第一閘極結構及該第二閘極結構周圍； 形成一圖案化遮罩於該第一閘極結構上；以及 進行一金屬閘極置換製程將該第二閘極結構轉換為一金屬閘極。
  2. 如申請專利範圍第1項所述之方法，其中形成該第一單擴散隔離結構之步驟包含： 去除部分該第一鰭狀結構以形成一凹槽並將該第一鰭狀結構分隔為第一部分與一第二部分；以及 形成一介電層於該凹槽內以形成該第一單擴散隔離結構。
  3. 如申請專利範圍第2項所述之方法，其中該介電層包含氮化矽。
  4. 如申請專利範圍第1項所述之方法，其中該第一鰭狀結構係沿著一第一方向延伸且該第一單擴散隔離結構係沿著一第二方向延伸。
  5. 如申請專利範圍第4項所述之方法，其中該第一方向垂直該第二方向。
  6. 如申請專利範圍第1項所述之方法，其中該基底包含一第一電晶體區以及一第二電晶體區，該第一單擴散隔離結構及該第一閘極結構係設於該第一電晶體區，該方法另包含： 形成一第二鰭狀結構於該第二電晶體區； 形成一第二單擴散隔離結構於該第二鰭狀結構內； 形成一第三閘極結構於該第二單擴散隔離結構上以及一第四閘極結構於該第二鰭狀結構上； 形成該層間介電層於該第三閘極結構及該第四閘極結構周圍； 利用該圖案化遮罩進行該金屬閘極置換製程將該第二閘極結構、該第三閘極結構以及該第四閘極結構轉換為金屬閘極。
  7. 如申請專利範圍第6項所述之方法，其中該第一電晶體區包含一PMOS區域且該第二電晶體區包含一NMOS區域。
  8. 如申請專利範圍第6項所述之方法，其中形成該第二單擴散隔離結構之步驟包含： 去除部分該第二鰭狀結構以形成一凹槽並將該第二鰭狀結構分隔為一第一部分與一第二部分；以及 形成一介電層於該凹槽內以形成該第二單擴散隔離結構。
  9. 如申請專利範圍第8項所述之方法，其中該介電層包含氮化矽。
  10. 如申請專利範圍第6項所述之方法，其中該第二鰭狀結構係沿著一第一方向延伸且該第二單擴散隔離結構係沿著一第二方向延伸。
  11. 如申請專利範圍第10項所述之方法，其中該第一方向垂直該第二方向。
  12. 一種半導體元件，包含： 一第一鰭狀結構設於一基底上； 一第一單擴散隔離結構設於該第一鰭狀結構內； 一第一閘極結構設於該第一單擴散隔離結構上；以及 一第二閘極結構設於該第一鰭狀結構上，其中該第一閘極結構及該第二閘極結構包含不同材料。
  13. 如申請專利範圍第12項所述之半導體元件，其中該第一閘極結構包含一多晶矽閘極且該第二閘極結構包含一金屬閘極。
  14. 如申請專利範圍第12項所述之半導體元件，其中該第一單擴散隔離結構包含氮化矽。
  15. 如申請專利範圍第12項所述之半導體元件，其中該第一鰭狀結構係沿著一第一方向延伸且該第一單擴散隔離結構係沿著一第二方向延伸。
  16. 如申請專利範圍第15項所述之半導體元件，其中該第一方向垂直該第二方向。
  17. 如申請專利範圍第12項所述之半導體元件，其中該基底包含一第一電晶體區以及一第二電晶體區，該第一單擴散隔離結構及該第一閘極結構係設於該第一電晶體區，該半導體元件另包含： 一第二鰭狀結構設於該第二電晶體區； 一第二單擴散隔離結構設於該第二鰭狀結構內；以及 一第三閘極結構設於該第二單擴散隔離結構上以及一第四閘極結構設於該第二鰭狀結構上。
  18. 如申請專利範圍第17項所述之半導體元件，其中該第三閘極結構及該第四閘極結構包含金屬閘極。
  19. 如申請專利範圍第17項所述之半導體元件，其中該第二鰭狀結構係沿著一第一方向延伸且該第二單擴散隔離結構係沿著一第二方向延伸。
  20. 如申請專利範圍第19項所述之半導體元件，其中該第一方向垂直該第二方向。
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US11637103B2 (en) 2023-04-25
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