TW202339000A - 半導體元件及其製作方法 - Google Patents

半導體元件及其製作方法 Download PDF

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TW202339000A
TW202339000A TW111130244A TW111130244A TW202339000A TW 202339000 A TW202339000 A TW 202339000A TW 111130244 A TW111130244 A TW 111130244A TW 111130244 A TW111130244 A TW 111130244A TW 202339000 A TW202339000 A TW 202339000A
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top surface
dielectric layer
base
voltage
gate dielectric
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TW111130244A
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許智凱
傅思逸
林毓翔
林建廷
許嘉榕
邱淳雅
陳金宏
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聯華電子股份有限公司
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Publication of TW202339000A publication Critical patent/TW202339000A/zh

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    • H01L21/823456—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions

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Abstract

本發明揭露一種製作半導體元件的方法，其主要先提供具有高壓區、中壓區以及低壓區的基底，然後形成第一電晶體於高壓區以及第二電晶體於低壓區。其中第一電晶體包含第一基座設於基底上、第一閘極介電層設於第一基座上以及第一閘極電極設於第一閘極介電層上。第二電晶體則包含一鰭狀結構設於基底上以及第二閘極電極設於鰭狀結構上，其中第一閘極介電層頂表面低於鰭狀結構頂表面。

Description

半導體元件及其製作方法
本發明是關於一種製作半導體元件的方法，尤指一種整合高壓元件、中壓元件以及低壓元件的方法。
以目前的半導體技術水準，業界已能將控制電路、記憶體、低壓操作電路以及高壓操作電路及元件同時整合製作在單一晶片上，藉此降低成本，同時提高操作效能，其中如垂直擴散金氧半導體(vertical double-diffusion metal-oxide-semiconductor, VDMOS)、絕緣閘極雙載子電晶體(insulated gate bipolar transistor, IGBT)以及橫向擴散金氧半導體(lateral-diffusion metal-oxide-semiconductor, LDMOS)等製作在晶片內的高壓元件，由於具有較佳的切換效率(power switching efficiency)，因此又較常被應用。如熟習該項技藝者所知，前述的高壓元件往往被要求能夠承受較高的崩潰電壓，並且能在較低的阻值下操作。
另外隨著元件尺寸持續地縮小，習知平面式(planar)場效電晶體元件之發展已面臨製程上之極限。為了克服製程限制，以非平面(non-planar)之場效電晶體元件，例如鰭狀場效電晶體(fin field effect transistor, Fin FET)元件來取代平面電晶體元件已成為目前之主流發展趨勢。由於鰭狀場效電晶體元件的立體結構可增加閘極與鰭狀結構的接觸面積，因此，可進一步增加閘極對於載子通道區域的控制，從而降低小尺寸元件面臨的汲極引發能帶降低(drain induced barrier lowering, DIBL)效應，並可以抑制短通道效應(short channel effect, SCE)。再者，由於鰭狀場效電晶體元件在同樣的閘極長度下會具有更寬的通道寬度，因而可獲得加倍的汲極驅動電流。甚而，電晶體元件的臨界電壓(threshold voltage)亦可藉由調整閘極的功函數而加以調控。
然而隨著元件尺寸持續縮小下現行高壓元件與鰭狀結構的整合上仍存在許多挑戰，例如漏電流以及崩潰電壓的控制等等。因此，如何改良現有高壓元件架構即為現今一重要課題。
本發明一實施例揭露一種製作半導體元件的方法，其主要先提供具有高壓區、中壓區以及低壓區的基底，然後形成第一電晶體於高壓區以及第二電晶體於低壓區。其中第一電晶體包含第一基座設於基底上、第一閘極介電層設於第一基座上以及第一閘極電極設於第一閘極介電層上。第二電晶體則包含一鰭狀結構設於基底上以及第二閘極電極設於鰭狀結構上，其中第一閘極介電層頂表面低於鰭狀結構頂表面。
本發明另一實施例揭露一種半導體元件，其主要包含一基底具有高壓區、中壓區以及低壓區，第一電晶體設於高壓區以及第二電晶體設於低壓區。其中第一電晶體包含第一基座設於基底上、第一閘極介電層設於第一基座上以及第一閘極電極設於第一閘極介電層上。第二電晶體則包含一鰭狀結構設於基底上以及第二閘極電極設於鰭狀結構上，其中第一閘極介電層頂表面低於鰭狀結構頂表面。
請參照第1圖至第11圖，第1圖至第11圖為本發明一實施例製作半導體元件之方法示意圖，其中第1圖為本發明一實施例製作半導體元件之上視圖，第2圖至第11圖則為第1圖中沿著切線AA’、切線BB’以及切線CC’方向製作半導體元件之剖面示意圖。如第1圖至第2圖所示，首先提供一基底12，例如一矽基底或矽覆絕緣(SOI)基板，其上定義有三個或三個以上的電晶體區，例如包括一高壓區14、一中壓區16以及一低壓區18，其中高壓區14中設有高壓元件114，中壓區16中設有中壓元件116，低壓區18中設有低壓元件118，且第2圖至第11圖較佳為沿著第1圖高壓區14中切線AA’、中壓區14中切線BB’以及低壓區18中切線CC’方向製作半導體元件的方法示意圖。在本實施例中，高壓區14、中壓區16以及低壓區18可包含相同導電型式或不同導電型式之電晶體區，例如各為PMOS電晶體區以及/或NMOS電晶體區，且三個區域分別預定為後續製作不同臨界電壓(threshold voltage)之閘極結構。在本實施例中可先選擇於高壓區14與中壓區16中利用離子佈植製程形成P型深井區並於低壓區18中形成N型深井區，但各區域的導電型式均不侷限於此。
然後於高壓區14與中壓區16的基底12上各形成基座20、22以及於低壓區18的基底上形成複數個鰭狀結構24。依據本發明之較佳實施例，基座20、22與鰭狀結構24較佳透過側壁圖案轉移(sidewall image transfer, SIT)技術製得，其程序大致包括：提供一佈局圖案至電腦系統，並經過適當地運算以將相對應之圖案定義於光罩中。後續可透過光微影及蝕刻製程，以形成多個等距且等寬之圖案化犧牲層或軸心體(mandrel)於基底上，使其個別外觀呈現條狀。之後依序施行沉積及蝕刻製程，以於圖案化犧牲層的各側壁形成側壁子。繼以去除圖案化犧牲層，並在側壁子的覆蓋下施行蝕刻製程，使得側壁子所構成之圖案被轉移至基底內，再伴隨鰭狀結構切割製程(fin cut)而獲得所需的圖案化結構，例如條狀圖案化鰭狀結構。
除此之外，基座20、22與鰭狀結構24之形成方式又可包含先形成一圖案化遮罩(圖未示)於基底12上，再經過一蝕刻製程，將圖案化遮罩之圖案轉移至基底12中以形成基座20、22與鰭狀結構24。另外，基座20、22與鰭狀結構24之形成方式另也可以是先製作一圖案化硬遮罩層(圖未示)於基底12上，並利用磊晶製程於暴露出於圖案化硬遮罩層之基底12上成長出例如包含矽鍺的半導體層，而此半導體層即可作為相對應的基座20、22與鰭狀結構24。這些形成基座20、22與鰭狀結構24的實施例均屬本發明所涵蓋的範圍。
在本實施例中，各基座20、22與鰭狀結構24頂表面可於上述圖案化過中設有一襯墊層26、一襯墊層28以及一硬遮罩30於基底12上，其中襯墊層26較佳包含氧化矽，襯墊層28較佳包含氮化矽，硬遮罩30較佳包含氧化矽，但均不侷限於此。
然後如第3圖所示，進行一可流動式化學氣相沉積(flowable chemical vapor deposition, FCVD)製程形成一由氧化矽所構成的絕緣層32於基座20、22與鰭狀結構24上並填滿基座20、22與鰭狀結構24之間的凹槽，再進行一平坦化製程例如利用化學機械研磨(chemical mechanical polishing, CMP)去除硬遮罩30使襯墊層28頂表面切齊絕緣層32頂表面。
隨後如第4圖所示，先利用蝕刻去除由氮化矽所構成的襯墊層28暴露出下方由氧化矽所構成的襯墊層26，使兩側的絕緣層32頂表面略為高於襯墊層26頂表面並同時形成凹槽(圖未示)於襯墊層26正上方，然後進行一離子佈植製程於高壓區14的基座20兩側內形成摻雜區34，其中摻雜區34較佳作為後續高壓元件的輕摻雜汲極。接著形成一硬遮罩36於高壓區14、中壓區16以及低壓區18的基座20、22、鰭狀結構24以及絕緣層32上並填滿襯墊層26上方的凹槽。在本實施例中硬遮罩36較佳包含氮化矽，但不侷限於此。
隨後如第5圖所示，先形成一圖案化遮罩38例如圖案化光阻於中壓區16與低壓區18的硬遮罩36上且圖案化遮罩38具有一開口暴露出高壓區14的部分硬遮罩36表面，再利用圖案化遮罩38為遮罩進行一蝕刻製程去除高壓區14的部分硬遮罩36、部分基座20與基座22兩側的部分絕緣層32形成凹槽40。
如第6圖所示，然後進行一氧化物成長製程或更具體而言一快速熱氧化(rapid thermal oxidation, RTO)製程以形成一由氧化矽所構成的閘極介電層42於高壓區14的基座20上，再完全去除圖案化遮罩38與下方的硬遮罩36。其中所成長的閘極介電層42兩側仍有部分之前利用圖案化遮罩所形成的凹槽40，且閘極介電層42頂表面較佳低於中壓區16與低壓區18的絕緣層32頂表面。
接著可形成另一圖案化遮罩(圖未示)例如圖案化光阻覆蓋高壓區14與中壓區16的絕緣層32且圖案化遮罩具有一開口暴露出低壓區18的襯墊層26與絕緣層32頂表面，進行一離子佈植製程將摻質植入低壓區18的鰭狀結構24內調整元件的臨界電壓(threshold voltage)，再去除圖案化遮罩。
隨後如第7圖所示，先全面性形成一由氮化矽所構成的硬遮罩44覆蓋高壓區14、中壓區16以及低壓區18包括高壓區14的閘極介電層42、中壓區16的基座24以及低壓區18的鰭狀結構24上，再形成另一圖案化遮罩46例如圖案化光阻覆蓋高壓區14與低壓區16的絕緣層32，且圖案化遮罩46具有一開口暴露出中壓區16的硬遮罩44。緊接著利用圖案化遮罩46為遮罩進行一蝕刻製程去除中壓區16的硬遮罩44、部分絕緣層32、襯墊層26甚至部分基座22並暴露出基座22表面。
然後如第8圖所示，先進行另一氧化物成長製程例如一快速熱氧化(rapid thermal oxidation, RTO)製程以形成一由氧化矽所構成的閘極介電層48於中壓區16的基座22上，其中中壓區16的閘極介電層48頂表面較佳高於高壓區14的閘極介電層42頂表面同時高壓區14的閘極介電層42厚度較佳大於中壓區16的閘極介電層48厚度。在本實施例中高壓區14的閘極介電層42厚度較佳約中壓區16的閘極介電層48厚度的1倍以上例如1.5倍甚至2倍。
接著去除原本設於高壓區14、中壓區16以及低壓區18的圖案化遮罩46與剩餘的硬遮罩44，再進行一蝕刻製程完全去除低壓區14鰭狀結構24頂部的襯墊層26並暴露出鰭狀結構24頂表面以及去除高壓區14、中壓區16以及低壓區18部分絕緣層32，使剩餘的絕緣層32頂表面略低於高壓區14與中壓區16的基座20、22以及低壓區18的鰭狀結構24頂表面形成淺溝隔離(shallow trench isolation, STI)50。需注意的是，在本階段高壓區14的閘極介電層42頂表面較佳低於中壓區16的閘極介電層48頂表面以及低壓區18的鰭狀結構24頂表面而中壓區16的閘極介電層48頂表面則較佳切齊低壓區18的鰭狀結構24頂表面。
如第9圖所示，隨後進行一氧化製程例如現場蒸氣成長製程(in-situ steam generation, ISSG)製程形成一由氧化矽所構成的閘極介電層52於低壓區18的鰭狀結構24表面。接著可於高壓區14、中壓區16以及低壓區18的基座20、22與鰭狀結構24上分別形成閘極結構54、56、58或虛置閘極。在本實施例中，閘極結構54、56、58的製作方式可依據製程需求以先閘極(gate first)製程、後閘極(gate last)製程之先高介電常數介電層(high-k first)製程或後閘極製程之後高介電常數介電層(high-k last)製程等方式製作完成。以本實施例之後高介電常數介電層製程為例，可先依序形成一由多晶矽所構成的閘極材料層60、一由氮化矽所構成的硬遮罩62、一由氧化矽所構成的硬遮罩64於各區域的閘極介電層42、48、52上，並利用一圖案化光阻(圖未示)當作遮罩進行一圖案轉移製程，以單次蝕刻或逐次蝕刻步驟，去除部分硬遮罩62、64以及部分閘極材料層60甚至中壓區16的部分閘極介電層48，然後剝除圖案化光阻，以於各區域的基底12上形成由閘極介電層42、48、52與圖案化之閘極材料層60所構成的閘極結構54、56、58，其中圖案化之閘極材料層60較佳成為各區域的閘極電極66。
隨後分別在閘極結構54、56、58側壁形成至少一側壁子(圖未示)。在本實施例中，側壁子可為單一側壁子或複合式側壁子，例如可細部包含一偏位側壁子(圖未示)以及一主側壁子(圖未示)，偏位側壁子與主側壁子較佳包含不同材料，且兩者均可選自由氧化矽、氮化矽、氮氧化矽以及氮碳化矽所構成的群組，但不侷限於此。
請繼續參照第10圖，第10圖為本發明一實施例沿著第1圖高壓區14中切線AA’、中壓區14中切線BB’以及低壓區18中切線DD’方向製作半導體元件的方法示意圖。如第10圖所示，進行一乾蝕刻及/或濕蝕刻製程，利用低壓區18的閘極結構58與側壁子為蝕刻遮罩，沿著側壁子向下單次或多次蝕刻基底12，以於閘極結構58兩側的基底12中形成凹槽(圖未示)。接著進行一選擇性磊晶成長(selective epitaxial growth, SEG)製程，以於凹槽中形成磊晶層68。需注意的是，本實施例僅於低壓區18的閘極結構58兩側形成磊晶層68但高壓區14與中壓區16則較佳不形成任何磊晶層。另外低壓區18的硬遮罩64可於形成凹槽時被部分去除，使低壓區18的硬遮罩64頂表面略低於高壓區14與中壓區16的硬遮罩64頂表面。
從第10圖的剖面來看，低壓區18的磊晶層68較佳與凹槽具有相同的截面形狀，如圓弧、六邊形(hexagon；又稱sigma Σ)或八邊形(octagon)之截面形狀，但也可以是其他截面形狀。於本發明較佳實施例中，磊晶層68根據不同之金氧半導體(MOS)電晶體類型而可以具有不同的材質，舉例來說，若該金氧半導體電晶體為一P型電晶體(PMOS)時，磊晶層68可選擇包含矽化鍺(SiGe)、矽化鍺硼(SiGeB)或矽化鍺錫(SiGeSn)。而於本發明另一實施例中，若該金氧半導體電晶體為一N型電晶體(NMOS)時，磊晶層68可選擇包含碳化矽(SiC)、碳磷化矽(SiCP)或磷化矽(SiP)。此外，選擇性磊晶製程可以用單層或多層的方式來形成，且其異質原子(例如鍺原子或碳原子)亦可以漸層的方式改變，但較佳是使磊晶層68的表面較淡或者無鍺原子，以利後續金屬矽化物層的形成。
隨後可先利用微影暨蝕刻製程去除中壓區16的部分閘極介電層48暴露出閘極結構56兩側的基座22頂表面，再進行一道或一道以上離子佈植製程，分別於高壓區14與中壓區16閘極結構54、56兩側的基座20、22內形成源極/汲極區域70，以及於高壓區14中高壓電晶體外圍的基座20內形成摻雜區作為靜電放電保護環72，其中高壓區14中的源極/汲極區域70與靜電放電保護環72較佳包含不同導電型式的摻質，例如一者包含N型摻質另一者則包含P型摻質。
依據本發明一實施例，又可選擇性於低壓區18中磊晶層68的一部分或全部形成源極/汲極區域70。在一實施例中，低壓區18中源極/汲極區域70的形成亦可同步(in-situ)於選擇性磊晶成長製程進行，例如金氧半導體是PMOS時，形成矽化鍺磊晶層、矽化鍺硼磊晶層或矽化鍺錫磊晶層，可以伴隨著注入P型摻質；或是當金氧半導體是NMOS時，形成矽化碳磊晶層、矽化碳磷磊晶層或矽化磷磊晶層，可以伴隨著注入N型摻質。藉此可省略後續利用額外離子佈植步驟形成P型/N型電晶體之源極/汲極區域70。此外在另一實施例中，源極/汲極區域70的摻質亦可以漸層的方式形成。
然後如第11圖所示，可選擇性形成一由氮化矽所構成的接觸洞蝕刻停止層(contact etch stop layer, CESL)(圖未示)於基底12上並覆蓋高壓區14、中壓區16以及低壓區18的閘極結構54、56、58，再形成一層間介電層74於接觸洞蝕刻停止層上。接著進行一平坦化製程，例如利用化學機械研磨(chemical mechanical polishing, CMP)去除部分層間介電層74及部分接觸洞蝕刻停止層使硬遮罩64上表面與層間介電層74上表面齊平。
隨後進行一金屬閘極置換製程將高壓區14、中壓區16以及低壓區18的各閘極結構54、56、58轉換為金屬閘極。例如可先進行一選擇性之乾蝕刻或濕蝕刻製程，例如利用氨水(ammonium hydroxide, NH 4OH)或氫氧化四甲銨(Tetramethylammonium Hydroxide, TMAH)等蝕刻溶液來去除硬遮罩62、64以及閘極結構54、56、58中的閘極材料層60以於層間介電層74中形成凹槽(圖未示)。之後依序形成一高介電常數介電層76以及至少包含功函數金屬層78與低阻抗金屬層80的導電層於凹槽內，並再搭配進行一平坦化製程使U型高介電常數介電層76、U型功函數金屬層78與低阻抗金屬層80的表面與層間介電層74表面齊平，其中高介電常數介電層76、功函數金屬層78與低阻抗金屬層80較佳一同各電晶體或各元件的閘極電極66。
在本實施例中，高介電常數介電層76包含介電常數大於4的介電材料，例如選自氧化鉿(hafnium oxide, HfO 2)、矽酸鉿氧化合物(hafnium silicon oxide, HfSiO 4)、矽酸鉿氮氧化合物(hafnium silicon oxynitride, HfSiON)、氧化鋁(aluminum oxide, Al 2O 3)、氧化鑭(lanthanum oxide, La 2O 3)、氧化鉭(tantalum oxide, Ta 2O 5)、氧化釔(yttrium oxide, Y 2O 3)、氧化鋯(zirconium oxide, ZrO 2)、鈦酸鍶（strontium titanate oxide, SrTiO 3）、矽酸鋯氧化合物(zirconium silicon oxide, ZrSiO 4)、鋯酸鉿(hafnium zirconium oxide, HfZrO 4)、鍶鉍鉭氧化物(strontium bismuth tantalate, SrBi 2Ta 2O 9, SBT)、鋯鈦酸鉛(lead zirconate titanate,  PbZr xTi 1-xO 3, PZT)、鈦酸鋇鍶(barium strontium titanate, Ba xSr 1-xTiO 3, BST)、或其組合所組成之群組。
功函數金屬層78較佳用以調整形成金屬閘極之功函數，使其適用於N型電晶體(NMOS)或P型電晶體(PMOS)。若電晶體為N型電晶體，功函數金屬層78可選用功函數為3.9電子伏特(eV)～4.3 eV的金屬材料，如鋁化鈦(TiAl)、鋁化鋯(ZrAl)、鋁化鎢(WAl)、鋁化鉭(TaAl)、鋁化鉿(HfAl)或TiAlC (碳化鈦鋁)等，但不以此為限；若電晶體為P型電晶體，功函數金屬層78可選用功函數為4.8 eV～5.2 eV的金屬材料，如氮化鈦(TiN)、氮化鉭(TaN)或碳化鉭(TaC)等，但不以此為限。功函數金屬層78與低阻抗金屬層80之間可包含另一阻障層(圖未示)，其中阻障層的材料可包含鈦(Ti)、氮化鈦(TiN)、鉭(Ta)、氮化鉭(TaN)等材料。低阻抗金屬層80則可選自銅(Cu)、鋁(Al)、鎢(W)、鈦鋁合金(TiAl)、鈷鎢磷化物(cobalt tungsten phosphide，CoWP)等低電阻材料或其組合。由於依據金屬閘極置換製程將虛置閘極轉換為金屬閘極乃此領域者所熟知技藝，在此不另加贅述。接著可去除部分高介電常數介電層76、部分功函數金屬層78與部分低阻抗金屬層80形成凹槽(圖未示)，然後再填入一硬遮罩82於凹槽內並使硬遮罩82與層間介電層74表面齊平，其中硬遮罩82可選自由氧化矽、氮化矽、氮氧化矽以及氮碳化矽所構成的群組。
之後可進行一圖案轉移製程，例如可利用一圖案化遮罩去除閘極結構54、56、58旁的部分的層間介電層74以及部分接觸洞蝕刻停止層以形成複數個接觸洞(圖未示)並暴露出源極/汲極區域70。然後再於各接觸洞中填入所需的金屬材料，例如包含鈦(Ti)、氮化鈦(TiN)、鉭(Ta)、氮化鉭(TaN)等的阻障層材料以及選自鎢(W)、銅(Cu)、鋁(Al)、鈦鋁合金(TiAl)、鈷鎢磷化物(cobalt tungsten phosphide，CoWP)等低電阻材料或其組合的低阻抗金屬層。之後進行一平坦化製程，例如以化學機械研磨去除部分金屬材料以分別形成接觸插塞84於各接觸洞內電連接源極/汲極區域70。至此即完成本發明較佳實施例一半導體元件的製作。
請再參照第1圖與第11圖，第1圖與第11圖又分別揭露本發明一實施例之一半導體元件之結構示意圖。如第1圖與第11圖所示，半導體元件主要包含一基底12具有高壓區14、中壓區16以及低壓區18，高壓元件114設於高壓區14，中壓元件116設於中壓區16以及低壓元件118設於低壓區18，靜電放電保護環72環繞高壓元件114以及淺溝隔離50環繞高壓元件114、中壓元件116以及低壓元件118。其中高壓元件114包含基座20設於基底12上、閘極介電層42設於基座20上、由高介電常數介電層76、功函數金屬層78與低阻抗金屬層80所構成的閘極電極66設於閘極介電層42上以及源極/汲極區域70設於閘極電極66兩側的基座20內。
中壓元件116包含基座22設於基底12上、閘極介電層48設於基座20上、由高介電常數介電層76、功函數金屬層78與低阻抗金屬層80所構成的閘極電極66設於閘極介電層48上以及源極/汲極區域70設於閘極電極66兩側的基座22內。低壓元件118則包含複數個鰭狀結構24設於基底12、閘極介電層52設於鰭狀結構24上、由高介電常數介電層76、功函數金屬層78與低阻抗金屬層80所構成的閘極電極66設於閘極介電層52上以及源極/汲極區域70設於閘極電極66兩側的鰭狀結構24或基底12內。
從細部來看，高壓區14的閘極電極66頂表面較佳切齊中壓區16與低壓區18的閘極電極66頂表面，高壓區14的閘極介電層42頂表面較佳低於中壓區16的閘極介電層48頂表面與低壓區18的鰭狀結構24頂表面但切齊淺溝隔離50頂表面，中壓區16的閘極介電層48頂表面較佳切齊低壓區18的鰭狀結構24頂表面，低壓區18的閘極介電層52頂表面可略高於中壓區16的閘極介電層48頂表面，高壓區14的源極/汲極區域70頂表面切齊低壓區18的鰭狀結構24頂表面，且靜電放電保護環72頂表面切齊源極/汲極區域70頂表面。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
12:基底 14:高壓區 16:中壓區 18:低壓區 20:基座 22:基座 24:鰭狀結構 26:襯墊層 28:襯墊層 30:硬遮罩 32:絕緣層 34:摻雜區 36:硬遮罩 38:圖案化遮罩 40:凹槽 42:閘極介電層 44:硬遮罩 46:圖案化遮罩 48:閘極介電層 50:淺溝隔離 52:閘極介電層 54:閘極結構 56:閘極結構 58:閘極結構 60:閘極材料層 62:硬遮罩 64:硬遮罩 66:閘極電極 68:磊晶層 70:源極/汲極區域 72:靜電放電保護環 74:層間介電層 76:高介電常數介電層 78:功函數金屬層 80:低阻抗金屬層 82:硬遮罩 84:接觸插塞 114:高壓元件 116:中壓元件 118:低壓元件
第1圖至第11圖為本發明一實施例製作半導體元件之方法示意圖。
12:基底
14:高壓區
16:中壓區
18低壓區
20:基座
22:基座
24:鰭狀結構
32:絕緣層
34:摻雜區
42:閘極介電層
48:閘極介電層
50:淺溝隔離
52:閘極介電層
54:閘極結構
56:閘極結構
58:閘極結構
66:閘極電極
70:源極/汲極區域
72:靜電放電保護環
74:層間介電層
76:高介電常數介電層
78:功函數金屬層
80:低阻抗金屬層
82:硬遮罩
84:接觸插塞
114:高壓元件
116:中壓元件
118:低壓元件

Claims (17)

  1. 一種製作半導體元件的方法，其特徵在於，包含： 提供一基底包含一高壓區、一中壓區以及一低壓區； 形成一高壓元件於該高壓區，該高壓元件包含： 一第一基座設於該基底上； 一第一閘極介電層設於該第一基座上；以及 一第一閘極電極設於該第一閘極介電層上； 形成一低壓元件於該低壓區，該低壓元件包含： 一鰭狀結構設於該基底上；以及 一第二閘極電極設於該鰭狀結構上，其中該第一閘極介電層頂表面低於該鰭狀結構頂表面。
  2. 如申請專利範圍第1項所述之方法，其中該第一閘極電極頂表面切齊該第二閘極電極頂表面。
  3. 如申請專利範圍第1項所述之方法，另包含： 形成該第一基座於該高壓區、一第二基座於該中壓區以及該鰭狀結構於該低壓區； 形成一絕緣層環繞該第一基座、該第二基座以及該鰭狀結構； 去除部分該第一基座； 形成該第一閘極介電層於該第一基座上； 形成一第二閘極介電層於該第二基座上； 去除該絕緣層以形成一淺溝隔離； 形成一第三閘極介電層於該鰭狀結構上； 形成該第一閘極電極於該第一閘極介電層上、該第二閘極電極於該第三閘極介電層上以及一第三閘極電極於該第二閘極介電層上； 形成一第一源極/汲極區域於該第一閘極電極旁；以及 形成一第二源極/汲極區域於該第二閘極電極旁。
  4. 如申請專利範圍第3項所述之方法，其中該第一閘極介電層頂表面低於該第二閘極介電層頂表面。
  5. 如申請專利範圍第3項所述之方法，其中該第一閘極電極頂表面切齊該第三閘極電極頂表面。
  6. 如申請專利範圍第3項所述之方法，其中該第一源極/汲極區域頂表面切齊該鰭狀結構頂表面。
  7. 如申請專利範圍第3項所述之方法，另包含形成一靜電放電保護環環繞該高壓元件。
  8. 如申請專利範圍第7項所述之方法，其中該靜電放電保護環頂表面切齊該第一源極/汲極區域頂表面。
  9. 一種半導體元件，其特徵在於，包含： 一基底包含一高壓區、一中壓區以及一低壓區； 一高壓元件設於該高壓區，該高壓元件包含： 一第一基座設於該基底上； 一第一閘極介電層設於該第一基座上；以及 一第一閘極電極設於該第一閘極介電層上； 一低壓元件設於該低壓區，該低壓元件包含： 一鰭狀結構設於該基底上；以及 一第二閘極電極設於該鰭狀結構上，其中該第一閘極介電層頂表面低於該鰭狀結構頂表面。
  10. 如申請專利範圍第9項所述之半導體元件，其中該第一閘極電極頂表面切齊該第二閘極電極頂表面。
  11. 如申請專利範圍第9項所述之半導體元件，其中該高壓元件包含一源極/汲極區域設於該第一閘極電極旁，且該源極/汲極區域頂表面切齊該鰭狀結構頂表面。
  12. 如申請專利範圍第11項所述之半導體元件，另包含一淺溝隔離設於該第一基座與該源極/汲極區域之間。
  13. 如申請專利範圍第11項所述之半導體元件，另包含形成一靜電放電保護環環繞該高壓元件。
  14. 如申請專利範圍第13項所述之半導體元件，其中該靜電放電保護環頂表面切齊該源極/汲極區域頂表面。
  15. 如申請專利範圍第9項所述之半導體元件，另包含一中壓元件設於該中壓區，該中壓元件包含： 一第二基座設於該基底上； 一第二閘極介電層設於該第二基座上；以及 一第三閘極電極設於該第二閘極介電層上。
  16. 如申請專利範圍第15項所述之半導體元件，其中該第一閘極介電層頂表面低於該第二閘極介電層頂表面。
  17. 如申請專利範圍第15項所述之半導體元件，其中該第一閘極電極頂表面切齊該第三閘極電極頂表面。
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