CN106803484B - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

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CN106803484B
CN106803484B CN201510843189.5A CN201510843189A CN106803484B CN 106803484 B CN106803484 B CN 106803484B CN 201510843189 A CN201510843189 A CN 201510843189A CN 106803484 B CN106803484 B CN 106803484B
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shallow trench
trench isolation
semiconductor device
gate
layer
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CN106803484A (zh
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曾奕铭
梁文安
黄振铭
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to US14/981,929 priority patent/US9824931B2/en
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Abstract

本发明公开一种半导体元件及其制作方法。该制作半导体元件的方法为首先提供一基底，该基底上具有一鳍状结构，然后形成一第一浅沟隔离于鳍状结构周围，将鳍状结构分隔为一第一部分与一第二部分，以及形成一第二浅沟隔离于第一部分及第二部分之间。

Description

半导体元件及其制作方法
技术领域
本发明涉及一种制作半导体元件的方法，尤其是涉及一种于鳍状结构与鳍状结构之间制作浅沟隔离的方法。
背景技术
近年来，随着场效晶体管(field effect transistors,FETs)元件尺寸持续地缩小，现有平面式(planar)场效晶体管元件的发展已面临制作工艺上的极限。为了克服制作工艺限制，以非平面(non-planar)的场效晶体管元件，例如鳍状场效晶体管(fin fieldeffect transistor,Fin FET)元件来取代平面晶体管元件已成为目前的主流发展趋势。由于鳍状场效晶体管元件的立体结构可增加栅极与鳍状结构的接触面积，因此，可进一步增加栅极对于载流子通道区域的控制，从而降低小尺寸元件面临的漏极引发能带降低(draininduced barrier lowering,DIBL)效应，并可以抑制短通道效应(short channel effect,SCE)。再者，由于鳍状场效晶体管元件在同样的栅极长度下会具有更宽的通道宽度，因而可获得加倍的漏极驱动电流。甚而，晶体管元件的临界电压(threshold voltage)亦可通过调整栅极的功函数而加以调控。
在现行的鳍状场效晶体管元件制作工艺中，鳍状结构经由分割后通常会填入绝缘物形成浅沟隔离。然而被分隔后的鳍状结构与鳍状结构之间的浅沟隔离通常会因制作工艺的因素形成扩口并影响后续栅极结构的设置。因此如何改良现有鳍状场效晶体管制作工艺与架构即为现今一重要课题。
发明内容
为解决上述问题，本发明优选实施例公开一种制作半导体元件的方法。首先提供一基底，该基底上具有一鳍状结构，然后形成一第一浅沟隔离于鳍状结构周围，将鳍状结构分隔为一第一部分与一第二部分，以及形成一第二浅沟隔离于第一部分及第二部分之间。
本发明另一实施例公开一种半导体元件，其包含：一基底；一鳍状结构设于基底上，该鳍状结构包含一第一部分以及一第二部分；以及一第一浅沟隔离设于第一部分及第二部分之间，且第一浅沟隔离具有一凹陷部。
附图说明
图1至图10为本发明优选实施例制作一半导体元件的方法示意图；
图11为本发明另一实施例的半导体元件结构示意图。
主要元件符号说明
12 基底 14 第一区域
16 第二区域 18 衬垫氧化层
20 衬垫氮化层 22 硬掩模
24 鳍状结构 26 沟槽
28 绝缘层 30 浅沟隔离
32 开口 34 第一部分
36 第二部分 38 绝缘层
40 浅沟隔离 42 凹陷部
44 栅极绝缘层 46 栅极结构
48 栅极结构 50 多晶硅材料
52 间隙壁 54 源极/漏极区域
56 外延层 58 接触洞蚀刻停止层
60 层间介电层 62 金属栅极
64 金属栅极 66 介质层
68 高介电常数介电层 70 功函数金属层
72 低阻抗金属层 74 接触洞蚀刻停止层
76 层间介电层 80 上凹表面
82 谷点 84 顶点
86 突起部 h 高度
具体实施方式
请参照图1至图10，图1至图10为本发明优选实施例制作一半导体元件的方法示意图。如图1所示，首先提供一基底12，例如一硅基底或硅覆绝缘(silicon on insulator,SOI)基板，并于基底12上定义一第一区域14与一第二区域16。在本实施例中，第二区域16优选于后续制作工艺中用来形成鳍状结构之间的浅沟隔离，第一区域14则为第二区域16旁的区域，或更具体而言第二区域16旁用来形成鳍状结构晶体管的主动区域。
然后依序形成一衬垫氧化层18、一衬垫氮化层20以及一由氧化物所构成的硬掩模22于基底12上，并进行一光刻暨蚀刻制作工艺，去除部分硬掩模22、部分衬垫氮化层20与部分衬垫氧化层18，以于基底12中上形成鳍状结构24以及一沟槽26环绕鳍状结构24。
接着如图2所示，进行一可流动式化学气相沉积(flowable chemical vapordeposition,FCVD)制作工艺形成一绝缘层28于硬掩模22上并填满沟槽26。其中绝缘层28可包含氧化物，例如二氧化硅，但不局限于此。
如图3所示，随后进行一平坦化制作工艺，例如利用化学机械研磨(chemicalmechanical polishing,CMP)去除部分绝缘层28、硬掩模22与衬垫氮化层20，使剩余的绝缘层28上表面与衬垫氧化层18上表面切齐并同时形成一浅沟隔离30于鳍状结构24周围。
如图4所示，接着进行一光刻暨蚀刻制作工艺，例如先形成一图案化掩模(图未示)于部分鳍状结构24与浅沟隔离30上并暴露第二区域14，然后利用蚀刻去除未被图案化掩模所遮蔽的部分衬垫氧化层18与部分鳍状结构24，以于鳍状结构24中形成一开口32并同时将鳍状结构24分隔为一第一部分34与第二部分36。
然后如图5所示，进行一原子沉积(atomic layer deposition,ALD)制作工艺以形成一绝缘层38于第一部分34与第二部分36上并填满开口32。在本实施例中，所形成的绝缘层38优选包含氧化物，例如二氧化硅，但不局限于此。
如图6所示，接着进行一蚀刻制作工艺去除部分绝缘层38与部分浅沟隔离30，使浅沟隔离30上表面略低于鳍状结构24上表面并同时形成另一浅沟隔离40于第二区域16，特别是鳍状结构24的第一部分34与第二部分36之间。值得注意的是，由于第一部分34与第二部分36之间的浅沟隔离40是以ALD方式所形成，而浅沟隔离30则是以可流动式化学气相沉积(FCVD)制作工艺来形成的，两者蚀刻选择比不同，因此以蚀刻去除部分绝缘层38形成浅沟隔离40与降低浅沟隔离30高度时设于第一区域14的浅沟隔离30优选维持一平坦表面而第二区域16的浅沟隔离40则具有一凹陷部42。
然后如图7所示，先形成一栅极绝缘层44于鳍状结构24的第一部分34与第二部分36表面以及第二区域16的鳍状结构24侧壁，再形成栅极结构46于第一区域14的鳍状结构24上以及形成栅极结构48于第二区域16的浅沟隔离40上。
栅极结构46、48的制作方式可依据制作工艺需求以先栅极(gate first)制作工艺、后栅极(gate last)制作工艺的先高介电常数介电层(high-k first)制作工艺以及后栅极制作工艺的后高介电常数介电层(high-k last)制作工艺等方式制作完成。以本实施例的后高介电常数介电层制作工艺为例，可先于鳍状结构24与浅沟隔离40上形成优选包含多晶硅材料50所构成的栅极结构46、48，然后于栅极结构46、48侧壁形成间隙壁52，其中间隙壁52可选自由二氧化硅、氮化硅、氮氧化硅以及氮碳化硅所构成的群组，但不局限于此。
接着于间隙壁52两侧的鳍状结构24以及/或基底12中形成一源极/漏极区域54及/或外延层56，并选择性于源极/漏极区域54及/或外延层56的表面形成一金属硅化物(图未示)。
如图8所示，然后形成一接触洞蚀刻停止层58于栅极结构46、48与基底12上，其中接触洞蚀刻停止层58可选择任何具有应力的材料，例如可选自由氮化硅以及氮碳化硅所构成的群组，但并不局限于此。
接着形成一层间介电层60于接触洞蚀刻停止层58与鳍状结构24上，并进行一平坦化制作工艺，例如利用CMP去除部分层间介电层60与部分接触洞蚀刻停止层58以暴露出由多晶硅材料50所构成的栅极电极，使栅极电极上表面与层间介电层60上表面齐平。其中层间介电层60可由任何包含氧化物的绝缘材料所构成，例如四乙氧基硅烷(Tetraethylorthosilicate,TEOS)，但不局限于此。
如图9所示，随后进行一金属栅极置换制作工艺将栅极结构46、48转换为金属栅极62、64。举例来说，可先进行一选择性的干蚀刻或湿蚀刻制作工艺，例如利用氨水(ammoniumhydroxide,NH4OH)或氢氧化四甲铵(Tetramethylammonium Hydroxide,TMAH)等蚀刻溶液来去除栅极结构46、48中的多晶硅材料50与部分栅极绝缘层44，以于层间介电层60中形成多个凹槽(图未示)。之后依序形成一介质层66、一高介电常数介电层68以及至少包含U型功函数金属层70与低阻抗金属层72的导电层于各凹槽内，其中介质层66优选设于第一部分34与第二部分36的侧壁。然后再搭配进行一平坦化制作工艺使U型高介电常数介电层68、U型功函数金属层70与低阻抗金属层72的表面与层间介电层60表面齐平。
在本实施例中，高介电常数介电层68包含介电常数大于4的介电材料，例如是选自氧化铪(hafnium oxide，HfO2)、硅酸铪氧化合物(hafnium silicon oxide，HfSiO4)、硅酸铪氮氧化合物(hafnium silicon oxynitride，HfSiON)、氧化铝(aluminum oxide，Al2O3)、氧化镧(lanthanum oxide，La2O3)、氧化钽(tantalum oxide，Ta2O5)、氧化钇(yttrium oxide，Y2O3)、氧化锆(zirconium oxide，ZrO2)、钛酸锶(strontium titanate oxide，SrTiO3)、硅酸锆氧化合物(zirconium silicon oxide，ZrSiO4)、锆酸铪(hafnium zirconium oxide，HfZrO4)、锶铋钽氧化物(strontium bismuth tantalate,SrBi2Ta2O9,SBT)、锆钛酸铅(leadzirconatetitanate,PbZrxTi1-xO3,PZT)、钛酸钡锶(barium strontium titanate,BaxSr1- xTiO3,BST)、或其组合所组成的群组。
功函数金属层70优选用以调整形成金属栅极的功函数，使其适用于N型晶体管(NMOS)或P型晶体管(PMOS)。若晶体管为N型晶体管，功函数金属层70可选用功函数为3.9电子伏特(eV)～4.3eV的金属材料，如铝化钛(TiAl)、铝化锆(ZrAl)、铝化钨(WAl)、铝化钽(TaAl)、铝化铪(HfAl)或TiAlC(碳化钛铝)等，但不以此为限；若晶体管为P型晶体管，功函数金属层70可选用功函数为4.8eV～5.2eV的金属材料，如氮化钛(TiN)、氮化钽(TaN)或碳化钽(TaC)等，但不以此为限。功函数金属层70与低阻抗金属层72之间可包含另一阻障层(图未示)，其中阻障层的材料可包含钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)等材料。低阻抗金属层72则可选自铜(Cu)、铝(Al)、钨(W)、钛铝合金(TiAl)、钴钨磷化物(cobalttungsten phosphide，CoWP)等低电阻材料或其组合。由于依据金属栅极置换制作工艺将虚置栅极转换为金属栅极是此领域者所熟知技术，在此不另加赘述。
之后如图10所示，可先选择性去除层间介电层60与接触洞蚀刻停止层58，然后再沉积另一接触洞蚀刻停止层74与层间介电层76于金属栅极62、64上。接着进行一接触插塞制作工艺，例如先形成多个接触洞(图未示)于层间介电层76与接触洞蚀刻停止层74中，然后于接触洞中填入所需的金属材料，包括依序形成一选自由钛(Ti)、氮化钛(TiN)、钽(Ta)及氮化钽(TaN)等群组所构成的阻障层以及一选自由钨(W)、铜(Cu)、铝(Al)、钛铝合金(TiAl)及钴钨磷化物(cobalt tungsten phosphide，CoWP)等低电阻材料所构成的金属层。随后搭配进行一平坦化制作工艺，例如以CMP去除部分阻障层与部分金属层以形成接触插塞78电连接金属栅极62、64与基底12内的源极/漏极区域54与外延层56。
请继续参照图10，其另公开本发明优选实施例的一半导体元件的结构示意图。如图10所示，本发明的半导体元件主要包含一鳍状结构24设于基底12上且鳍状结构24包含一第一部分34与第二部分36、一浅沟隔离30环绕第一部分34与第二部分36、一浅沟隔离40设于第一部分34与第二部分36之间，一栅极绝缘层44设于第一部分34与第二部分36上以及金属栅极62、64分别设于第一区域14与第二区域16。
在本实施例中，由于栅极绝缘层44与介质层66分别于不同阶段形成，因此栅极绝缘层44的厚度优选大于介质层66的厚度。另外设于第一区域14的金属栅极62上表面优选切齐第二区域16的金属栅极64上表面，且各金属栅极62、64更细部包含一高介电常数介电层68设于介质层66上、一功函数金属层70与一低阻抗金属层72。以第二区域16的金属栅极64来看，其高介电常数介电层68优选直接接触介质层66及浅沟隔离40。
从细部来看，设于第一部分34与第二部分36之间的浅沟隔离40优选包含一凹陷部42，其中凹陷部42包含一上凹表面80，上凹表面80包含一谷点(valley point)82与二顶点84，且二顶点84分别接触第一部分34与第二部分36的侧壁。
若以整个半导体元件来看，相较于浅沟隔离40是利用原子沉积制作工艺所形成因此具有前述的凹陷部42，环绕第一部分34与第二部分36的浅沟隔离30是以FCVD制作工艺所形成因此优选具有平坦表面。若与浅沟隔离40所设置的位置来比较，浅沟隔离30的上表面优选与浅沟隔离40上凹表面80的二顶点84切齐，或浅沟隔离40上凹表面80的谷点82优选略低于浅沟隔离30上表面。依据本发明的优选实施例，由谷点82至与浅沟隔离30上表面切齐的水平面的高度h优选小于10奈米。
请继续参照图11，图11为本发明另一实施例的半导体元件结构示意图。相较于图10中上凹表面80的二顶点84直接接触第一部分34与第二部分36的侧壁，本实施例的上凹表面80与第一部分34及第二部分36侧壁之间各具有一突起部86，且突起部86的上表面优选为一平整表面且与浅沟隔离30上表面切齐。
一般而言，现有将鳍状结构分割为两部分后会利用FCVD制作工艺同时于被分隔的鳍状结构之间以及鳍状结构周围形成浅沟隔离。然而通过FCVD制作工艺所形成的浅沟隔离通常含有氧原子，而此种浅沟隔离利用后续FCVD制作工艺所伴随的退火制作工艺处理后通常会与基底中的硅反映并再次撑大浅沟隔离的临界尺寸(critical dimension,CD)形成扩口，影响后续栅极结构的设置。为了改善此问题，本发明优选先形成一浅沟隔离于鳍状结构周围，将鳍状结构分割为第一部分与第二部分，然后在第一部分与第二部分之间利用ALD制作工艺方式填入绝缘材料形成浅沟隔离。由于以ALD方式所形成的浅沟隔离不会产生上述扩口情形，本发明可由此缩小单元间的临界尺寸并同时改善漏电流的情形。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (15)

1.一种制作半导体元件的方法，包含：
提供一基底，该基底上具有一鳍状结构；
利用可流动式化学气相沉积制作工艺形成一第一浅沟隔离于该鳍状结构周围；
将该鳍状结构分隔为一第一部分与一第二部分；
利用原子沉积制作工艺填入绝缘材料以形成一第二浅沟隔离于该第一部分及该第二部分之间。
2.如权利要求1所述的方法，还包含：
在形成该第一浅沟隔离后形成一开口于该鳍状结构中并由此将该鳍状结构分隔为该第一部分及该第二部分；
进行该原子沉积制作工艺以形成一绝缘层于该第一部分及该第二部分并填入该开口；以及
进行一蚀刻制作工艺去除部分该第一浅沟隔离及该绝缘层以形成该第二浅沟隔离。
3.如权利要求1所述的方法，其中该第二浅沟隔离包含一凹陷部。
4.如权利要求3所述的方法，其中该凹陷部包含一上凹表面，该上凹表面包含一谷点(valley point)与二顶点，且该二顶点分别接触该第一部分及该第二部分。
5.如权利要求4所述的方法，其中该第一浅沟隔离的上表面与该二顶点齐平。
6.如权利要求1所述的方法，其中该第一浅沟隔离的上表面为一平面。
7.如权利要求1所述的方法，还包含：
形成一栅极绝缘层于该第一部分及该第二部分上；
形成一栅极结构于该第二浅沟隔离上；
形成一间隙壁于该栅极结构周围；以及
将该栅极结构转换为一金属栅极。
8.一种如权利要求1所述方法制得的半导体元件，包含：
基底；
鳍状结构，设于该基底上，该鳍状结构包含第一部分以及第二部分；以及
第一浅沟隔离，设于该第一部分及该第二部分之间，且该第一浅沟隔离具有一凹陷部，该第一浅沟隔离是利用原子沉积制备工艺填入绝缘材料来形成。
9.如权利要求8所述的半导体元件，还包含：
栅极绝缘层，设于该第一部分及该第二部分上；
介质层，设于该第一部分及该第二部分的侧壁；以及
栅极结构，设于该介质层上。
10.如权利要求9所述的半导体元件，其中该栅极绝缘层的厚度大于该介质层的厚度。
11.如权利要求9所述的半导体元件，其中栅极结构包含：
高介电常数介电层，设于该介质层上；
功函数金属层，设于该高介电常数金属层上；以及
低阻抗金属层，设于该功函数金属层上。
12.如权利要求11所述的半导体元件，其中该高介电常数介电层直接接触该介质层及该第一浅沟隔离。
13.如权利要求8所述的半导体元件，其中该凹陷部包含一上凹表面，该上凹表面包含一谷点(valley point)与二顶点，且该二顶点分别接触该第一部分及该第二部分。
14.如权利要求13所述的半导体元件，还包含：
第二浅沟隔离环绕该第一部分及该第二部分，其中该第二浅沟隔离的上表面与该上凹表面的二顶点齐平。
15.如权利要求14所述的半导体元件，其中该第二浅沟隔离的上表面为一平坦表面。
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