CN104377124A - 半导体器件制造方法 - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 35
- 239000004065 semiconductor Substances 0.000 title claims description 26
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 229910052751 metal Inorganic materials 0.000 claims abstract description 51
- 239000002184 metal Substances 0.000 claims abstract description 50
- 238000005530 etching Methods 0.000 claims abstract description 41
- 238000009792 diffusion process Methods 0.000 claims abstract description 23
- 239000010410 layer Substances 0.000 claims description 83
- 230000004888 barrier function Effects 0.000 claims description 40
- 239000000463 material Substances 0.000 claims description 17
- 239000000945 filler Substances 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 14
- 229910010041 TiAlC Inorganic materials 0.000 claims description 12
- 239000011229 interlayer Substances 0.000 claims description 7
- 238000002955 isolation Methods 0.000 claims description 2
- 238000009413 insulation Methods 0.000 abstract description 4
- 230000010354 integration Effects 0.000 abstract description 4
- 230000000903 blocking effect Effects 0.000 abstract 3
- 230000015556 catabolic process Effects 0.000 abstract 1
- 238000006731 degradation reaction Methods 0.000 abstract 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 229910010038 TiAl Inorganic materials 0.000 description 4
- 238000003475 lamination Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 229910003855 HfAlO Inorganic materials 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910010413 TiO 2 Inorganic materials 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052761 rare earth metal Inorganic materials 0.000 description 1
- 150000002910 rare earth metals Chemical class 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
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Abstract
本发明提供了一种CMOS金属栅极的形成方法,采用了新的金属栅极堆栈结构,不需要在高K栅极绝缘层与刻蚀停止层之间形成扩散阻挡层也可阻挡Al扩散,并避免了由此而引起的高K栅极绝缘层和PMOS栅极功函数控制层的劣化;同时,由于取消了扩散阻挡层,在NMOS区域的NMOS栅极功函数控制层更加接近高K栅极绝缘层,从而能够更有效地控制NMOS功函数。本发明的金属栅极结构简化,厚度减小,适用于高集成度、小尺寸的CMOS器件。
Description
技术领域
本发明涉及半导体器件制造方法领域,特别地,涉及一种CMOS器件金属栅极的制造方法。
背景技术
半导体集成电路技术在进入到90nm特征尺寸的技术节点后,维持或提高晶体管性能越来越具有挑战性。在90nm节点后,应力技术逐渐被采用以提高器件的性能。与之同时,在制造工艺方面,后栅工艺(gate last)中的高K金属栅技术(HKMG)也逐渐被采用以应对随着器件不断减小而带来的挑战。HKMG的应用,可以在抑制泄露电流的同时,确保栅极绝缘层的EOT(Effective Oxide Thickness)。
通常,CMOS器件的金属栅极结构和制造方法如下(可以参见副图8(a)和9(a)):在衬底上先后依次形成高K栅极绝缘层31,扩散阻挡层32(通常为TiN),刻蚀停止层33(通常为TaN),PMOS栅极功函数控制层34(通常为TiN),然后,去除覆盖在NMOS区域的PMOS栅极功函数控制层34;接着,依次形成NMOS栅极功函数控制层35(通常为TiAl),金属填充层36(通常为TiN/Al叠层或TiN/W叠层);进行平坦化处理,去除多余的栅极堆栈材料,从而形成所需要的栅极堆栈。其中,扩散阻挡层32的作用是为了阻挡NMOS栅极功函数控制层35中的金属元素扩散而引起的高K栅极绝缘层31和PMOS栅极功函数控制层34的劣化。由此可以看出,在现有技术中,PMOS金属栅极堆栈至少包括高K栅极绝缘层31,扩散阻挡层32,刻蚀停止层33,PMOS栅极功函数控制层34,NMOS栅极功函数控制层35,金属填充层36这样6层结构,而NMOS金属栅极堆栈至少包括高K栅极绝缘层31,扩散阻挡层32,刻蚀停止层33,NMOS栅极功函数控制层35,金属填充层36这样5层结构,它们的结构均较为复杂,层数繁多。更不利的情况是,随着器件尺寸缩小,以及诸如FinFET等立体结构器件的出现,金属栅极堆栈的尺寸也越来越小,所要填充的空间的深宽比变大,使得多层结构、厚度较大的传统金属栅极堆栈在形成过程中存在问题,参见附图1,其中在衬底1上形成有容纳栅极凹槽的结构层2,结构层2在平面CMOS器件中通常为层间介质层,在FinFET器件中通常为相邻的半导体鳍片(Fin),尤其是对于FinFET器件,由于半导体鳍片高度较高,例如通常为25-40nm,覆盖鳍片的栅极高度通常为25-75nm,因此,在鳍片顶部的栅极表面距离鳍片之间的STI结构表面的高度为50-115nm,而鳍片间距较小,通常为30-50nm,FinFET结构体现出高低不平的三维表面,尤其是在栅极特征尺寸小于35nm时候,往往会出现了较大深宽比的结构需要填充栅极,因此,在形成金属栅极堆栈3时,往往会形成空洞4,这将严重影响器件性能,甚至导致器件失效。
因此,需要提供一种新的CMOS金属栅极结构和工艺,适用于高集成度、小尺寸的CMOS器件,能够克服上述缺陷,确保器件性能以及正常工作。
发明内容
针对CMOS金属栅极填充过程中存在的问题,本发明提出了一种半导体制造方法,采用新的金属栅极堆栈结构以及材料来克服现有技术中的问题。
本发明提供一种半导体器件制造方法,其中,包括如下步骤:
提供半导体衬底,在该半导体衬底上形成STI结构,所述STI结构将NMOS区域和PMOS区域隔离;
在所述NMOS区域和所述PMOS区域形成栅极凹槽;
依次形成高K栅极绝缘层,刻蚀停止层,PMOS栅极功函数控制层;
去除位于所述NMOS区域的所述PMOS栅极功函数控制层;
形成NMOS栅极功函数控制层,其中,所述NMOS栅极功函数控制层材料为TiAlC,厚度为0.1-5nm;
沉积金属填充层,将所述栅极凹槽完全填充;
进行CMP工艺,去除所述栅极凹槽以外的所述金属填充层、所述NMOS栅极功函数控制层、所述PMOS栅极功函数控制层、所述刻蚀停止层以及所述高K栅极绝缘层,在所述栅极凹槽内形成金属栅极堆栈。
根据本发明的一个方面,形成NMOS栅极功函数控制层的工艺为ALD。
根据本发明的一个方面,所述NMOS栅极功函数控制层材料TiAlC中的Al原子含量不大于50%。
根据本发明的一个方面,所述高K栅极绝缘层与所述刻蚀停止层之间不形成扩散阻挡层。
根据本发明的一个方面,在去除位于所述NMOS区域的所述PMOS栅极功函数控制层的步骤之后,将位于所述NMOS区域的所述刻蚀停止层完全去除,使得在所述NMOS区域的所述金属栅极堆栈中,所述NMOS栅极功函数控制层直接接触所述高K栅极绝缘层。
根据本发明的一个方面,在去除位于所述NMOS区域的所述PMOS栅极功函数控制层的步骤之后,将位于所述NMOS区域的所述刻蚀停止层部分去除,使得在所述NMOS区域的所述金属栅极堆栈中,所述NMOS栅极功函数控制层与所述高K栅极绝缘层之间残留部分厚度的所述刻蚀停止层,其厚度为0.1-3nm。
根据本发明的一个方面,所述栅极凹槽位于FinFET结构CMOS器件相邻半导体鳍片之间,或者,所述栅极凹槽位于平面结构CMOS器件的层间介质层之中。
另外,本发明还提供一种半导体器件,其包括:
半导体衬底,在该半导体衬底上的STI结构,以及被所述STI结构隔离的NMOS区域和PMOS区域;
所述NMOS区域和所述PMOS区域分别具有金属栅极堆栈;
所述NMOS的金属栅极堆栈由下而上依次包括:高K栅极绝缘层,刻蚀停止层,NMOS栅极功函数控制层,金属填充层;所述PMOS的金属栅极堆栈由下而上依次包括:高K栅极绝缘层,刻蚀停止层,PMOS栅极功函数控制层,NMOS栅极功函数控制层,金属填充层;
其中,所述NMOS栅极功函数控制层材料为TiAlC,厚度为0.1-5nm。
根据本发明的一个方面,,所述NMOS栅极功函数控制层材料TiAlC中的Al原子含量不大于50%。
根据本发明的一个方面,在所述NMOS区域和所述PMOS区域的金属栅极堆栈中,所述高K栅极绝缘层与所述刻蚀停止层之间不存在扩散阻挡层。
本发明的优点在于:在CMOS金属栅极形成工艺中,采用了新的金属栅极堆栈结构,具体为采用了TiAlC材料的NMOS栅极功函数控制层,其Al原子含量较现有技术中的NMOS栅极功函数控制层更小,从而,不需要在高K栅极绝缘层与刻蚀停止层之间形成扩散阻挡层也可阻挡Al扩散,并避免了由此而引起的高K栅极绝缘层和PMOS栅极功函数控制层的劣化,这样,金属栅极堆栈的结构简化,厚度减小;同时,由于取消了扩散阻挡层,在NMOS区域的NMOS栅极功函数控制层更加接近高K栅极绝缘层,从而能够更有效地控制NMOS功函数,在此基础上也可以将NMOS栅极功函数控制层的厚度减薄,从而获得厚度更小的栅极堆栈。综上所述,本发明的金属栅极结构简化,厚度减小,适用于高集成度、小尺寸的CMOS器件,能够克服现有技术中填充工艺出现空洞的缺陷,确保器件性能以及正常工作。
附图说明
图1现有技术中金属栅极堆栈填充出现空洞的示意图;
图2-7本发明形成金属栅极堆栈的工艺流程示意图;
图8-9本发明NMOS和PMOS的金属栅极堆栈结构(b)与现有技术金属栅极堆栈结构(a)的对比。
具体实施方式
以下,通过附图中示出的具体实施例来描述本发明。但是应该理解,这些描述只是示例性的,而并非要限制本发明的范围。此外,在以下说明中,省略了对公知结构和技术的描述,以避免不必要地混淆本发明的概念。
本发明提供一种半导体器件制造方法,特别地涉及一种用于形成CMOS金属栅极的方法。下面,参见附图2-9,将详细描述本发明提供的半导体器件制造方法。
首先,参见附图2,提供半导体衬底10,在半导体衬底10上形成STI结构13,STI结构13将NMOS区域12和PMOS区域11隔离,并且,在NMOS区域12和PMOS区域11分别形成有栅极凹槽16。在本实施例的图示中,采用了平面结构的CMOS,但是,本发明更有利地可以被用于包括FinFET结构的CMOS中。衬底10上还包括源漏区域14以及层间介质层15。在平面结构的CMOS器件中,栅极凹槽16形成在层间介质层15之中,具体的形成方式:现在衬底10上的不同MOS区域形成虚设栅极(Dummy Gate)和虚设栅极绝缘层(均未图示),虚设栅极通常为多晶硅栅极,虚设栅极绝缘层通常为氧化硅绝缘层,然后,形成MOS晶体管的源漏区域等部件;采用层间介质层15覆盖虚设栅极并进行平坦化,从而暴露出虚设栅极;之后,去除虚设栅极和虚设栅极绝缘层,形成栅极凹槽16。而在FinFET结构的CMOS器件中,栅极凹槽位于相邻半导体鳍片之间,具体形成工艺与平面结构CMOS器件栅极凹槽形成工艺类似,此处不再赘述。
由于本发明的方法应用于高密度集成的平面以及FinFET结构的CMOS电路中,用于容纳金属栅极和高K栅绝缘层(HKMG)的栅极凹槽16的宽度很小,例如在10-35nm,填充难度加大,尤其是在FinFET结构CMOS电路中,栅极凹槽16的深度和宽度分别可以达到50-115nm和10-35nm,其填充难度更大,这样,采用常规HKMG结构与工艺对栅极凹槽16进行填充,会出现空洞情况(例如附图1的情形),因此,本发明提出了新的HKMG结构和形成方法。同时,值得注意的是,虽然这里采用了平面结构CMOS的图示,但是本发明同样并且是更有利地可应用与栅极凹槽填充难度更大的FinFET结构CMOS电路中;同时,图示中的器件结构仅为简化示意图,本发明的CMOS器件中还可以包括但不限于:LDD、栅极侧墙、源漏区域接触等CMOS器件的常规部件,并且示意图中各部件所展现出的相对大小关系并不意味着它们实际尺寸比例。
接着,参见附图3,在界面氧化层(未图示)上,依次形成高K栅极绝缘层21,刻蚀停止层22,PMOS栅极功函数控制层23。高K栅极绝缘层21选自下面材料之一或组合构成的一层或者多层:Al2O3,HfO2,包括HfSiOx、HfSiON、HfAlOx、HfTaOx、HfLaOx、HfAlSiOx以及HfLaSiOx至少之一在内的铪基高K介质材料,包括ZrO2、La2O3、LaAlO3、TiO2、或Y2O3至少之一在内的稀土基高K介质材料。高K栅极绝缘层21的厚度为0.5-20nm,优选为1-10nm,沉积工艺例如为ALD、CVD。刻蚀停止层22的材料为TaN,其厚度范围是0.1-5nm。与现有技术的结构不同,本发明中,高K栅极绝缘层21与刻蚀停止层22不形成扩散阻挡层(例如TiN),具体理由将在随后进行详述。PMOS栅极功函数控制层23,其材料为TiN,厚度为0.1-5nm,采用ALD方式沉积,用于调节PMOS的栅极功函数。
接着,参见附图4,去除位于NMOS区域12的PMOS栅极功函数控制层23。可以通过掩模曝光,暴露出位于NMOS区域12的PMOS栅极功函数控制层23,而遮蔽位于PMOS区域11的PMOS栅极功函数控制层23,通过刻蚀工艺去除位于NMOS区域12的PMOS栅极功函数控制层23,具体可以采用干法、湿法刻蚀。刻蚀工艺停止在刻蚀停止层22上,随后,可以不去除或者部分去除或者全部去除刻蚀停止层22,其中,至少部分取出刻蚀停止层22可以进一步降低整个栅极堆栈的厚度。在全部去除刻蚀停止层22的情况下,NMOS区域的栅极堆栈中,随后形成的NMOS栅极功函数控制层24将直接接触高K栅极绝缘层21。在部分去除刻蚀停止层22的情况下,NMOS区域的栅极堆栈中,随后形成的NMOS栅极功函数控制层24与高K栅极绝缘层21之间残留部分厚度的刻蚀停止层22,其厚度为0.1-3nm。
接着,参见附图5,形成NMOS栅极功函数控制层24。NMOS栅极功函数控制层24的材料为TiAlC,相对于现有技术中所采用TiAl,TiAlC的Al含量更低,例如,Al原子含量不大于50%。采用ALD工艺沉积NMOS栅极功函数控制层24,可以精确控制其厚度,其厚度为0.1-5nm,优选地控制在1-2nm。而现有技术中的采用TiAl的NMOS栅极功函数控制层厚度通常在5nm以上,大于本发明的厚度。
接着,参见附图6,沉积金属填充层25,将栅极凹槽16完全填充。金属填充层25通常为TiN/Al叠层或TiN/W叠层,沉积工艺为CVD,厚度依据栅极凹槽16的形貌而定,其厚度需要完全填充栅极凹槽16。
接着参见附图7,进行CMP工艺,去除栅极凹槽16以外的金属填充层25、NMOS栅极功函数控制层24、PMOS栅极功函数控制层23、刻蚀停止层22以及高K栅极绝缘层21,在栅极凹槽内分别形成PMOS金属栅极堆栈20和NMOS金属栅极堆栈30。该步骤CMP以层间介质层15的表面为终点。
由此,获得了CMOS器件的金属栅极堆栈。参见图8和图9,分别是现有技术中的栅极堆栈与本发明栅极堆栈的对比,图8为NMOS的情形,图9为PMOS的情形,(a)图为现有技术中的栅极堆栈,(b)图为本发明的栅极堆栈。具体而言,现有技术中,NMOS金属栅极堆栈为高K栅极绝缘层31,扩散阻挡层32,刻蚀停止层33,NMOS栅极功函数控制层35,金属填充层36,PMOS金属栅极堆栈为高K栅极绝缘层31,扩散阻挡层32,刻蚀停止层33,PMOS栅极功函数控制层34,NMOS栅极功函数控制层35,金属填充层36;而本发明中,NMOS金属栅极堆栈30为高K栅极绝缘层21,刻蚀停止层22,NMOS栅极功函数控制层24,金属填充层25,其中,刻蚀停止层22可选地为部分厚度或被完全去除;PMOS金属栅极堆栈20为高K栅极绝缘层21,刻蚀停止层22,PMOS栅极功函数控制层23,NMOS栅极功函数控制层24,金属填充层25。本发明采用了TiAlC材料的NMOS栅极功函数控制层,因其Al原子含量较现有技术中的TiAl材料的NMOS栅极功函数控制层更小,不需要在高K栅极绝缘层21与刻蚀停止层22之间形成现有技术中的扩散阻挡层,Al原子的扩散也能够被阻挡,即没有扩散阻挡层也能避免由Al原子扩散此而引起的高K栅极绝缘层和PMOS栅极功函数控制层的劣化,这样,整个金属栅极堆栈(包括NMOS和PMOS)的结构得到简化,厚度也减小;同时,由于取消了现有技术中扩散阻挡层,在NMOS区域的NMOS栅极功函数控制层24更加接近高K栅极绝缘层21,从而能够更有效地控制NMOS功函数,而在此基础上,也可以将NMOS栅极功函数控制层24的厚度减薄,从而获得厚度更小的栅极堆栈。综上所述,本发明相对于现有技术,取消了扩散阻挡层,并且,采用了厚度更薄的NMOS栅极功函数控制层24,这使得金属栅极堆栈的结构简化,厚度减小,适用于高集成度、小尺寸的CMOS器件,能够克服现有技术中填充工艺出现空洞的缺陷,确保器件性能以及正常工作。
以上参照本发明的实施例对本发明予以了说明。但是,这些实施例仅仅是为了说明的目的,而并非为了限制本发明的范围。本发明的范围由所附权利要求及其等价物限定。不脱离本发明的范围,本领域技术人员可以做出多种替换和修改,这些替换和修改都应落在本发明的范围之内。
Claims (10)
1.一种半导体器件制造方法,其特征在于,包括如下步骤:
提供半导体衬底,在该半导体衬底上形成STI结构,所述STI结构将NMOS区域和PMOS区域隔离;
在所述NMOS区域和所述PMOS区域形成栅极凹槽;
依次形成高K栅极绝缘层,刻蚀停止层,PMOS栅极功函数控制层;
去除位于所述NMOS区域的所述PMOS栅极功函数控制层;
形成NMOS栅极功函数控制层,其中,所述NMOS栅极功函数控制层材料为TiAlC,厚度为0.1-5nm;
沉积金属填充层,将所述栅极凹槽完全填充;
进行CMP工艺,去除所述栅极凹槽以外的所述金属填充层、所述PMOS栅极功函数控制层、所述NMOS栅极功函数控制层、所述刻蚀停止层以及所述高K栅极绝缘层,在所述栅极凹槽内形成金属栅极堆栈。
2.根据权利要求1所述的方法,其特征在于,形成NMOS栅极功函数控制层的工艺为ALD。
3.根据权利要求1所述的方法,其特征在于,所述NMOS栅极功函数控制层材料TiAlC中的Al原子含量不大于50%。
4.根据权利要求1所述的方法,其特征在于,所述高K栅极绝缘层与所述刻蚀停止层之间不形成扩散阻挡层。
5.根据权利要求1所述的方法,其特征在于,在去除位于所述NMOS区域的所述PMOS栅极功函数控制层的步骤之后,将位于所述NMOS区域的所述刻蚀停止层完全去除,使得在所述NMOS区域的所述金属栅极堆栈中,所述NMOS栅极功函数控制层直接接触所述高K栅极绝缘层。
6.根据权利要求1所述的方法,其特征在于,在去除位于所述NMOS区域的所述PMOS栅极功函数控制层的步骤之后,将位于所述NMOS区域的所述刻蚀停止层部分去除,使得在所述NMOS区域的所述金属栅极堆栈中,所述NMOS栅极功函数控制层与所述高K栅极绝缘层之间残留部分厚度的所述刻蚀停止层,其厚度为0.1-3nm。
7.根据权利要求1所述的方法,其特征在于,所述栅极凹槽位于FinFET结构CMOS器件相邻半导体鳍片之间,或者,所述栅极凹槽位于平面结构CMOS器件的层间介质层之中。
8.一种半导体器件,其特征在于包括:
半导体衬底,在该半导体衬底上的STI结构,以及被所述STI结构隔离的NMOS区域和PMOS区域;
所述NMOS区域和所述PMOS区域分别具有金属栅极堆栈;
所述NMOS的金属栅极堆栈由下而上依次包括:高K栅极绝缘层,刻蚀停止层,NMOS栅极功函数控制层,金属填充层;所述PMOS的金属栅极堆栈由下而上依次包括:高K栅极绝缘层,刻蚀停止层,PMOS栅极功函数控制层,NMOS栅极功函数控制层,金属填充层;
其中,所述NMOS栅极功函数控制层材料为TiAlC,厚度为0.1-5nm。
9.根据权利要求8所述的器件,其特征在于,所述NMOS栅极功函数控制层材料TiAlC中的Al原子含量不大于50%。
10.根据权利要求8所述的器件,其特征在于,在所述NMOS区域和所述PMOS区域的金属栅极堆栈中,所述高K栅极绝缘层与所述刻蚀停止层之间不存在扩散阻挡层。
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