TWI662599B - 半導體裝置及其製作方法 - Google Patents

半導體裝置及其製作方法 Download PDF

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TWI662599B
TWI662599B TW104128778A TW104128778A TWI662599B TW I662599 B TWI662599 B TW I662599B TW 104128778 A TW104128778 A TW 104128778A TW 104128778 A TW104128778 A TW 104128778A TW I662599 B TWI662599 B TW I662599B
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layer
semiconductor device
contact plug
gate structure
lower contact
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TW104128778A
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TW201711091A (zh
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許家彰
林俊賢
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聯華電子股份有限公司
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Priority to US14/856,573 priority patent/US9793170B2/en
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Priority to US15/697,462 priority patent/US10283412B2/en
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Abstract

一種半導體裝置，包含有一基底；一第一閘極結構，設於該基底上；一第一側壁子，設於該第一閘極結構旁；一下部接觸插塞，靠近該第一閘極結構並接觸該第一側壁子；以及一第一懸凸部，設於該第一側壁子的上端緣。

Description

半導體裝置及其製作方法
本發明係關於一種半導體裝置，特別是有關於一種低阻值接觸結構及其製作方法。
隨著積體電路元件尺寸的微縮，金氧半場效電晶體(MOSFET)結構中的多晶矽閘極與二氧化矽絕緣層，已面臨到材料本身的物理極限。當元件尺寸必需再往下微縮時，則需導入高介電常數絕緣層及金屬閘極(high k/metal gate，簡稱HK/MG)製程。
目前的HK/MG製程可分為閘極先製(通常稱為MIPS，在多晶矽閘極與高介電常數介電層之間夾入金屬層)與閘極後製(也稱為RMG，置換金屬閘極)。「先製」與「後製」是指金屬電極層是在高溫退火之前或之後沉積。
通常，在RMG製程之後，才會開始進行接觸結構(M0 contact)的製作。目前，業界多採用自對準接觸結構(Self-Aligned Contact)。然而，即便採用了金屬閘極以及自對準接觸結構，該技術領域仍存在待克服的技術問題。
舉例來說，當閘極結構之間的間隙小於一定尺度時，例如10奈米，以現行製程所製備的自對準接觸結構即無法滿足元件的電性需求。製程的對位誤差，導致最終的自對準接觸結構產生側向偏移。當自對準接觸結構偏離預定的位置時，自對準接觸結構與下方主動區域間的接觸面積便會減少，導致了接觸電阻(Rc)的上升。
本發明於是提出一種經改良的低阻值接觸結構及其製作方法，可以相容於置換金屬閘極(RMG)製程，藉此解決上述先前技藝的不足與缺點。
根據本發明一實施例，本發明批露一種半導體裝置，包含有一基底；一第一閘極結構，設於該基底上；一第一側壁子，設於該第一閘極結構旁；一下部接觸插塞，靠近該第一閘極結構並接觸該第一側壁子；以及一第一懸凸部，設於該第一側壁子的上端緣。
根據本發明一實施例，其中該半導體裝置另包含一第二閘極結構，設於該基底上；一第二側壁子，位於該第二閘極結構旁；以及一第二懸凸部，設於該第二側壁子的上端緣；其中該下部接觸插塞係位於該第一閘極結構及該第二閘極結構之間，且該下部接觸插塞接觸到該第一側壁子及該第二側壁子，其中介於該第一側壁子及該第二側壁子之間的該下部接觸插塞具有一瓶狀輪廓。
根據本發明一實施例，其中該半導體裝置另包含一層間介電層，覆蓋該第一閘極結構、該第二閘極結構、該第一懸凸部以及該第二懸凸部；以及至少一上部接觸插塞，位於該層間介電層中，並直接位於該下部接觸插塞上，使該上部接觸插塞電連接該下部接觸插塞。
根據本發明又一實施例，本發明批露一種半導體裝置的製作方法。首先提供一基底，其上具有一虛設閘極結構，一側壁子，位於該虛設閘極結構的側壁上，以及一汲極/源極區域，靠近該虛設閘極結構。再於該汲極/源極區域上形成一犧牲層，再於該犧牲層上形成一蓋層，接著進行一置換金屬閘極製程，將該虛設閘極結構置換成一金屬閘極。再於該蓋層中形成一開口，顯露出該犧牲層的一上表面。接著經由該開口去除該犧牲層，藉此形成一下部接觸洞，顯露出全部該汲極/源極區域。然後，於該下部接觸洞中形成一下部接觸插塞。
為讓本發明之上述目的、特徵及優點能更明顯易懂，下文特舉較佳實施方式，並配合所附圖式，作詳細說明如下。然而如下之較佳實施方式與圖式僅供參考與說明用，並非用來對本發明加以限制者。
在下文中，將參照附圖說明細節，該些附圖中之內容亦構成說明書細節描述的一部份，並且以可實行該實施例之特例描述方式來繪示。下文實施例已描述足夠的細節俾使該領域之一般技藝人士得以具以實施。當然，亦可採行其他的實施例，或是在不悖離文中所述實施例的前提下作出任何結構性、邏輯性、及電性上的改變。因此，下文之細節描述不應被視為是限制，反之，其中所包含的實施例將由隨附的申請專利範圍來加以界定。
本發明實施例係提供一種接觸插塞的製作方法，結合閘極後製的置換金屬閘極(RMG)製程，其主要特徵在於：進行RMG製程前，預先於閘極之間的間隙埋入一虛設非晶矽(dummy a-Si)層，隨後以高密度電漿沉積氧化層(HDP oxide)覆蓋非晶矽層，待完成RMG製程後，再進行接觸結構的金屬置換(M0 contact replacement)步驟，將預先埋入在間隙內的虛設非晶矽層以金屬層取代，如此確保能形成一低阻值接觸結構。
請參閱第1圖至第8圖，其為依據本發明一較佳實施例所繪示的接觸結構的製作方法示意圖。如第1圖所示，首先提供一基底10，例如一半導體基底或矽基底，但不限於此。根據本發明一實施例，基底10上可以設有複數個鰭狀結構(圖未示)。
接著，在基底10的表面上形成至少兩相鄰的虛設閘極結構20及30。根據本發明一實施例，虛設閘極結構20包含有至少一犧牲層201及一蓋層202，例如，犧牲層201可以包含非晶矽或多晶矽，蓋層202可以包含氮化矽，但不限於此。根據本發明一實施例，虛設閘極結構30包含有至少一犧牲層301及一蓋層302，例如，犧牲層301可以包含非晶矽或多晶矽，蓋層302可以包含氮化矽，但不限於此。在犧牲層201與基底10之間，可以設有一閘極氧化層203，在犧牲層301與基底10之間，可以設有一閘極氧化層303。閘極氧化層203、303可以例如是二氧化矽層，但不限於此。
根據本發明一實施例，虛設閘極結構20及30可以是直線平行排列，並且跨設在基底10的鰭狀結構(圖未示)上。
根據本發明一實施例，在虛設閘極結構20的側壁上，可以形成有至少一側壁子205，例如，氮化矽側壁子，但不限於此。在虛設閘極結構30的側壁上，可以形成有至少一側壁子305，例如，氮化矽側壁子，但不限於此。
根據本發明一實施例，在基底10中設有一導電區域110，例如，一重摻雜汲極/源極區域，但不限於此。根據本發明一實施例，導電區域110可以包含一磊晶層(圖未示)，例如，矽鍺(SiGe)磊晶層或矽磷(SiP)磊晶層，但不限於此。根據本發明一實施例，在基底10中還可設有一輕摻雜汲極(LDD)區域120，直接位於側壁子205或側壁子305的正下方。
此外，根據本發明一實施例，可選擇性的在虛設閘極結構20、30上以及導電區域110表面上順形的覆蓋一接觸蝕刻停止層(圖未示)，例如，氮化矽薄膜。
根據本發明一實施例，在兩相鄰的虛設閘極結構20及30之間，具有一間隙40，其底部顯露出導電區域110的上表面。如前所述，由於間隙40隨著半導體製程的演進，越做越小，相對的使得其底部顯露出的導電區域110的面積也跟著減少，一旦自對準接觸結構稍微產生偏移，就會明顯導致接觸電阻(Rc)的上升。本發明可以解決這個問題。
如第2圖所示，根據本發明一實施例，接著在間隙40內填入一犧牲層50，例如，非晶矽(a-Si)層，但不限於此。犧牲層50具有一頂面50a，其低於虛設閘極結構20及30的上表面。形成犧牲層50的作法，例如，先以化學氣相沉積法，全面沉積一材料層，例如，非晶矽層，使其填滿間隙40，再施以化學機械研磨(CMP)或回蝕刻製程，去除部分的材料層，僅留下間隙40內的材料層。
如第3圖所示，隨後於犧牲層50上覆蓋一蓋層60，例如，高密度電漿矽氧(HDP oxide)層，使蓋層60與犧牲層50共同填滿間隙40。根據本發明一實施例，形成蓋層60的作法，例如，進行一高密度電漿化學氣相沉積(HDP CVD)製程，全面沉積一高密度電漿矽氧層，覆蓋在虛設閘極結構20及30上，並填入間隙40內，覆蓋住犧牲層50，再施以化學機械研磨(CMP)，去除部分的高密度電漿矽氧層，直到虛設閘極結構20及30的蓋層202及302被顯露出來，最後僅留下間隙40內的高密度電漿矽氧層。
如第4圖所示，接著進行置換金屬閘極(RMG)製程，例如，先去除虛設閘極結構20及30，包括犧牲層201、301及蓋層202、302，形成閘極溝槽220及320。然後，分別於閘極溝槽220及320內形成高介電常數介電層221、321、置換金屬閘極222、322以及蓋層223、323。如此，形成置換閘極結構20’、30’。
根據本發明一實施例，上述高介電常數介電層221、321可選自氧化鉿(hafnium oxide, HfO2 )、矽酸鉿氧化合物(hafnium silicon oxide, HfSiO4 )、矽酸鉿氮氧化合物(hafnium silicon oxynitride, HfSiON)、氧化鋁(aluminum oxide, Al2 O3 )、氧化鑭(lanthanum oxide, La2 O3 )、氧化鉭(tantalum oxide, Ta2 O5 )、氧化釔(yttrium oxide, Y2 O3 )、氧化鋯(zirconium oxide, ZrO2 )、鈦酸鍶(strontium titanate oxide, SrTiO3 )、矽酸鋯氧化合物(zirconium silicon oxide, ZrSiO4 )、鋯酸鉿(hafnium zirconium oxide, HfZrO4 )、鍶鉍鉭氧化物(strontium bismuth tantalate, SrBi2 Ta2 O9 , SBT)、鋯鈦酸鉛(lead zirconate titanate, PbZrx Ti1 -xO3 , PZT)與鈦酸鋇鍶(barium strontium titanate, Bax Sr1 -xTiO3 , BST)所組成之群組。
根據本發明一實施例，上述置換金屬閘極222、322可以是多層結構，例如為依序填入的一底阻障層、一功函數金屬層、一頂阻障層以及一主導電層。底阻障層例如為氮化鉭(tantalum nitride, TaN)、氮化鈦(titanium nitride, TiN)等之單層結構或複合層結構。功函數金屬層係為一滿足電晶體所需功函數要求的金屬，其可為單層結構或複合層結構，例如氮化鈦(titanium nitride, TiN)、碳化鈦(titanium carbide, TiC)、氮化鉭(tantalum nitride, TaN)、碳化鉭(tantalum carbide, TaC)、碳化鎢(tungsten carbide, WC)、鋁化鈦(titanium aluminide, TiAl)或氮化鋁鈦(aluminum titanium nitride, TiAlN)等。頂阻障層例如為氮化鉭(tantalum nitride, TaN)、氮化鈦(titanium nitride, TiN)等之單層結構或複合層結構。主導電層可由鋁、鎢、鈦鋁合金(TiAl)或鈷鎢磷化物(cobalt tungsten phosphide, CoWP)等低電阻材料所構成。
根據本發明一實施例，上述蓋層223、323可以是例如氮化矽，但不限於此。此時，蓋層223、323的上表面約略與蓋層60的頂面60a同一平面，或者，蓋層60的頂面60a可以略低於蓋層223、323的上表面。
如第5圖所示，在完成置換金屬閘極(RMG)製程之後，接著在蓋層223、323的上表面以及蓋層60的頂面60a上形成一光阻(或蝕刻抵擋)圖案70，其包括一開口70a，顯露出部分蓋層60的頂面60a，其中開口70a係位於導電區域110的正上方。根據本發明一實施例，開口70a的寬度可以小於或等於導電區域110的寬度，但不限於此。接著，利用一蝕刻製程，經由開口70a蝕刻蓋層60，在蓋層60中形成一開口602，使部分的犧牲層50的頂面50a被顯露出來。隨後，再將光阻圖案70去除。
根據本發明一實施例，剩下的蓋層60緊貼在側壁子205、305的上端構成一懸凸部(overhang feature)60b。此懸凸部60b可補償側壁子205、305的上端厚度的不足，進而能改善電氣性能。
如第6圖所示，接著進行一蝕刻製程，例如，濕蝕刻製程，經由開口602選擇性的蝕刻掉犧牲層50，如此在開口602下方形成一較寬的開口502。開口502顯露出部分位於懸凸部60b以下的側壁子205、305表面，並且完整的顯露出導電區域110。根據本發明一實施例，開口602與開口502可構成一具有瓶狀輪廓的開口(或稱為「下部接觸洞」)600。此時，懸凸部60b與側壁子205、305之間會形成一底切(undercut)結構605。
根據本發明另一實施例，若側壁子205、305上以及導電區域110設有一接觸蝕刻停止層(圖未示)，例如，氮化矽薄膜，在蝕刻掉犧牲層50之後，可以繼續進行另一蝕刻製程，以去除導電區域110上的接觸蝕刻停止層。
如第7圖所示，接下來，可以進行一化學氣相沉積(CVD)製程，例如，原子層沉積(atomic layer deposition, ALD)法，或其他沉積方法，順形的在開口600的內壁上，包括懸凸部60b與側壁子205、305的表面，以及導電區域110的表面，沉積一黏著層802。根據本發明一實施例，黏著層802可以包括，但不限於，鈦、氮化鈦。根據本發明另一實施例，黏著層802可以沉積在開口600以外的區域，例如，蓋層223、323的上表面。
然後，繼續利用另一沉積製程，於黏著層802上形成一低阻值導電層804，例如，鎢金屬層。根據本發明一實施例，低阻值導電層804填滿開口600。再進行一化學機械研磨製程，將開口600外的黏著層802及低阻值導電層804去除，而留在開口600內的黏著層802及低阻值導電層804即構成一下部接觸插塞800。根據本發明一實施例，對應於具有瓶狀輪廓的開口600，下部接觸插塞800包含一較窄的上部以及一較寬的底部。
如第8圖所示，接下來，全面沉積一層間介電(ILD)層90，例如，矽氧層。層間介電層90覆蓋下部接觸插塞800以及蓋層223、323。接著，再進行微影及蝕刻製程，於層間介電層90中形成一開口(或稱為「上部接觸洞」)90a。開口90a可以位於下部接觸插塞800的正上方，顯露出下部接觸插塞800。
隨後，進行一化學氣相沉積製程，例如，原子層沉積法，或其他沉積方法，順形的在開口90a的內壁上，以及層間介電層90的表面，沉積一黏著層902。根據本發明一實施例，黏著層902可以包括，但不限於，鈦、氮化鈦。繼續利用另一沉積製程，於黏著層902上形成一低阻值導電層904，例如，鎢金屬層。根據本發明一實施例，低阻值導電層904填滿開口90a。再進行一化學機械研磨製程，將開口90a外的黏著層902及低阻值導電層904去除，而留在開口90a內的黏著層902及低阻值導電層904即構成一上部接觸插塞900。上部接觸插塞900結合下部接觸插塞800，即構成本發明的低阻值接觸結構。
結構上，如第8圖所示，本發明實施例提供一種半導體裝置1，包含有一基底10，一第一閘極結構20’，設於基底10上，一第一側壁子205，設於第一閘極結構20’旁，一下部接觸插塞800，靠近第一閘極結構20’並接觸第一側壁子205，以及一第一懸凸部60b，設於第一側壁子205的上端緣。第一懸凸部60b與第一側壁子205之間具有一底切結構605。下部接觸插塞800包含一第一鎢金屬層804以及一第一黏著層802。
根據本發明一實施例，半導體裝置1另包含一第二閘極結構30’，設於基底10上，一第二側壁子305，位於第二閘極結構30’旁，以及一第二懸凸部60b，設於第二側壁子305的上端緣。其中下部接觸插塞800係位於第一閘極結構20’及第二閘極結構30’之間，且下部接觸插塞800接觸到第一側壁子205及第二側壁子305，其中介於第一側壁子205及第二側壁子305之間的下部接觸插塞800具有一瓶狀輪廓。
根據本發明一實施例，半導體裝置1另包含一層間介電層90，覆蓋第一閘極結構20’、第二閘極結構30’、第一懸凸部60b以及第二懸凸部60b，以及至少一上部接觸插塞900，位於層間介電層90中，並直接位於下部接觸插塞800上，使上部接觸插塞900電連接下部接觸插塞800。
熟習該項技藝者應理解，上部接觸插塞900亦可以形成在第一閘極結構20’或第二閘極結構30’正上方，以電連接第一閘極結構20’或第二閘極結構30’，但未繪示於此圖剖面中。
第9圖為依據本發明另一較佳實施例所繪示的接觸結構的剖面示意圖。如第9圖所示，接續第6圖，在開口600的內沉積黏著層802以及填入低阻值導電層804之後，再進行一化學機械研磨製程，將開口600外的黏著層802及低阻值導電層804去除，而留在開口600內的黏著層802及低阻值導電層804即構成一下部接觸插塞800。此時，可以藉由調整化學機械研磨製程參數，使得低阻值導電層804的上表面呈現一略微上凸輪廓800a。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
1‧‧‧半導體裝置
10‧‧‧基底
20、30‧‧‧虛設閘極結構
20’、30’‧‧‧置換閘極結構
40‧‧‧間隙
50‧‧‧犧牲層
50a‧‧‧頂面
60‧‧‧蓋層
60a‧‧‧頂面
60b‧‧‧懸凸部
70‧‧‧光阻圖案
70a‧‧‧開口
90‧‧‧層間介電層
90a‧‧‧開口(上部接觸洞)
110‧‧‧導電區域
120‧‧‧輕摻雜汲極區域
201、301‧‧‧犧牲層
202、302‧‧‧蓋層
203、303‧‧‧閘極氧化層
205、305‧‧‧側壁子
221、321‧‧‧高介電常數介電層
222、322‧‧‧置換金屬閘極
223、323‧‧‧蓋層
502、602‧‧‧開口
600‧‧‧具有瓶狀輪廓的開口(下部接觸洞)
605‧‧‧底切結構
800‧‧‧下部接觸插塞
800a‧‧‧上凸輪廓
802‧‧‧黏著層
804‧‧‧低阻值導電層
900‧‧‧上部接觸插塞
902‧‧‧黏著層
904‧‧‧低阻值導電層
第1圖至第8圖為依據本發明一較佳實施例所繪示的接觸結構的製作方法示意圖。第9圖為依據本發明另一較佳實施例所繪示的接觸結構的剖面示意圖。

Claims (20)

  1. 一種半導體裝置，包含有： 一基底； 一第一閘極結構，設於該基底上； 一第一側壁子，設於該第一閘極結構旁； 一下部接觸插塞，靠近該第一閘極結構並接觸該第一側壁子；以及 一第一懸凸部，設於該第一側壁子的上端緣。
  2. 如申請專利範圍第1項所述的半導體裝置，其中該下部接觸插塞包含一第一鎢金屬層以及一第一黏著層。
  3. 如申請專利範圍第2項所述的半導體裝置，其中該第一黏著層位於該第一側壁子與該第一鎢金屬層之間。
  4. 如申請專利範圍第2項所述的半導體裝置，其中該第一黏著層位於該第一懸凸部與該第一鎢金屬層之間。
  5. 如申請專利範圍第2項所述的半導體裝置，其中該第一黏著層包含鈦或氮化鈦。
  6. 如申請專利範圍第1項所述的半導體裝置，其中該第一懸凸部包含氧化矽。
  7. 如申請專利範圍第1項所述的半導體裝置，其中該第一懸凸部的上表面係與該第一閘極結構的上表面共平面。
  8. 如申請專利範圍第1項所述的半導體裝置，其中該第一懸凸部與該第一側壁子之間具有一底切結構。
  9. 如申請專利範圍第1項所述的半導體裝置，其中該下部接觸插塞包含一較窄的上部以及一較寬的底部。
  10. 如申請專利範圍第3項所述的半導體裝置，其中另包含： 一第二閘極結構，設於該基底上； 一第二側壁子，位於該第二閘極結構旁；以及 一第二懸凸部，設於該第二側壁子的上端緣； 其中該下部接觸插塞係位於該第一閘極結構及該第二閘極結構之間，且該下部接觸插塞接觸到該第一側壁子及該第二側壁子，其中介於該第一側壁子及該第二側壁子之間的該下部接觸插塞具有一瓶狀輪廓。
  11. 如申請專利範圍第10項所述的半導體裝置，其中另包含： 一層間介電層，覆蓋該第一閘極結構、該第二閘極結構、該第一懸凸部以及該第二懸凸部；以及 至少一上部接觸插塞，位於該層間介電層中，並直接位於該下部接觸插塞上，使該上部接觸插塞電連接該下部接觸插塞。
  12. 如申請專利範圍第11項所述的半導體裝置，其中另包含： 一第二黏著層，介於該上部接觸插塞與該下部接觸插塞之間。
  13. 如申請專利範圍第12項所述的半導體裝置，其中該第二黏著層包含鈦或氮化鈦。
  14. 一種半導體裝置的製作方法，包含有： 提供一基底，其上具有一虛設閘極結構，一側壁子，位於該虛設閘極結構的側壁上，以及一汲極/源極區域，靠近該虛設閘極結構； 於該汲極/源極區域上形成一犧牲層； 於該犧牲層上形成一蓋層，其中該蓋層的一上表面係與該虛設閘極結構的一上表面共平面； 進行一置換金屬閘極製程，將該虛設閘極結構置換成一置換閘極結構； 於該蓋層中形成一開口，顯露出該犧牲層的一上表面； 經由該開口去除該犧牲層，藉此形成一下部接觸洞，顯露出全部該汲極/源極區域；以及 於該下部接觸洞中形成一下部接觸插塞。
  15. 如申請專利範圍第14項所述的半導體裝置的製作方法，其中另包含： 於該置換閘極結構、該蓋層以及該下部接觸插塞上沉積一層間介電層；以及 於該層間介電層中形成一上部接觸插塞，其中該上部接觸插塞電連接該下部接觸插塞。
  16. 如申請專利範圍第14項所述的半導體裝置的製作方法，其中該犧牲層包含非晶矽。
  17. 如申請專利範圍第16項所述的半導體裝置的製作方法，其中該蓋層包含矽氧層。
  18. 如申請專利範圍第16項所述的半導體裝置的製作方法，其中該蓋層包含高密度電漿矽氧層。
  19. 如申請專利範圍第14項所述的半導體裝置的製作方法，其中該置換閘極結構包含一高介電常數介電層、一底阻障層、一功函數金屬層、一頂阻障層，以及一主導電層。
  20. 如申請專利範圍第14項所述的半導體裝置的製作方法，其中該下部接觸插塞包含一黏著層以及一鎢金屬層。
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