CN112736079A - 具有连接pmos区域栅极结构的接触插塞的半导体元件 - Google Patents

具有连接pmos区域栅极结构的接触插塞的半导体元件 Download PDF

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CN112736079A
CN112736079A CN201911033932.5A CN201911033932A CN112736079A CN 112736079 A CN112736079 A CN 112736079A CN 201911033932 A CN201911033932 A CN 201911033932A CN 112736079 A CN112736079 A CN 112736079A
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contact plug
gate structure
gate
semiconductor device
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陈士程
何立轩
吕佐文
梁世豪
吴宗训
庄博仁
许启茂
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to US16/695,028 priority patent/US11171091B2/en
Publication of CN112736079A publication Critical patent/CN112736079A/zh
Priority to US17/493,852 priority patent/US11756888B2/en
Priority to US18/226,784 priority patent/US20230369227A1/en
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Abstract

本发明公开一种一种具有连接PMOS区域栅极结构的接触插塞的半导体元件，该半导体元件主要包含一基底，该基底包含一NMOS区域以及一PMOS区域，一栅极结构由NMSO区域至PMOS区域沿着第一方向延伸于基底上以及一第一接触插塞设于栅极结构上，其中第一接触插塞由一分隔NMOS区域及PMOS区域的交界线偏向PMOS区域。半导体元件另包含一第一源极/漏极区域沿着第二方向延伸于栅极结构两侧的NMOS区域上以及一第二源极/漏极区域沿着第二方向延伸于栅极结构两侧的PMOS区域上。

Description

具有连接PMOS区域栅极结构的接触插塞的半导体元件
技术领域
本发明涉及一种半导体元件，尤其是涉及一种具有连接PMOS区域栅极结构的接触插塞的半导体元件。
背景技术
在现有半导体产业中，多晶硅系广泛地应用于半导体元件如金属氧化物半导体(metal-oxide-semiconductor，MOS)晶体管中，作为标准的栅极填充材料选择。然而，随着MOS晶体管尺寸持续地微缩，传统多晶硅栅极因硼穿透(boron penetration)效应导致元件效能降低，及其难以避免的空乏效应(depletion effect)等问题，使得等效的栅极介电层厚度增加、栅极电容值下降，进而导致元件驱动能力的衰退等困境。因此，半导体业界更尝试以新的栅极填充材料，例如利用功函数(work function)金属来取代传统的多晶硅栅极，用以作为匹配高介电常数(High-K)栅极介电层的控制电极。
然而，在现今金属栅极晶体管制作过程中，特别是在制作CMOS晶体管元件时NMOS区域与PMOS区域的功函数金属层由于重叠容易产生所谓金属交界现象(metal boundaryeffect)并影响元件效能。因此如何改良现今制作工艺以解决上述问题即为现今一重要课题。
发明内容
本发明一实施例公开一种半导体元件，其主要包含一基底，该基底包含一NMOS区域以及一PMOS区域，一栅极结构由该NMSO区域至该PMOS区域沿着一第一方向延伸于该基底上以及一第一接触插塞设于该栅极结构上，其中该第一接触插塞由一分隔该NMOS区域及该PMOS区域的交界线偏向该PMOS区域。
依据本发明一实施例，其中该第一接触插塞紧邻该交界线且不重叠该交界线。
依据本发明一实施例，另包含一第一源极/漏极区域沿着一第二方向延伸于该栅极结构两侧的该NMOS区域上。
依据本发明一实施例，另包含一第二接触插塞设于该第一源极/漏极区域上。
依据本发明一实施例，另包含一第二源极/漏极区域沿着一第二方向延伸于该栅极结构两侧的该PMOS区域上。
依据本发明一实施例，另包含一第三接触插塞设于该第二源极/漏极区域上。
依据本发明一实施例，其中该第一接触插塞设于该第二源极/漏极区域之间的一通道区正上方的该栅极结构上。
依据本发明一实施例，其中该第一接触插塞设于该第二源极/漏极区域一侧并远离该交界线的该栅极结构上。
依据本发明一实施例，其中该第一接触插塞设于该第二源极/漏极区域一侧并靠近该交界线的该栅极结构上。
依据本发明一实施例，其中该栅极结构包含一金属栅极。
附图说明
图1为本发明一实施例的半导体元件的上视图；
图2至图3为图1中沿着切线AA’方向制作半导体元件的方法示意图；
图4为本发明一实施例的半导体元件的上视图；
图5为本发明一实施例的半导体元件的上视图；
图6为本发明一实施例的半导体元件的上视图；
图7为本发明一实施例的半导体元件的上视图。
主要元件符号说明
12 基底 14 NMOS区域
16 PMOS区域 18 交界线
20 浅沟隔离 22 栅极结构
24 栅极介电层 26 栅极材料层
28 硬掩模 30 源极/漏极区域
32 源极/漏极区域 34 接触洞蚀刻停止层
36 层间介电层 38 金属栅极
40 栅极介电层 42 高介电常数介电层
44 功函数金属层 46 功函数金属层
48 低阻抗金属层 50 层间介电层
52 接触插塞 54 接触插塞
56 栅极接触插塞 58 通道区
具体实施方式
请参照图1至图3，图1为本发明一实施例的一半导体元件的上视图，图2至3图则为图1中沿着切线AA’方向制作半导体元件的方法示意图。如图1所示，首先提供一基底12，其上定义有至少一晶体管区，例如第一区域以及一第二区域，其中本实施例的第一区域较佳为NMOS区域14而第二区域则较佳为一PMOS区域16，NMOS区域14与PMOS区域16间具有一交界线(boundary)18，且基底12内设有由氧化硅构成的浅沟隔离20将NMOS区域14与PMOS区域16隔开。本实施例虽以平面型晶体管为例，但在其他变化实施例中，本发明的半导体制作工艺也可应用于非平面型晶体管例如鳍状结构晶体管(Fin-FET)，此时，图2所标示的基底12即相对应代表为形成于一基底12上的鳍状结构。
然后于基底12上形成至少一栅极结构22或虚置栅极。在本实施例中，栅极结构22的制作方式可依据制作工艺需求以先栅极(gate first)制作工艺、后栅极(gate last)制作工艺的先高介电常数介电层(high-k first)制作工艺以及后栅极制作工艺的后高介电常数介电层(high-k last)制作工艺等方式制作完成。以本实施例的后高介电常数介电层制作工艺为例，可先依序形成一栅极介电层24或介质层、一由多晶硅所构成的栅极材料层26以及一选择性硬掩模28于基底12上，并利用一图案化光致抗蚀剂(图未示)当作掩模进行一图案转移制作工艺，以单次蚀刻或逐次蚀刻步骤，去除部分硬掩模28、部分栅极材料层26、以及部分栅极介电层24，然后剥除图案化光致抗蚀剂，以于基底12上形成由图案化的栅极介电层24、图案化的栅极材料层26以及图案化的硬掩模28所构成的栅极结构22。从图1来看，栅极结构22较佳沿着一第一方向，例如X方向延伸于基底12上并同时横跨NMOS区域14及PMOS区域16。
在本实施例中，基底12例如是硅基底、外延硅基底、碳化硅基底或硅覆绝缘(silicon-on-insulator,SOI)基底等的半导体基底，但不以此为限。栅极介电层24可包含二氧化硅(SiO2)、氮化硅(SiN)或高介电常数(high dielectric constant,high-k)材料；栅极材料层26可包含金属材料、多晶硅或金属硅化物(silicide)等导电材料；硬掩模28可选自由氧化硅、氮化硅、碳化硅(SiC)以及氮氧化硅(SiON)所构成的群组，但不局限于此。
然后在栅极结构22侧壁形成至少一间隙壁(图未示)，于NMOS区域14及PMOS区域16间隙壁两侧的基底12内分别形成源极/漏极区域30、32及/或外延层，选择性于源极/漏极区域30、32及/或外延层的表面形成一金属硅化物(图未示)，并选择性形成一接触洞蚀刻停止层34于基底12表面与栅极结构22上。从图1来看，NMOS区域14与PMOS区域16内的源极/漏极区域30、32分别沿着一与第一方向垂直的第二方向，例如Y方向延伸于栅极结构22两侧的基底12内。
在本实施例中，间隙壁可为单一间隙壁或复合式间隙壁，且各间隙壁的材料均可选自由氧化硅、氮化硅、氮氧化硅(SiON)以及氮碳化硅(SiCN)所构成的群组。源极/漏极区域30、32可依据所置备晶体管的导电型式而包含不同掺质，例如可包含P型掺质或N型掺质。接触洞蚀刻停止层34则较佳包含氮化硅或氮碳化硅，但均不局限于此。
然后形成一层间介电层36于接触洞蚀刻停止层34上，并进行一平坦化制作工艺，例如利用化学机械研磨去除部分层间介电层36以及部分接触洞蚀刻停止层34，由此暴露出硬掩模28，使硬掩模28上表面与层间介电层36上表面齐平。
随后图2所示，进行一金属栅极置换制作工艺将设于NMOS区域14与PMOS区域16的栅极结构22转换为金属栅极38。举例来说，可先利用图案化掩模为掩模进行一干蚀刻或湿蚀刻制作工艺，例如利用氨水(ammonium hydroxide,NH4OH)或氢氧化四甲铵(Tetramethylammonium Hydroxide,TMAH)等蚀刻溶液来去除硬掩模28、栅极材料层26甚至栅极介电层24，以于层间介电层36中形成凹槽(图未示)横跨NMOS区域14与PMOS区域16。之后依序形成另一选择性介质层或栅极介电层40、一高介电常数介电层42、一选择性阻障层(图未示)以及一功函数金属层44于NMOS区域14与PMOS区域16的凹槽内，形成另一图案化掩模(图未示)例如图案化光致抗蚀剂覆盖NMOS区域14，利用蚀刻去除NMOS区域14的功函数金属层44，去除图案化掩模后再形成另一功函数金属层46于NMOS区域14与PMOS区域16。然后依序形成另一选择性阻障层(图未示)例如上阻障层以及一低阻抗金属层48于凹槽内并填满凹槽，再搭配平坦化制作工艺以形成金属栅极38横跨NMOS区域14及PMOS区域16。
在本实施例中，高介电常数介电层42包含介电常数大于4的介电材料，例如选自氧化铪(hafnium oxide，HfO2)、硅酸铪氧化合物(hafnium silicon oxide,HfSiO4)、硅酸铪氮氧化合物(hafnium silicon oxynitride,HfSiON)、氧化铝(aluminum oxide,Al2O3)、氧化镧(lanthanum oxide,La2O3)、氧化钽(tantalum oxide,Ta2O5)、氧化钇(yttrium oxide,Y2O3)、氧化锆(zirconium oxide,ZrO2)、钛酸锶(strontium titanate oxide,SrTiO3)、硅酸锆氧化合物(zirconium silicon oxide,ZrSiO4)、锆酸铪(hafnium zirconium oxide,HfZrO4)、锶铋钽氧化物(strontium bismuth tantalate,SrBi2Ta2O9,SBT)、锆钛酸铅(leadzirconate titanate,PbZrxTi1-xO3,PZT)、钛酸钡锶(barium strontium titanate,BaxSr1- xTiO3,BST)、或其组合所组成的群组。
在本实施例中，功函数金属层46较佳为N型功函数金属层，其可选用功函数为3.9电子伏特(eV)～4.3eV的金属材料，如铝化钛(TiAl)、铝化锆(ZrAl)、铝化钨(WAl)、铝化钽(TaAl)、铝化铪(HfAl)或TiAlC(碳化钛铝)等，但不以此为限。功函数金属层44则较佳为P型功函数金属层，其可选用功函数为4.8eV～5.2eV的金属材料，如氮化钛(TiN)、氮化钽(TaN)或碳化钽(TaC)等，但不以此为限。低阻抗金属层48则可选自铜(Cu)、铝(Al)、钨(W)、钛铝合金(TiAl)、钴钨磷化物(cobalt tungsten phosphide，CoWP)等低电阻材料或其组合。
之后可形成另一层间介电层50或金属间介电层于金属栅极38上并进行一次或一次以上图案转移制作工艺，例如可利用一图案化掩模去除部分层间介电层36、50以及部分接触洞蚀刻停止层34以形成接触洞(图未示)并暴露出金属栅极38与金属栅极38两侧的源极/漏极区域30、32。然后于各接触洞中填入所需的金属材料，例如包含钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)等的阻障层材料以及选自钨(W)、铜(Cu)、铝(Al)、钛铝合金(TiAl)、钴钨磷化物(cobalt tungsten phosphide，CoWP)等低电阻材料或其组合的低阻抗金属层。之后进行一平坦化制作工艺，例如以化学机械研磨去除部分金属材料以分别形成接触插塞于各接触洞内电连接源极/漏极区域30、32以及栅极结构22。如图3所示，本实施例所制备的接触插塞较佳包含接触插塞52接触或电连接NMOS区域14的源极/漏极区域30，接触插塞54接触或电连接PMOS区域16的源极/漏极区域32以及一接触插塞(或至此简称栅极接触插塞56)接触或电连接由NMOS区域14延伸至PMOS区域16的栅极结构22或金属栅极38。至此即完成本发明优选实施例的半导体元件的制作。
请继续参照图1，图1为本发明一实施例依据图2至图3制作工艺所制备的半导体元件的上视图。如图1所示，相较于现有CMOS元件中连接栅极结构的接触插塞设于NMOS区域14与PMOS区域16之间的交界处或交界线18上，本发明较佳调整栅极接触插塞56所设置的位置，使栅极接触插塞56略为偏向PMOS区域16并设于PMOS区域16内任何一处的栅极结构22上。
举例来说，如图1所示，栅极接触插塞56从上视方向来看可朝PMOS区域16方向略为偏移并直接接触或连接PMOS区域16的栅极结构22，其中栅极接触插塞56在俯视角度下呈现约略矩形且栅极接触插塞56边缘可选择略为偏向PMOS区域16并重叠部分NMOS区域14与PMOS区域16间的交界线18或如图中所示不重叠交界线18，亦即栅极接触插塞56的矩形边缘可紧贴并重叠NMOS区域14与PMOS区域16间的交界线18或仅紧邻但不重叠交界线18。
请参照图4，图4为本发明一实施例依据图2至图3制作工艺所制备的半导体元件的上视图。如图4所示，栅极接触插塞56除了可如前述实施例般设于PMOS区域16内且靠近NMOS区域14与PMOS区域16间的交界线18之外，又可选择朝远离交界线18的方向移动并设置于PMOS区域16通道区58正上方的栅极结构22上。换句话说，本实施例的栅极接触插塞56可设置于源极/漏极区域32之间的一通道区58正上方的栅极结构22上。依据本发明的一实施例，栅极接触插塞56所设置的位置可依据栅极结构22本身临界尺寸或更具体而言宽度0倍至5倍的范围由栅极结构22与通道区58重叠之处朝NMOS区域14方向或远离NMOS区域14的方向移动，其中所谓的0倍范围即本实施例中栅极接触插塞56与通道区58完全重叠的状态。换句话说，本实施例中栅极接触插塞56设于栅极结构22与通道区58重叠之处即所谓栅极结构22本身临界尺寸的0倍距离。
请参照图5，图5为本发明一实施例依据图2至图3制作工艺所制备的半导体元件的上视图。如图5所示，相较于图4的实施例中栅极接触插塞56是以栅极结构22临界尺寸宽度的0倍距离设于栅极结构22与通道区58交界处，本实施例的栅极接触插塞56可由图4的位置以栅极结构22本身一个宽度距离朝NMOS区域14方向移动，或从整体来看栅极接触插塞56是设于源极/漏极区域32一侧并靠近NMOS区域14与PMOS区域16间交界线18的栅极结构22上。
请参照图6，图6为本发明一实施例依据图2至图3制作工艺所制备的半导体元件的上视图。如图6所示，相较于图5的实施例中栅极接触插塞56是由图4的位置以栅极结构22本身一个宽度距离朝NMOS区域14方向移动，本实施例的栅极接触插塞56可由图4的位置同样以栅极结构22本身一个宽度距离朝远离NMOS区域14方向移动，或从整体来看栅极接触插塞56是设于源极/漏极区域32一侧并远离NMOS区域14与PMOS区域16间交界线18的栅极结构22上。
请参照图7，图7为本发明一实施例依据图2至图3制作工艺所制备的半导体元件的上视图。如图7所示，相较于图6的实施例中栅极接触插塞56是由图4的位置以栅极结构22本身一个宽度距离朝远离NMOS区域14方向移动，本实施例的栅极接触插塞56可由图4的位置以栅极结构本身五个宽度距离朝远离NMOS区域14方向移动，此变化型也属本发明所涵盖的范围。
综上所述，本发明主要在制作CMOS晶体管元件时调整栅极接触插塞(即直接接触横跨NMOS区域与PMOS区域的栅极线或栅极结构的接触插塞)所设置的位置，使栅极接触插塞由NMOS区域与PMOS区域间的交界线偏向PMOS区域，由此改善现行制作CMOS晶体管元件时NMOS区域与PMOS区域的功函数金属层因重叠所产生的金属交界现象(metal boundaryeffect)。依据前述实施例，本发明所制备的CMOS晶体管元件仅包含单一一颗栅极接触插塞，或由NMOS区域延伸至PMOS区域的栅极结构仅连接单一一颗栅极接触插塞，且该栅极接触插塞除了连接或接触PMOS区域的栅极结构之外又较佳设于PMOS区域内并远离NMOS区域方向的栅极结构上，例如图6或图7所揭露的栅极接触插塞56所设置的位置。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (10)

1.一种半导体元件，其特征在于，包含：
基底，包含NMOS区域以及PMOS区域；
栅极结构，由该NMSO区域至该PMOS区域沿着第一方向延伸于该基底上；
第一接触插塞，设于该栅极结构上，其中该第一接触插塞由一分隔该NMOS区域及该PMOS区域的交界线偏向该PMOS区域。
2.如权利要求1所述的半导体元件，其中该第一接触插塞紧邻该交界线且不重叠该交界线。
3.如权利要求1所述的半导体元件，另包含第一源极/漏极区域沿着第二方向延伸于该栅极结构两侧的该NMOS区域上。
4.如权利要求3所述的半导体元件，另包含第二接触插塞设于该第一源极/漏极区域上。
5.如权利要求1所述的半导体元件，另包含第二源极/漏极区域沿着第二方向延伸于该栅极结构两侧的该PMOS区域上。
6.如权利要求5所述的半导体元件，另包含第三接触插塞设于该第二源极/漏极区域上。
7.如权利要求5所述的半导体元件，其中该第一接触插塞设于该第二源极/漏极区域之间的一通道区正上方的该栅极结构上。
8.如权利要求5所述的半导体元件，其中该第一接触插塞设于该第二源极/漏极区域一侧并远离该交界线的该栅极结构上。
9.如权利要求5所述的半导体元件，其中该第一接触插塞设于该第二源极/漏极区域一侧并靠近该交界线的该栅极结构上。
10.如权利要求1所述的半导体元件，其中该栅极结构包含金属栅极。
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070210391A1 (en) * 2006-03-09 2007-09-13 Tela Innovations, Inc. Dynamic Array Architecture
US20090152734A1 (en) * 2007-12-13 2009-06-18 Tela Innovations, Inc. Super-Self-Aligned Contacts and Method for Making the Same
US20090315079A1 (en) * 2008-06-23 2009-12-24 Li-Chun Tien Layout Architecture for Improving Circuit Performance
CN103928402A (zh) * 2013-01-11 2014-07-16 中芯国际集成电路制造(上海)有限公司 共用栅极的半导体结构及对应的形成方法
US20170330952A1 (en) * 2016-05-16 2017-11-16 United Microelectronics Corp. Semiconductor device and method of forming the same
US20180108646A1 (en) * 2016-10-17 2018-04-19 Samsung Electronics Co., Ltd. Integrated circuit and semiconductor device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6383904B1 (en) * 2000-10-16 2002-05-07 Advanced Micro Devices, Inc. Fabrication of self-aligned front gate and back gate of a field effect transistor in semiconductor on insulator
JP2007335512A (ja) * 2006-06-13 2007-12-27 Renesas Technology Corp 半導体装置及びその製造方法
KR101718981B1 (ko) * 2010-06-30 2017-03-23 삼성전자주식회사 콘택 플러그를 포함하는 반도체 소자
CN112736079A (zh) * 2019-10-28 2021-04-30 联华电子股份有限公司 具有连接pmos区域栅极结构的接触插塞的半导体元件

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070210391A1 (en) * 2006-03-09 2007-09-13 Tela Innovations, Inc. Dynamic Array Architecture
US20090152734A1 (en) * 2007-12-13 2009-06-18 Tela Innovations, Inc. Super-Self-Aligned Contacts and Method for Making the Same
US20090315079A1 (en) * 2008-06-23 2009-12-24 Li-Chun Tien Layout Architecture for Improving Circuit Performance
CN103928402A (zh) * 2013-01-11 2014-07-16 中芯国际集成电路制造(上海)有限公司 共用栅极的半导体结构及对应的形成方法
US20170330952A1 (en) * 2016-05-16 2017-11-16 United Microelectronics Corp. Semiconductor device and method of forming the same
US20180108646A1 (en) * 2016-10-17 2018-04-19 Samsung Electronics Co., Ltd. Integrated circuit and semiconductor device

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