CN115881538A - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

Info

Publication number
CN115881538A
CN115881538A CN202111134660.5A CN202111134660A CN115881538A CN 115881538 A CN115881538 A CN 115881538A CN 202111134660 A CN202111134660 A CN 202111134660A CN 115881538 A CN115881538 A CN 115881538A
Authority
CN
China
Prior art keywords
layer
metal silicide
forming
metal
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202111134660.5A
Other languages
English (en)
Inventor
邱劲砚
蔡纬撰
易延才
柯贤文
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
United Microelectronics Corp
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to CN202111134660.5A priority Critical patent/CN115881538A/zh
Priority to US17/510,394 priority patent/US20230094638A1/en
Priority to TW111130215A priority patent/TW202335060A/zh
Publication of CN115881538A publication Critical patent/CN115881538A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Abstract

本发明公开一种半导体元件及其制作方法，其中该制作半导体元件的方法为，主要先形成一栅极结构于一基底上，然后形成一源极/漏极区域于该栅极结构两侧，形成一外延层于源极/漏极区域上，形成一层间介电层于栅极结构上，形成一接触洞于层间介电层内并暴露出该外延层，形成一低应力金属层于该接触洞内，形成一阻障层于该低应力金属层上，再进行一退火制作工艺以形成第一硅化金属层与第二硅化金属层。

Description

半导体元件及其制作方法
技术领域
本发明涉及一种制作半导体元件的方法，尤其是涉及一种于栅极结构两侧形成接触洞后形成两层硅化金属层于接触洞内的方法。
背景技术
近年来，随着场效晶体管(field effect transistors,FETs)元件尺寸持续地缩小，现有平面式(planar)场效晶体管元件的发展已面临制作工艺上的极限。为了克服制作工艺限制，以非平面(non-planar)的场效晶体管元件，例如鳍状场效晶体管(fin fieldeffect transistor,Fin FET)元件来取代平面晶体管元件已成为目前的主流发展趋势。由于鳍状场效晶体管元件的立体结构可增加栅极与鳍状结构的接触面积，因此，可进一步增加栅极对于载流子沟道区域的控制，从而降低小尺寸元件面临的漏极引发能带降低(draininduced barrier lowering,DIBL)效应，并可以抑制短沟道效应(short channel effect,SCE)。再者，由于鳍状场效晶体管元件在同样的栅极长度下会具有更宽的沟道宽度，因而可获得加倍的漏极驱动电流。甚而，晶体管元件的临界电压(threshold voltage)也可通过调整栅极的功函数而加以调控。
然而，在现行鳍状场效晶体管元件制作工艺中，特别是接触插塞的制备阶段时常发生接触电阻(contact resistance)过高的问题进而影响整个元件的运作与电性表现。因此如何改良现有鳍状场效晶体管制作工艺以解决此问题即为现今一重要课题。
发明内容
本发明一实施例公开一种制作半导体元件的方法，其主要先形成一栅极结构于一基底上，然后形成一源极/漏极区域于该栅极结构两侧，形成一外延层于源极/漏极区域上，形成一层间介电层于栅极结构上，形成一接触洞于层间介电层内并暴露出该外延层，形成一低应力金属层于该接触洞内，形成一阻障层于该低应力金属层上，再进行一退火制作工艺以形成第一硅化金属层与第二硅化金属层。
本发明另一实施例公开一种半导体元件，其主要包含一栅极结构设于基底上，一源极/漏极区域设于栅极结构两侧以及一接触插塞设于栅极结构旁的源极/漏极区域上，其中接触插塞细部包含一第一硅化金属层设于源极/漏极区域上以及一第二硅化金属层设于该第一硅化金属层上。
附图说明
图1至图6为本发明一实施例制作一半导体元件的方法示意图。
主要元件符号说明
12:基底
14:栅极结构
16:栅极结构
18:栅极介电层
20:栅极材料层
22:硬掩模
24:间隙壁
26:源极/漏极区域
28:外延层
36:接触洞蚀刻停止层
38:层间介电层
40:高介电常数介电层
42:功函数金属层
44:低阻抗金属层
46:硬掩模
48:接触洞
50:低应力金属层
52:阻障层
54:退火制作工艺
56:界面层
58:硅化金属层
60:硅化金属层
62:导电层
64:接触插塞
具体实施方式
请参照图1至图6，图1至图6为本发明一实施例制作一半导体元件的方法示意图。如图1所示，首先提供一基底12，然后于基底12上形成至少一栅极结构14、16。在本实施例中，形成栅极结构14、16的方式较佳依序形成一栅极介电层、一栅极材料层以及一硬掩模于基底12上，并利用一图案化光致抗蚀剂(图未示)当作掩模进行一图案转移制作工艺，以单次蚀刻或逐次蚀刻步骤，去除部分硬掩模、部分栅极材料层以及部分栅极介电层，然后剥除图案化光致抗蚀剂，以于基底12上形成至少一由图案化的栅极介电层18、图案化的栅极材料层20以及图案化的硬掩模22所构成的栅极结构14、16。在本实施例中，栅极结构14、16的数量以两颗为例，但不局限于此，且为了凸显后续于两个栅极结构14、16之间所形成的接触插塞，本实施例仅显示部分栅极结构14、16，例如仅显示栅极结构14的右半部分与栅极结构16的左半部分。
在本实施例中，基底12例如是硅基底、外延硅基底、碳化硅基底或硅覆绝缘(silicon-on-insulator,SOI)基底等的半导体基底，但不以此为限。栅极介电层18可包含二氧化硅(SiO2)、氮化硅(SiN)或高介电常数(high dielectric constant,high-k)材料；栅极材料层20可包含金属材料、多晶硅或金属硅化物(silicide)等导电材料；硬掩模22可选自由氧化硅、氮化硅、碳化硅(SiC)以及氮氧化硅(SiON)所构成的群组，但不局限于此。
此外，在一实施例中，还可选择预先在基底12中形成多个掺杂阱(未绘示)或多个作为电性隔离之用的浅沟槽隔离(shallow trench isolation,STI)。并且，本实施例虽以平面型晶体管为例，但在其他变化实施例中，本发明的半导体制作工艺也可应用于非平面晶体管，例如是鳍状晶体管(Fin-FET)，此时，图1所标示的基底12即相对应代表为形成于一基底12上的鳍状结构。
然后在各栅极结构14、16侧壁形成至少一间隙壁24，于间隙壁24两侧的基底12中形成一源极/漏极区域26及/或外延层28。在本实施例中，间隙壁24可为单一间隙壁或复合式间隙壁，例如可细部包含一偏位间隙壁(图未示)以及一主间隙壁(图未示)。其中本实施例的间隙壁24较佳由氮化硅所构成，但间隙壁24又可选自由氧化硅、氮氧化硅以及氮碳化硅所构成的群组。源极/漏极区域26与外延层28可依据所置备晶体管的导电型式而包含不同掺质或不同材料。例如源极/漏极区域26可包含P型掺质或N型掺质，而外延层28则可包含锗化硅、碳化硅或磷化硅。
接着如图2所示，可选择性形成一由氮化硅所构成的接触洞蚀刻停止层(contactetch stop layer,CESL)36于基底12上并覆盖栅极结构14、16，再形成一层间介电层38于接触洞蚀刻停止层36上。接着进行一平坦化制作工艺，例如利用化学机械研磨(chemicalmechanical polishing,CMP)去除部分层间介电层38与部分接触洞蚀刻停止层36并使硬掩模22上表面与层间介电层38上表面齐平。
随后进行一金属栅极置换制作工艺将栅极结构14、16转换为金属栅极。例如可先进行一选择性的干蚀刻或湿蚀刻制作工艺，例如利用氨水(ammonium hydroxide,NH4OH)或氢氧化四甲铵(Tetramethylammonium Hydroxide,TMAH)等蚀刻溶液来去除栅极结构14、16中的硬掩模22与栅极材料层20，以于层间介电层38中形成凹槽(图未示)。之后依序形成一高介电常数介电层40以及至少包含功函数金属层42与低阻抗金属层44的导电层于凹槽内，并再搭配进行一平坦化制作工艺使U型高介电常数介电层40、U型功函数金属层42与低阻抗金属层44的表面与层间介电层38表面齐平。
在本实施例中，高介电常数介电层40包含介电常数大于4的介电材料，例如选自氧化铪(hafnium oxide,HfO2)、硅酸铪氧化合物(hafnium silicon oxide,HfSiO4)、硅酸铪氮氧化合物(hafnium silicon oxynitride,HfSiON)、氧化铝(aluminum oxide,Al2O3)、氧化镧(lanthanum oxide,La2O3)、氧化钽(tantalum oxide,Ta2O5)、氧化钇(yttrium oxide,Y2O3)、氧化锆(zirconium oxide,ZrO2)、钛酸锶(strontium titanate oxide,SrTiO3)、硅酸锆氧化合物(zirconium silicon oxide,ZrSiO4)、锆酸铪(hafnium zirconium oxide,HfZrO4)、锶铋钽氧化物(strontium bismuth tantalate,SrBi2Ta2O9,SBT)、锆钛酸铅(leadzirconate titanate,PbZrxTi1-xO3,PZT)、钛酸钡锶(barium strontium titanate,BaxSr1- xTiO3,BST)、或其组合所组成的群组。
功函数金属层42较佳用以调整形成金属栅极的功函数，使其适用于N型晶体管(NMOS)或P型晶体管(PMOS)。若晶体管为N型晶体管，功函数金属层42可选用功函数为3.9电子伏特(eV)～4.3eV的金属材料，如铝化钛(TiAl)、铝化锆(ZrAl)、铝化钨(WAl)、铝化钽(TaAl)、铝化铪(HfAl)或TiAlC(碳化钛铝)等，但不以此为限；若晶体管为P型晶体管，功函数金属层42可选用功函数为4.8eV～5.2eV的金属材料，如氮化钛(TiN)、氮化钽(TaN)或碳化钽(TaC)等，但不以此为限。功函数金属层42与低阻抗金属层44之间可包含另一阻障层(图未示)，其中阻障层的材料可包含钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)等材料。低阻抗金属层44则可选自铜(Cu)、铝(Al)、钨(W)、钛铝合金(TiAl)、钴钨磷化物(cobalttungsten phosphide，CoWP)等低电阻材料或其组合。由于依据金属栅极置换制作工艺将虚置栅极转换为金属栅极是此领域者所熟知技术，在此不另加赘述。接着可去除部分高介电常数介电层40、部分功函数金属层42与部分低阻抗金属层44形成凹槽(图未示)，然后再填入一硬掩模46于凹槽内并使硬掩模46与层间介电层38表面齐平，其中硬掩模46可选自由氧化硅、氮化硅、氮氧化硅以及氮碳化硅所构成的群组。
如图3所示，接着可利用图案化掩模进行一蚀刻制作工艺，去除栅极结构14、16旁的部分层间介电层38及部分接触洞蚀刻停止层36以形成接触洞48暴露外延层28表面。然后依序形成一低应力金属层50以及一阻障层52于接触洞48内但不填满接触洞48。
在本实施例中，形成低应力金属层50较佳利用物理气相沉积(physical vapordeposition,PVD)制作工艺而形成阻障层52则较佳利用化学气相沉积(chemical vapordeposition,CVD)制作工艺，其中形成低应力金属层50的物理气相沉积制作工艺的直流功率(DC power)较佳约1000瓦、射频功率(RF power)约4500瓦以及自动电容调节器位置(automatic capacitance tuner position)较佳约75％。一般而言，自动电容调节器位置为一种在静电放电防护电路下用来控制等离子体轰击强度的电容参数，而相较于现有技术中将自动电容调节器位置控制于约10％所产生具有约-712Mpa的高应力金属层，本实施例较佳将自动电容调节器位置调至70％～80％或更佳约75％，如此便可产生具有约介于-330Mpa至-270Mpa或更佳约-299Mpa的低应力金属层。另外在本实施例中，低应力金属层50较佳包含钛，但依据本发明其他实施例也可选自由钛、钴、镍及铂等所构成的群组，阻障层52则可包含氮化钛、氮化钽等金属化合物且最佳包含氮化钛。
如图4所示，然后进行一退火制作工艺54以形成多层硅化金属层。在本实施例中，在连续沉积低应力金属层50与阻障层52之后本阶段所进行的退火制作工艺54可包含依序进行一第一热处理制作工艺与一第二热处理制作工艺以形成多个硅化金属层于外延层28上。在本实施例中，第一热处理制作工艺包含一常温退火(soak anneal)制作工艺，其温度较佳介于500℃至600℃，且最佳为550℃，而其处理时间则较佳介于10秒至60秒，且最佳为30秒。第二热处理制作工艺包含一峰值退火(spike anneal)制作工艺，其温度较佳介于600℃至950℃，且最佳为600℃，而其处理较佳时间则较佳介于100毫秒至5秒，且最佳为5秒。
值得注意的是，本阶段于进行上述退火制作工艺后外延层28较佳与低应力金属层50反应依序于外延层28表面以及未反应的阻障层52之间由下至上形成一界面层56、硅化金属层58以及另一硅化金属层60。其中界面层56较佳包含锗化硅，硅化金属层58包含金属硅锗化物或更具体而言钛硅锗化物(titanium germanosilicide,TiSiGe)，而硅化金属层60则包含金属硅化物或更具体而言钛硅化物(titanium silicide,TiSi)。
如图5所示，之后形成一导电层62于接触洞48内并填满接触洞48。在本实施例中，导电层62较佳包含钨，但不局限于此。最后进行一平坦化制作工艺，例如以CMP制作工艺去除部分导电层62、部分阻障层52及部分低应力金属层50，甚至可视制作工艺需求接着去除部分层间介电层38，以形成接触插塞64电连接外延层28。至此即完成本发明优选实施例一半导体元件的制作。
请继续参照图6，图6揭露本发明一实施例的接触插塞64中各元素包括钛原子、硅原子以及锗原子于材料层中的分布比例图，其中图示中X轴为接触插塞64中各材料层的相对深度距离而Y轴则为各元素于接触插塞64中的浓度。如图6所示，接触插塞64中的锗原子浓度较佳由外延层28至界面层56递减后又于钛硅锗化物所构成的硅化金属层58中略为提升，然后于氮化钛所构成的阻障层52中再次递减。在本实施例中，外延层28的锗浓度较佳介于25～45％或更佳介于48～58％，界面层56的锗浓度较佳介于17～23％，而硅化金属层58的锗浓度则较佳介于24～29％。另外从厚度上来看，界面层56的厚度较佳约10-20埃，硅化金属层58的厚度约50埃，而硅化金属层60的厚度则可小于、等于或大于硅化金属层58的厚度。
需注意的是本实施例中虽于钛硅锗化物(TiSiGe)所构成的硅化金属层58与氮化钛所构成的阻障层52之间另设置一由钛硅化物(TiSi)所构成的硅化金属层60，亦即在界面层56与阻障层52之间设有两层硅化金属层58、60，但不局限于此，依据本发明其他实施例又可于前述沉积低应力金属层50至退火制作工艺54之间略为调整制作工艺中的参数不额外形成钛硅化物(TiSi)所构成硅化金属层，使钛硅锗化物(TiSiGe)所构成的硅化金属层58直接接触上方由氮化钛所构成的阻障层52，此变化型也属本发明所涵盖的范围。为了对应此实施例且更清楚标示界面层56与钛硅锗化物所构成的硅化金属层58之间的锗浓度变化图6中仅绘示硅化金属层58与阻障层52但省略两者之间另一层由钛硅化物所构成的硅化金属层60。
综上所述，本发明主要先形成接触洞于金属栅极两侧后依序形成一低应力金属层以及一阻障层于接触洞内，然后利用一退火制作工艺使低应力金属层与外延层反应形成界面层56、由钛硅锗化物所构成的硅化金属层58以及由钛硅化物所构成的硅化金属层60。依据本发明的优选实施例，通过调整物理气相沉积制作工艺中的部分参数本发明可形成主要由钛金属所构成的低应力金属层，而此具有低应力的金属层又可促使锗原子扩散至由钛硅锗化物所构成的硅化金属层58并降低接触插塞的整体接触电阻(contact resistance)。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (18)

1.一种制作半导体元件的方法，其特征在于，包含：
形成栅极结构于基底上；
形成源极/漏极区域于该栅极结构两侧；
形成层间介电层于该栅极结构上；
形成接触洞于该层间介电层内并暴露出该源极/漏极区域；
形成第一硅化金属层于该接触洞内；以及
形成第二硅化金属层于该第一硅化金属层上。
2.如权利要求1所述的方法，另包含：
形成外延层于该源极/漏极区域上；
形成该接触洞并暴露出该外延层；
形成低应力金属层于该接触洞内；
形成阻障层于该低应力金属层上；以及
进行退火制作工艺以形成该第一硅化金属层及该第二硅化金属层。
3.如权利要求2所述的方法，其中该阻障层包含氮化钛。
4.如权利要求2所述的方法，另包含于该外延层以及该第一硅化金属层之间形成界面层。
5.如权利要求4所述的方法，其中该界面层的锗浓度小于该第一硅化金属层的锗浓度。
6.如权利要求4所述的方法，其中该界面层的锗浓度小于该外延层的锗浓度。
7.如权利要求4所述的方法，其中该界面层包含锗化硅。
8.如权利要求1所述的方法，其中该第一硅化金属层包含金属硅锗化物。
9.如权利要求1所述的方法，其中该第二硅化金属层包含金属硅化物。
10.一种半导体元件，其特征在于，包含：
栅极结构，设于基底上；
源极/漏极区域，设于该栅极结构两侧；
接触插塞，设于该栅极结构旁的该源极/漏极区域上，该接触插塞包含：
第一硅化金属层，设于该源极/漏极区域上；以及
第二硅化金属层，设于该第一硅化金属层上。
11.如权利要求10所述的半导体元件，另包含：
外延层，设于该源极/漏极区域上；
界面层，设于该外延层上；
该第一硅化金属层，设于该界面层上；
该第二硅化金属层，设于该第一硅化金属层上；
阻障层，设于该第二硅化金属层上；以及
导电层，设于该阻障层上。
12.如权利要求11所述的半导体元件，其中该界面层的锗浓度小于该第一硅化金属层的锗浓度。
13.如权利要求11所述的半导体元件，其中该界面层的锗浓度小于该外延层的锗浓度。
14.如权利要求11所述的半导体元件，其中该界面层包含锗化硅。
15.如权利要求11所述的半导体元件，其中该阻障层包含氮化钛。
16.如权利要求11所述的半导体元件，其中该导电层包含钨。
17.如权利要求10所述的半导体元件，其中该第一硅化金属层包含金属硅锗化物。
18.如权利要求10所述的半导体元件，其中该第二硅化金属层包含金属硅化物。
CN202111134660.5A 2021-09-27 2021-09-27 半导体元件及其制作方法 Pending CN115881538A (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN202111134660.5A CN115881538A (zh) 2021-09-27 2021-09-27 半导体元件及其制作方法
US17/510,394 US20230094638A1 (en) 2021-09-27 2021-10-26 Semiconductor device and method for fabricating the same
TW111130215A TW202335060A (zh) 2021-09-27 2022-08-11 半導體元件及其製作方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111134660.5A CN115881538A (zh) 2021-09-27 2021-09-27 半导体元件及其制作方法

Publications (1)

Publication Number Publication Date
CN115881538A true CN115881538A (zh) 2023-03-31

Family

ID=85706465

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111134660.5A Pending CN115881538A (zh) 2021-09-27 2021-09-27 半导体元件及其制作方法

Country Status (3)

Country Link
US (1) US20230094638A1 (zh)
CN (1) CN115881538A (zh)
TW (1) TW202335060A (zh)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10304938B2 (en) * 2016-09-01 2019-05-28 International Business Machines Corporation Maskless method to reduce source-drain contact resistance in CMOS devices
US10304735B2 (en) * 2017-06-22 2019-05-28 Globalfoundries Inc. Mechanically stable cobalt contacts
US10998241B2 (en) * 2018-09-19 2021-05-04 Taiwan Semiconductor Manufacturing Co., Ltd. Selective dual silicide formation using a maskless fabrication process flow
US11107896B2 (en) * 2018-11-29 2021-08-31 Taiwan Semiconductor Manufacturing Company, Ltd. Vertical interconnect features and methods of forming
US11532522B2 (en) * 2021-01-19 2022-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. Source/drain EPI structure for improving contact quality

Also Published As

Publication number Publication date
US20230094638A1 (en) 2023-03-30
TW202335060A (zh) 2023-09-01

Similar Documents

Publication Publication Date Title
CN106803484B (zh) 半导体元件及其制作方法
CN106684041B (zh) 半导体元件及其制作方法
CN107275210B (zh) 半导体元件及其制作方法
CN107808849B (zh) 半导体元件及其制作方法
CN106920839B (zh) 半导体元件及其制作方法
CN107026126B (zh) 半导体元件及其制作方法
US20210296466A1 (en) Semiconductor device and method for fabricating the same
CN115332153A (zh) 半导体元件及其制作方法
US20190140083A1 (en) Bipolar junction transistor and method for fabricating the same
CN112436004A (zh) 半导体元件及其制作方法
TWI814888B (zh) 一種製作半導體元件的方法
TWI690984B (zh) 半導體元件及其製作方法
US7755145B2 (en) Semiconductor device and manufacturing method thereof
CN116153863A (zh) 半导体元件及其制作方法
CN112736079A (zh) 具有连接pmos区域栅极结构的接触插塞的半导体元件
CN109390394B (zh) 穿隧场效晶体管及其制作方法
CN110828377B (zh) 一种具有不对称功函数金属层的半导体元件
CN115565878A (zh) 半导体元件及其制作方法
CN115206802A (zh) 横向扩散金属氧化物半导体元件及其制作方法
CN108022842B (zh) 半导体元件及其制作方法
TWI446456B (zh) 具有金屬閘極之電晶體及其製作方法
CN115881538A (zh) 半导体元件及其制作方法
CN114121660B (zh) 半导体元件及其制作方法
TWI821535B (zh) 一種製作半導體元件的方法
CN109545747B (zh) 半导体元件及其制作方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination