TW202335060A - 半導體元件及其製作方法 - Google Patents

半導體元件及其製作方法 Download PDF

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TW202335060A
TW202335060A TW111130215A TW111130215A TW202335060A TW 202335060 A TW202335060 A TW 202335060A TW 111130215 A TW111130215 A TW 111130215A TW 111130215 A TW111130215 A TW 111130215A TW 202335060 A TW202335060 A TW 202335060A
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layer
metal layer
forming
silicide
siliconized
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邱勁硯
蔡緯撰
易延才
柯賢文
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聯華電子股份有限公司
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Abstract

本發明揭露一種製作半導體元件的方法，其主要先形成一閘極結構於一基底上，然後形成一源極/汲極區域於該閘極結構兩側，形成一磊晶層於源極/汲極區域上，形成一層間介電層於閘極結構上，形成一接觸洞於層間介電層內並暴露出該磊晶層，形成一低應力金屬層於該接觸洞內，形成一阻障層於該低應力金屬層上，再進行一退火製程以形成第一矽化金屬層與第二矽化金屬層。

Description

半導體元件及其製作方法
本發明是關於一種製作半導體元件的方法，尤指一種於閘極結構兩側形成接觸洞後形成兩層矽化金屬層於接觸洞內的方法。
近年來，隨著場效電晶體(field effect transistors, FETs)元件尺寸持續地縮小，習知平面式(planar)場效電晶體元件之發展已面臨製程上之極限。為了克服製程限制，以非平面(non-planar)之場效電晶體元件，例如鰭狀場效電晶體(fin field effect transistor, Fin FET)元件來取代平面電晶體元件已成為目前之主流發展趨勢。由於鰭狀場效電晶體元件的立體結構可增加閘極與鰭狀結構的接觸面積，因此，可進一步增加閘極對於載子通道區域的控制，從而降低小尺寸元件面臨的汲極引發能帶降低(drain induced barrier lowering, DIBL)效應，並可以抑制短通道效應(short channel effect, SCE)。再者，由於鰭狀場效電晶體元件在同樣的閘極長度下會具有更寬的通道寬度，因而可獲得加倍的汲極驅動電流。甚而，電晶體元件的臨界電壓(threshold voltage)亦可藉由調整閘極的功函數而加以調控。
然而，在現行鰭狀場效電晶體元件製程中，特別是接觸插塞的製備階段時常發生接觸電阻(contact resistance)過高的問題進而影響整個元件的運作與電性表現。因此如何改良現有鰭狀場效電晶體製程以解決此問題即為現今一重要課題。
本發明一實施例揭露一種製作半導體元件的方法，其主要先形成一閘極結構於一基底上，然後形成一源極/汲極區域於該閘極結構兩側，形成一磊晶層於源極/汲極區域上，形成一層間介電層於閘極結構上，形成一接觸洞於層間介電層內並暴露出該磊晶層，形成一低應力金屬層於該接觸洞內，形成一阻障層於該低應力金屬層上，再進行一退火製程以形成第一矽化金屬層與第二矽化金屬層。
本發明另一實施例揭露一種半導體元件，其主要包含一閘極結構設於基底上，一源極/汲極區域設於閘極結構兩側以及一接觸插塞設於閘極結構旁之源極/汲極區域上，其中接觸插塞細部包含一第一矽化金屬層設於源極/汲極區域上以及一第二矽化金屬層設於該第一矽化金屬層上。
請參照第1圖至第6圖，第1圖至第6圖為本發明一實施例製作一半導體元件之方法示意圖。如第1圖所示，首先提供一基底12，然後於基底12上形成至少一閘極結構14、16。在本實施例中，形成閘極結構14、16的方式較佳依序形成一閘極介電層、一閘極材料層以及一硬遮罩於基底12上，並利用一圖案化光阻(圖未示)當作遮罩進行一圖案轉移製程，以單次蝕刻或逐次蝕刻步驟，去除部分硬遮罩、部分閘極材料層以及部分閘極介電層，然後剝除圖案化光阻，以於基底12上形成至少一由圖案化之閘極介電層18、圖案化之閘極材料層20以及圖案化之硬遮罩22所構成的閘極結構14、16。在本實施例中，閘極結構14、16的數量以兩顆為例，但不侷限於此，且為了凸顯後續於兩個閘極結構14、16之間所形成的接觸插塞，本實施例僅顯示部分閘極結構14、16，例如僅顯示閘極結構14的右半部份與閘極結構16的左半部份。
在本實施例中，基底12例如是矽基底、磊晶矽基底、碳化矽基底或矽覆絕緣(silicon-on-insulator, SOI)基底等之半導體基底，但不以此為限。閘極介電層18可包含二氧化矽(SiO 2)、氮化矽(SiN)或高介電常數(high dielectric constant, high-k)材料；閘極材料層20可包含金屬材料、多晶矽或金屬矽化物(silicide)等導電材料；硬遮罩22可選自由氧化矽、氮化矽、碳化矽(SiC)以及氮氧化矽(SiON)所構成的群組，但不侷限於此。
此外，在一實施例中，還可選擇預先在基底12中形成複數個摻雜井(未繪示)或複數個作為電性隔離之用的淺溝渠隔離(shallow trench isolation, STI)。並且，本實施例雖以平面型電晶體為例，但在其他變化實施例中，本發明之半導體製程亦可應用於非平面電晶體，例如是鰭狀電晶體(Fin-FET)，此時，第1圖所標示之基底12即相對應代表為形成於一基底12上的鰭狀結構。
然後在各閘極結構14、16側壁形成至少一側壁子24，於側壁子24兩側的基底12中形成一源極/汲極區域26及/或磊晶層28。在本實施例中，側壁子24可為單一側壁子或複合式側壁子，例如可細部包含一偏位側壁子(圖未示)以及一主側壁子(圖未示)。其中本實施例的側壁子24較佳由氮化矽所構成，但側壁子24又可選自由氧化矽、氮氧化矽以及氮碳化矽所構成的群組。源極/汲極區域26與磊晶層28可依據所置備電晶體的導電型式而包含不同摻質或不同材料。例如源極/汲極區域26可包含P型摻質或N型摻質，而磊晶層28則可包含鍺化矽、碳化矽或磷化矽。
接著如第2圖所示，可選擇性形成一由氮化矽所構成的接觸洞蝕刻停止層(contact etch stop layer, CESL)36於基底12上並覆蓋閘極結構14、16，再形成一層間介電層38於接觸洞蝕刻停止層36上。接著進行一平坦化製程，例如利用化學機械研磨(chemical mechanical polishing, CMP)去除部分層間介電層38與部分接觸洞蝕刻停止層36並使硬遮罩22上表面與層間介電層38上表面齊平。
隨後進行一金屬閘極置換製程將閘極結構14、16轉換為金屬閘極。例如可先進行一選擇性之乾蝕刻或濕蝕刻製程，例如利用氨水(ammonium hydroxide, NH 4OH)或氫氧化四甲銨(Tetramethylammonium Hydroxide, TMAH)等蝕刻溶液來去除閘極結構14、16中的硬遮罩22與閘極材料層20，以於層間介電層38中形成凹槽(圖未示)。之後依序形成一高介電常數介電層40以及至少包含功函數金屬層42與低阻抗金屬層44的導電層於凹槽內，並再搭配進行一平坦化製程使U型高介電常數介電層40、U型功函數金屬層42與低阻抗金屬層44的表面與層間介電層38表面齊平。
在本實施例中，高介電常數介電層40包含介電常數大於4的介電材料，例如選自氧化鉿(hafnium oxide, HfO 2)、矽酸鉿氧化合物(hafnium silicon oxide, HfSiO 4)、矽酸鉿氮氧化合物(hafnium silicon oxynitride, HfSiON)、氧化鋁(aluminum oxide, Al 2O 3)、氧化鑭(lanthanum oxide, La 2O 3)、氧化鉭(tantalum oxide, Ta 2O 5)、氧化釔(yttrium oxide, Y 2O 3)、氧化鋯(zirconium oxide, ZrO 2)、鈦酸鍶（strontium titanate oxide, SrTiO 3）、矽酸鋯氧化合物(zirconium silicon oxide, ZrSiO 4)、鋯酸鉿(hafnium zirconium oxide, HfZrO 4)、鍶鉍鉭氧化物(strontium bismuth tantalate, SrBi 2Ta 2O 9, SBT)、鋯鈦酸鉛(lead zirconate titanate,  PbZr xTi 1-xO 3, PZT)、鈦酸鋇鍶(barium strontium titanate, Ba xSr 1-xTiO 3, BST)、或其組合所組成之群組。
功函數金屬層42較佳用以調整形成金屬閘極之功函數，使其適用於N型電晶體(NMOS)或P型電晶體(PMOS)。若電晶體為N型電晶體，功函數金屬層42可選用功函數為3.9電子伏特(eV)～4.3 eV的金屬材料，如鋁化鈦(TiAl)、鋁化鋯(ZrAl)、鋁化鎢(WAl)、鋁化鉭(TaAl)、鋁化鉿(HfAl)或TiAlC (碳化鈦鋁)等，但不以此為限；若電晶體為P型電晶體，功函數金屬層42可選用功函數為4.8 eV～5.2 eV的金屬材料，如氮化鈦(TiN)、氮化鉭(TaN)或碳化鉭(TaC)等，但不以此為限。功函數金屬層42與低阻抗金屬層44之間可包含另一阻障層(圖未示)，其中阻障層的材料可包含鈦(Ti)、氮化鈦(TiN)、鉭(Ta)、氮化鉭(TaN)等材料。低阻抗金屬層44則可選自銅(Cu)、鋁(Al)、鎢(W)、鈦鋁合金(TiAl)、鈷鎢磷化物(cobalt tungsten phosphide，CoWP)等低電阻材料或其組合。由於依據金屬閘極置換製程將虛置閘極轉換為金屬閘極乃此領域者所熟知技藝，在此不另加贅述。接著可去除部分高介電常數介電層40、部分功函數金屬層42與部分低阻抗金屬層44形成凹槽(圖未示)，然後再填入一硬遮罩46於凹槽內並使硬遮罩46與層間介電層38表面齊平，其中硬遮罩46可選自由氧化矽、氮化矽、氮氧化矽以及氮碳化矽所構成的群組。
如第3圖所示，接著可利用圖案化遮罩進行一蝕刻製程，去除閘極結構14、16旁的部分層間介電層38及部分接觸洞蝕刻停止層36以形成接觸洞48暴露磊晶層28表面。然後依序形成一低應力金屬層50以及一阻障層52於接觸洞48內但不填滿接觸洞48。
在本實施例中，形成低應力金屬層50較佳利用物理氣相沉積(physical vapor deposition, PVD)製程而形成阻障層52則較佳利用化學氣相沉積(chemical vapor deposition, CVD)製程，其中形成低應力金屬層50的物理氣相沉積製程的直流功率(DC power)較佳約1000瓦、射頻功率(RF power)約4500瓦以及自動電容調節器位置(automatic capacitance tuner position)較佳約75%。一般而言，自動電容調節器位置係為一種在靜電放電防護電路下用來控制電漿轟擊強度的電容參數，而相較於習知技藝中將自動電容調節器位置控制於約10%所產生具有約-712Mpa的高應力金屬層，本實施例較佳將自動電容調節器位置調至70%-80%或更佳約75%，如此便可產生具有約介於-330Mpa至-270Mpa或更佳約-299Mpa的低應力金屬層。另外在本實施例中，低應力金屬層50較佳包含鈦，但依據本發明其他實施例也可選自由鈦、鈷、鎳及鉑等所構成的群組，阻障層52則可包含氮化鈦、氮化鉭等金屬化合物且最佳包含氮化鈦。
如第4圖所示，然後進行一退火製程54以形成複數層矽化金屬層。在本實施例中，在連續沉積低應力金屬層50與阻障層52之後本階段所進行的退火製程54可包含依序進行一第一熱處理製程與一第二熱處理製程以形成複數個矽化金屬層於磊晶層28上。在本實施例中，第一熱處理製程包含一常溫退火(soak anneal)製程，其溫度較佳介於500℃至600℃，且最佳為550℃，而其處理時間則較佳介於10秒至60秒，且最佳為30秒。第二熱處理製程包含一峰值退火(spike anneal)製程，其溫度較佳介於600℃至950℃，且最佳為600℃，而其處理較佳時間則較佳介於100毫秒至5秒，且最佳為5秒。
值得注意的是，本階段於進行上述退火製程後磊晶層28較佳與低應力金屬層50反應依序於磊晶層28表面以及未反應的阻障層52之間由下至上形成一介面層56、矽化金屬層58以及另一矽化金屬層60。其中介面層56較佳包含鍺化矽，矽化金屬層58包含金屬矽鍺化物或更具體而言鈦矽鍺化物(titanium germanosilicide, TiSiGe)，而矽化金屬層60則包含金屬矽化物或更具體而言鈦矽化物(titanium silicide, TiSi)。
如第5圖所示，之後形成一導電層62於接觸洞48內並填滿接觸洞48。在本實施例中，導電層62較佳包含鎢，但不侷限於此。最後進行一平坦化製程，例如以CMP製程去除部分導電層62、部分阻障層52及部分低應力金屬層50，甚至可視製程需求接著去除部分層間介電層38，以形成接觸插塞64電連接磊晶層28。至此即完成本發明較佳實施例一半導體元件的製作。
請繼續參照第6圖，第6圖揭露本發明一實施例之接觸插塞64中各元素包括鈦原子、矽原子以及鍺原子於材料層中的分佈比例圖，其中圖示中X軸係為接觸插塞64中各材料層的相對深度距離而Y軸則為各元素於接觸插塞64中之濃度。如第6圖所示，接觸插塞64中的鍺原子濃度較佳由磊晶層28至介面層56遞減後又於鈦矽鍺化物所構成的矽化金屬層58中略為提升，然後於氮化鈦所構成的阻障層52中再次遞減。在本實施例中，磊晶層28的鍺濃度較佳介於25-45%或更佳介於48-58%，介面層56的鍺濃度較佳介於17-23%，而矽化金屬層58的鍺濃度則較佳介於24-29%。另外從厚度上來看，介面層56的厚度較佳約10-20埃，矽化金屬層58的厚度約50埃，而矽化金屬層60的厚度則可小於、等於或大於矽化金屬層58的厚度。
需注意的是本實施例中雖於鈦矽鍺化物(TiSiGe)所構成的矽化金屬層58與氮化鈦所構成的阻障層52之間另設置一由鈦矽化物(TiSi)所構成的矽化金屬層60，亦即在介面層56與阻障層52之間設有兩層矽化金屬層58、60，但不侷限於此，依據本發明其他實施例又可於前述沉積低應力金屬層50至退火製程54之間略為調整製程中的參數不額外形成鈦矽化物(TiSi)所構成矽化金屬層，使鈦矽鍺化物(TiSiGe)所構成的矽化金屬層58直接接觸上方由氮化鈦所構成的阻障層52，此變化型也屬本發明所涵蓋的範圍。為了對應此實施例且更清楚標示介面層56與鈦矽鍺化物所構成的矽化金屬層58之間的鍺濃度變化第6圖中僅繪示矽化金屬層58與阻障層52但省略兩者之間另一層由鈦矽化物所構成的矽化金屬層60。
綜上所述，本發明主要先形成接觸洞於金屬閘極兩側後依序形成一低應力金屬層以及一阻障層於接觸洞內，然後利用一退火製程使低應力金屬層與磊晶層反應形成介面層56、由鈦矽鍺化物所構成的矽化金屬層58以及由鈦矽化物所構成的矽化金屬層60。依據本發明之較佳實施例，藉由調整物理氣相沉積製程中的部分參數本發明可形成主要由鈦金屬所構成的低應力金屬層，而此具有低應力的金屬層又可促使鍺原子擴散至由鈦矽鍺化物所構成的矽化金屬層58並降低接觸插塞的整體接觸電阻(contact resistance)。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
12:基底 14:閘極結構 16:閘極結構 18:閘極介電層 20:閘極材料層 22:硬遮罩 24:側壁子 26:源極/汲極區域 28:磊晶層 36:接觸洞蝕刻停止層 38:層間介電層 40:高介電常數介電層 42:功函數金屬層 44:低阻抗金屬層 46:硬遮罩 48:接觸洞 50:低應力金屬層 52:阻障層 54:退火製程 56:介面層 58:矽化金屬層 60:矽化金屬層 62:導電層 64:接觸插塞
第1圖至第6圖為本發明一實施例製作一半導體元件之方法示意圖。
12:基底
14:閘極結構
16:閘極結構
18:閘極介電層
24:側壁子
26:源極/汲極區域
28:磊晶層
36:接觸洞蝕刻停止層
38:層間介電層
40:高介電常數介電層
42:功函數金屬層
44:低阻抗金屬層
46:硬遮罩
50:低應力金屬層
52:阻障層
56:介面層
58:矽化金屬層
60:矽化金屬層
62:導電層
64:接觸插塞

Claims (18)

  1. 一種製作半導體元件的方法，其特徵在於，包含： 形成一閘極結構於一基底上； 形成一源極/汲極區域於該閘極結構兩側； 形成一層間介電層於該閘極結構上； 形成一接觸洞於該層間介電層內並暴露出該源極/汲極區域； 形成一第一矽化金屬層於該接觸洞內；以及 形成一第二矽化金屬層於該第一矽化金屬層上。
  2. 如申請專利範圍第1項所述之方法，另包含： 形成一磊晶層於該源極/汲極區域上； 形成該接觸洞並暴露出該磊晶層； 形成一低應力金屬層於該接觸洞內； 形成一阻障層於該低應力金屬層上；以及 進行一退火製程以形成該第一矽化金屬層及該第二矽化金屬層。
  3. 如申請專利範圍第2項所述之方法，其中該阻障層包含氮化鈦。
  4. 如申請專利範圍第2項所述之方法，另包含於該磊晶層以及該第一矽化金屬層之間形成一介面層。
  5. 如申請專利範圍第4項所述之方法，其中該介面層之鍺濃度小於該第一矽化金屬層之鍺濃度。
  6. 如申請專利範圍第4項所述之方法，其中該介面層之鍺濃度小於該磊晶層之鍺濃度。
  7. 如申請專利範圍第4項所述之方法，其中該介面層包含鍺化矽。
  8. 如申請專利範圍第1項所述之方法，其中該第一矽化金屬層包含金屬矽鍺化物。
  9. 如申請專利範圍第1項所述之方法，其中該第二矽化金屬層包含金屬矽化物。
  10. 一種半導體元件，其特徵在於，包含： 一閘極結構設於一基底上； 一源極/汲極區域設於該閘極結構兩側； 一接觸插塞設於該閘極結構旁之該源極/汲極區域上，該接觸插塞包含： 一第一矽化金屬層設於該源極/汲極區域上；以及 一第二矽化金屬層設於該第一矽化金屬層上。
  11. 如申請專利範圍第10項所述之半導體元件，另包含： 一磊晶層設於該源極/汲極區域上； 一介面層設於該磊晶層上； 該第一矽化金屬層設於該介面層上； 該第二矽化金屬層設於該第一矽化金屬層上； 一阻障層設於該第二矽化金屬層上；以及 一導電層設於該阻障層上。
  12. 如申請專利範圍第11項所述之半導體元件，其中該介面層之鍺濃度小於該第一矽化金屬層之鍺濃度。
  13. 如申請專利範圍第11項所述之半導體元件，其中該介面層之鍺濃度小於該磊晶層之鍺濃度。
  14. 如申請專利範圍第11項所述之半導體元件，其中該介面層包含鍺化矽。
  15. 如申請專利範圍第11項所述之半導體元件，其中該阻障層包含氮化鈦。
  16. 如申請專利範圍第11項所述之半導體元件，其中該導電層包含鎢。
  17. 如申請專利範圍第10項所述之半導體元件，其中該第一矽化金屬層包含金屬矽鍺化物。
  18. 如申請專利範圍第10項所述之半導體元件，其中該第二矽化金屬層包含金屬矽化物。
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