TWI821535B - 一種製作半導體元件的方法 - Google Patents

一種製作半導體元件的方法 Download PDF

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TWI821535B
TWI821535B TW109106796A TW109106796A TWI821535B TW I821535 B TWI821535 B TW I821535B TW 109106796 A TW109106796 A TW 109106796A TW 109106796 A TW109106796 A TW 109106796A TW I821535 B TWI821535 B TW I821535B
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metal
layer
gate
barrier layer
dielectric layer
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TW202135168A (zh
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唐俊榮
劉又仁
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聯華電子股份有限公司
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Abstract

本發明揭露一種製作半導體元件的方法。首先形成一閘極結構於一基底上，然後形成一層間介電層環繞閘極結構，進行一金屬閘極置換製程將該閘極結構轉換為一金屬閘極，形成一金屬間介電層於該金屬閘極上，形成一金屬內連線於該金屬間介電層內，再進行一高壓退火製程以改善金屬閘極之功函數變異。

Description

一種製作半導體元件的方法
本發明是關於一種製作半導體元件的方法，尤指一種於金屬內連線製程後以高壓退火製程改善金屬閘極電晶體功函數變異的方法。
在習知半導體產業中，多晶矽係廣泛地應用於半導體元件如金氧半導體(metal-oxide-semiconductor，MOS)電晶體中，作為標準的閘極填充材料選擇。然而，隨著MOS電晶體尺寸持續地微縮，傳統多晶矽閘極因硼穿透(boron penetration)效應導致元件效能降低，及其難以避免的空乏效應(depletion effect)等問題，使得等效的閘極介電層厚度增加、閘極電容值下降，進而導致元件驅動能力的衰退等困境。因此，半導體業界更嘗試以新的閘極填充材料，例如利用功函數(work function)金屬來取代傳統的多晶矽閘極，用以作為匹配高介電常數(High-K)閘極介電層的控制電極。
然而，在現今金屬閘極電晶體製作過程中，即使兩顆電晶體元件例如NMOS以及/或PMOS元件是設置於相鄰區域內仍容易出現元件不匹配(device mismatch)的情形進而影響元件效能。因此如何改良現今製程以解決上述問題即為現今一重要課題。
本發明一實施例揭露一種製作半導體元件的方法。首先形成一閘極結構於一基底上，然後形成一層間介電層環繞閘極結構，進行一金屬閘極置換製程將該閘極結構轉換為一金屬閘極，形成一金屬間介電層於該金屬閘極上，形成一金屬內連線於該金屬間介電層內，再進行一高壓退火製程以改善金屬閘極之功函數變異。
依據本發明一實施例，該金屬閘極置換製程包含先去除該閘極結構以形成一凹槽，形成一高介電常數介電層於凹槽內，形成一功函數金屬層於高介電常數介電層上，形成一阻障層於功函數金屬層上，再形成一低阻抗金屬層於該阻障層上。
依據本發明一實施例，阻障層包含一第一阻障層設於該功函數金屬層上以及一第二阻障層設於第一阻障層上。
依據本發明一實施例，第一阻障層包含氮化鈦。
依據本發明一實施例，第一阻障層厚度小於20埃。
依據本發明一實施例，第二阻障層包含鈦。
依據本發明一實施例，高壓退火製程包含氫氣。
依據本發明一實施例，高壓退火製程溫度係介於攝氏360度至攝氏440度。
依據本發明一實施例，高壓退火製程時間係介於一分鐘至60分鐘。
依據本發明一實施例，高壓退火製程壓力係介於5- 100標準大氣壓。
請參照第1圖至第5圖，第1圖至第5圖為本發明一實施例製作半導體元件之方法示意圖。如第1圖所示，首先提供一基底12，例如一矽基底或矽覆絕緣(SOI)基板，其上可定義有一電晶體區，例如一PMOS電晶體區或一NMOS電晶體區。基底12上具有至少一鰭狀結構14及一絕緣層(圖未示)，其中鰭狀結構14之底部係被絕緣層，例如氧化矽所包覆而形成淺溝隔離。需注意的是，本實施例雖以製作非平面型場效電晶體(non-planar)例如鰭狀結構場效電晶體為例，但不侷限於此，本發明又可應用至一般平面型(planar)場效電晶體，此實施例也屬本發明所涵蓋的範圍。
依據本發明一實施例，鰭狀結構14較佳透過側壁圖案轉移(sidewall image transfer, SIT)技術製得，其程序大致包括：提供一佈局圖案至電腦系統，並經過適當地運算以將相對應之圖案定義於光罩中。後續可透過光微影及蝕刻製程，以形成多個等距且等寬之圖案化犧牲層於基底上，使其個別外觀呈現條狀。之後依序施行沉積及蝕刻製程，以於圖案化犧牲層之各側壁形成側壁子。繼以去除圖案化犧牲層，並在側壁子的覆蓋下施行蝕刻製程，使得側壁子所構成之圖案被轉移至基底內，再伴隨鰭狀結構切割製程(fin cut)而獲得所需的圖案化結構，例如條狀圖案化鰭狀結構。
除此之外，鰭狀結構14之形成方式又可包含先形成一圖案化遮罩(圖未示)於基底12上，再經過一蝕刻製程，將圖案化遮罩之圖案轉移至基底12中以形成鰭狀結構。另外，鰭狀結構之形成方式也可以先形成一圖案化硬遮罩層(圖未示)於基底12上，並利用磊晶製程於暴露出於圖案化硬遮罩層之基底12上成長出例如包含矽鍺的半導體層，而此半導體層即可作為相對應的鰭狀結構。這些形成鰭狀結構的實施例均屬本發明所涵蓋的範圍。
接著可於基底12上形成至少一閘極結構16或虛置閘極。在本實施例中，閘極結構16之製作方式可依據製程需求以先閘極(gate first)製程、後閘極(gate last)製程之先高介電常數介電層(high-k first)製程以及後閘極製程之後高介電常數介電層(high-k last)製程等方式製作完成。以本實施例之後高介電常數介電層製程為例，可先依序形成一閘極介電層或介質層、一由多晶矽所構成之閘極材料層以及一選擇性硬遮罩於基底12上，並利用一圖案化光阻(圖未示)當作遮罩進行一圖案轉移製程，以單次蝕刻或逐次蝕刻步驟，去除部分閘極材料層與部分閘極介電層，然後剝除圖案化光阻，以於基底12上形成由圖案化之閘極介電層18與圖案化之閘極材料層20所構成的閘極結構16。
然後在閘極結構16側壁形成至少一側壁子22，接著於側壁子22兩側的鰭狀結構14以及/或基底12中形成一源極/汲極區域24及/或磊晶層(圖未示)，並選擇性於源極/汲極區域24及/或磊晶層的表面形成一金屬矽化物(圖未示)。在本實施例中，側壁子22可為單一側壁子或複合式側壁子，例如可細部包含一偏位側壁子26以及一主側壁子28。其中偏位側壁子26與主側壁子28可包含相同或不同材料，且兩者均可選自由氧化矽、氮化矽、氮氧化矽以及氮碳化矽所構成的群組。源極/汲極區域24可依據所置備電晶體的導電型式而包含不同摻質，例如可包含P型摻質或N型摻質。
接著如第2圖所示，先形成一接觸洞蝕刻停止層30於基底12表面與閘極結構16上，再形成一層間介電層32於接觸洞蝕刻停止層30上。然後進行一平坦化製程，例如利用化學機械研磨(chemical mechanical polishing, CMP)去除部分層間介電層32與部分接觸洞蝕刻停止層30並暴露出由多晶矽材料所構成的閘極材料層20，使各閘極材料層20上表面與層間介電層32上表面齊平。
如第3圖所示，隨後進行一金屬閘極置換製程將閘極結構16轉換為金屬閘極。舉例來說，可先進行一選擇性之乾蝕刻或濕蝕刻製程，例如利用氨水(ammonium hydroxide, NH4 OH)或氫氧化四甲銨(Tetramethylammonium Hydroxide, TMAH)等蝕刻溶液來去除閘極結構16中的閘極材料層20甚至閘極介電層18，以於層間介電層32中形成凹槽(圖未示)。之後依序形成一選擇性介質層34或閘極介電層、一高介電常數介電層36、一功函數金屬層38、一阻障層44以及一低阻抗金屬層40於凹槽內，然後進行一平坦化製程，例如利用CMP去除部分低阻抗金屬層40、部分阻障層44、部分功函數金屬層38以及部分高介電常數介電層36以形成金屬閘極42。以本實施例利用後高介電常數介電層製程所製作的金屬閘極為例，閘極結構16或金屬閘極42較佳包含一介質層34或閘極介電層、一U型高介電常數介電層36、一U型功函數金屬層38以及一低阻抗金屬層40。
在本實施例中，高介電常數介電層36包含介電常數大於4的介電材料，例如選自氧化鉿(hafnium oxide，HfO2 )、矽酸鉿氧化合物(hafnium silicon oxide, HfSiO4 )、矽酸鉿氮氧化合物(hafnium silicon oxynitride, HfSiON)、氧化鋁(aluminum oxide, Al2 O3 )、氧化鑭(lanthanum oxide, La2 O3 )、氧化鉭(tantalum oxide, Ta2 O5 )、氧化釔(yttrium oxide, Y2 O3 )、氧化鋯(zirconium oxide, ZrO2 )、鈦酸鍶(strontium titanate oxide, SrTiO3 )、矽酸鋯氧化合物(zirconium silicon oxide, ZrSiO4 )、鋯酸鉿(hafnium zirconium oxide, HfZrO4 )、鍶鉍鉭氧化物(strontium bismuth tantalate, SrBi2 Ta2 O9 , SBT)、鋯鈦酸鉛(lead zirconate titanate, PbZrx Ti1-x O3 , PZT)、鈦酸鋇鍶(barium strontium titanate, Bax Sr1-x TiO3 , BST)、或其組合所組成之群組。
功函數金屬層38較佳用以調整形成金屬閘極之功函數，使其適用於N型電晶體(NMOS)或P型電晶體(PMOS)。若電晶體為N型電晶體，功函數金屬層38可選用功函數為3.9電子伏特(eV)～4.3 eV的金屬材料，如鋁化鈦(TiAl)、鋁化鋯(ZrAl)、鋁化鎢(WAl)、鋁化鉭(TaAl)、鋁化鉿(HfAl)或TiAlC (碳化鈦鋁)等，但不以此為限；若電晶體為P型電晶體，功函數金屬層38可選用功函數為4.8 eV～5.2 eV的金屬材料，如氮化鈦(TiN)、氮化鉭(TaN)或碳化鉭(TaC)等，但不以此為限。阻障層44的可包含但不侷限於鈦(Ti)、氮化鈦(TiN)、鉭(Ta)、氮化鉭(TaN)等材料。低阻抗金屬層40則可選自銅(Cu)、鋁(Al)、鎢(W)、鈦鋁合金(TiAl)、鈷鎢磷化物(cobalt tungsten phosphide，CoWP)等低電阻材料或其組合。
在本實施例中，阻障層44較佳細部包含一第一阻障層46以及一第二阻障層48，其中第一阻障層46較佳包含氮化鈦，第二阻障層48則較佳包含鈦。另外第一阻障層46厚度較佳小於第二阻障層48厚度，例如第一阻障層46厚度較佳小於20埃而第二阻障層48厚度則較佳介於80埃至100埃或更佳約90埃。
如第4圖所示，之後可進行一圖案轉移製程，例如可利用一圖案化遮罩去除金屬閘極42旁的部分層間介電層32以及部分接觸洞蝕刻停止層30以形成複數個接觸洞(圖未示)並暴露出下面的源極/汲極區域24。然後再於各接觸洞中填入所需的金屬材料，例如包含鈦(Ti)、氮化鈦(TiN)、鉭(Ta)、氮化鉭(TaN)等的阻障層材料以及選自鎢(W)、銅(Cu)、鋁(Al)、鈦鋁合金(TiAl)、鈷鎢磷化物(cobalt tungsten phosphide，CoWP)等低電阻材料或其組合的低阻抗金屬層。之後進行一平坦化製程，例如以化學機械研磨去除部分金屬材料以分別形成接觸插塞50於各接觸洞內電連接源極/汲極區域24。
隨後進行一金屬內連線製程，例如可依序形成一停止層52以及一金屬間介電層54於層間介電層32表面，進行一道或一道以上微影暨蝕刻製程去除部分金屬間介電層54及部分停止層52形成接觸洞(圖未示)。接著填入導電材料於各接觸洞內並搭配平坦化製程如CMP以形成金屬內連線56連接下方的接觸插塞50。隨後可重複進行上述製程並依據製程需求形成多組由金屬間介電層與金屬內連線所構成金屬內連線結構於層間介電層上以完成後段(beck-end-of-the-line, BEOL)製程。
在本實施例中，停止層52可選自由氮摻雜碳化物層(nitrogen doped carbide, NDC)、氮化矽、以及氮碳化矽(silicon carbon nitride, SiCN)所構成的群組而各金屬內連線56均可依據單鑲嵌製程或雙鑲嵌製程鑲嵌於金屬間介電層內。例如各金屬內連線56可更細部包含一阻障層以及一金屬層，其中阻障層可選自由鈦(Ti)、氮化鈦(TiN)、鉭(Ta)以及氮化鉭(TaN)所構成的群組，而金屬層可選自由鎢(W)、銅(Cu)、鋁(Al)、鈦鋁合金(TiAl)、鈷鎢磷化物(cobalt tungsten phosphide，CoWP)等所構成的群組，但不侷限於此。由於單鑲嵌或雙鑲嵌製程乃本領域所熟知技藝，在此不另加贅述。
如第5圖所示，隨後於後段製程後進行一高壓退火製程58以改善金屬閘極42之功函數變異(work function variation)。在本實施例中，高壓退火製程較佳包含氫氣，高壓退火製程溫度較佳介於攝氏360度至攝氏440度或更佳約攝氏400度，高壓退火製程時間較佳介於一分鐘至60分鐘或更佳約30分鐘，且高壓退火製程壓力較佳介於5-100標準大氣壓或更佳約20標準大氣壓。
一般而言，依據現行金屬閘極電晶體的製程中所製備出的電晶體元件上即使兩顆電晶體元件例如NMOS以及/或PMOS元件是設置於相鄰區域內仍容易出現元件不匹配(device mismatch)的情形，即所謂兩個相鄰元件間發生臨界電壓(Vt)以及開啟電流(Ion )或飽和電流(saturation current)不一致的狀況。考量此現象可能受制於金屬閘極中功函數金屬層在堆疊時因厚度或其他原因所產生的變異(variation)，本發明一實施例可選擇將金屬閘極中位於功函數金屬層與低阻抗金屬層之間阻障層的厚度，特別是前述第一阻障層46的厚度控制至20埃以下甚至接近0埃來藉此降低功函數金屬層發生變異的機率。
除此之外本發明另一手段可選擇於後段製程或金屬內連線製程後進行一高壓退火製程，在僅通入氫氣但不通入其他反應氣體例如氮氣等的條件下調整高壓退火製程的製程參數，例如控制高壓退火製程的溫度介於攝氏360度至攝氏440度或更佳約攝氏400度、時間介於一分鐘至60分鐘或更佳約30分鐘以及/或壓力介於5-100標準大氣壓或更佳約20標準大氣壓。藉由調整高壓退火製程的參數並選擇性搭配控制阻障層的厚度本發明可有效改善金屬閘極電晶體元件發生元件不匹配的現象。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
12:基底 14:鰭狀結構 16:閘極結構 18:閘極介電層 20:閘極材料層 22:側壁子 24:源極/汲極區域 26:偏位側壁子 28:主側壁子 30:接觸洞蝕刻停止層 32:層間介電層 34:介質層 36:高介電常數介電層 38:功函數金屬層 40:低阻抗金屬層 42:金屬閘極 44:阻障層 46:第一阻障層 48:第二阻障層 50:接觸插塞 52:停止層 54:金屬間介電層 56:金屬內連線 58:高壓退火製程
第1圖至第5圖為本發明一實施例製作半導體元件之方法示意圖。
12:基底
14:鰭狀結構
16:閘極結構
22:側壁子
24:源極/汲極區域
26:偏位側壁子
28:主側壁子
30:接觸洞蝕刻停止層
32:層間介電層
34:介質層
36:高介電常數介電層
38:功函數金屬層
40:低阻抗金屬層
42:金屬閘極
44:阻障層
46:第一阻障層
48:第二阻障層
50:接觸插塞
52:停止層
54:金屬間介電層
56:金屬內連線
58:高壓退火製程

Claims (10)

  1. 一種製作半導體元件的方法，其特徵在於，包含： 形成一閘極結構於一基底上； 形成一層間介電層環繞該閘極結構； 進行一金屬閘極置換製程將該閘極結構轉換為一金屬閘極； 形成一金屬間介電層於該金屬閘極上； 形成一金屬內連線於該金屬間介電層內；以及 進行一高壓退火製程以改善該金屬閘極之功函數變異。
  2. 如申請專利範圍第1項所述之方法，其中該金屬閘極置換製程包含： 去除該閘極結構以形成一凹槽； 形成一高介電常數介電層於該凹槽內； 形成一功函數金屬層於該高介電常數介電層上； 形成一阻障層於該功函數金屬層上；以及 形成一低阻抗金屬層於該阻障層上。
  3. 如申請專利範圍第2項所述之方法，其中該阻障層包含： 一第一阻障層設於該功函數金屬層上；以及 一第二阻障層設於該第一阻障層上。
  4. 如申請專利範圍第3項所述之方法，其中該第一阻障層包含氮化鈦。
  5. 如申請專利範圍第3項所述之方法，其中該第一阻障層厚度小於20埃。
  6. 如申請專利範圍第3項所述之方法，其中該第二阻障層包含鈦。
  7. 如申請專利範圍第1項所述之方法，其中該高壓退火製程包含氫氣。
  8. 如申請專利範圍第1項所述之方法，其中該高壓退火製程溫度係介於攝氏360度至攝氏440度。
  9. 如申請專利範圍第1項所述之方法，其中該高壓退火製程時間係介於一分鐘至60分鐘。
  10. 如申請專利範圍第1項所述之方法，其中該高壓退火製程壓力係介於5-100標準大氣壓。
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