CN106920839B - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

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CN106920839B
CN106920839B CN201510995716.4A CN201510995716A CN106920839B CN 106920839 B CN106920839 B CN 106920839B CN 201510995716 A CN201510995716 A CN 201510995716A CN 106920839 B CN106920839 B CN 106920839B
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hard mask
layer
region
gate structure
forming
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CN106920839A (zh
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游峻伟
丁煦
刘厥扬
王俞仁
陈广修
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to US15/469,569 priority patent/US10505041B2/en
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Abstract

本发明公开半导体元件及其制作方法。该制作半导体元件的方法为，首先提供一基底，然后形成一第一栅极结构于基底上以及一第一间隙壁于第一栅极结构旁，形成一第一外延层于第一栅极结构旁的基底内，形成一第一硬掩模层于第一栅极结构上，去除部分第一硬掩模层并形成一保护层于第一外延层上以及去除剩余的第一硬掩模层。

Description

半导体元件及其制作方法
技术领域
本发明涉及一种制作半导体元件的方法，尤其是涉及一种去除栅极结构上的硬掩模层并同时于基底表面形成一保护层的方法。
背景技术
为了能增加半导体结构的载流子迁移率，可以选择对于栅极通道施加压缩应力或是伸张应力。举例来说，若需要施加的是压缩应力，现有技术常利用选择性外延成长(selective epitaxial growth,SEG)技术于一硅基底内形成晶格排列与该硅基底相同的外延结构，例如硅锗(silicon germanium,SiGe)外延结构。利用硅锗外延结构的晶格常数(lattice constant)大于该硅基底晶格的特点，对P型金属氧化物半导体晶体管的通道区产生应力，增加通道区的载流子迁移率(carrier mobility)，并用于增加金属氧化物半导体晶体管的速度。反之，若是N型半导体晶体管则可选择于硅基底内形成硅碳(siliconcarbide,SiC)外延结构，对栅极通道区产生伸张应力。
现今以外延成长方式形成外延层的晶体管过程中通常会先以蚀刻拔除栅极结构上的硬掩模再进行后续接触插塞制作工艺。然而在去除硬掩模的过程中所使用的蚀刻溶液容易损害外延层的表面并影响元件运作。因此，如何改良现有制作工艺技术以解决现有瓶颈即为现今一重要课题。
发明内容
本发明公开一种制作半导体元件的方法。首先提供一基底，然后形成一第一栅极结构于基底上以及一第一间隙壁于第一栅极结构旁，形成一第一外延层于第一栅极结构旁的基底内，形成一第一硬掩模层于第一栅极结构上，去除部分第一硬掩模层并形成一保护层于第一外延层上以及去除剩余的第一硬掩模层。
本发明另一实施例公开一种半导体元件，其包含：一基底，一栅极结构设于基底上以及一外延层设于栅极结构旁的基底内，其中外延层优选包含一平坦表面以及突起部设于平坦表面两侧。
附图说明
图1至图10为本发明优选实施例制作一半导体元件的制作工艺示意图。
主要元件符号说明
12 基底 14 第一区域
16 第二区域 18 栅极结构
20 栅极结构 22 栅极介电层
24 栅极材料层 26 硬掩模
28 硬掩模 30 浅沟隔离
32 硬掩模 34 硬掩模
36 硬掩模层 38 间隙壁
40 凹槽 42 外延层
44 硬掩模层 46 间隙壁
48 凹槽 50 外延层
52 保护层 54 平坦表面
56 突起部 58 接触洞蚀刻停止层
60 层间介电层 62 高介电常数介电层
64 功函数金属层 66 低阻抗金属层
68 硬掩模 72 接触插塞
74 第一金属层 76 第二金属层
78 金属硅化物 80 第三金属层
具体实施方式
请参照图1至图10，图1至图10则为本发明优选实施例制作一半导体元件的制作工艺示意图。如图1所示，首先提供一基底12，基底上定义有一第一区域14与第二区域16，其中第一区域14优选为一NMOS区域，第二区域16优选为一PMOS区域。
然后分别于第一区域14上形成栅极结构18以及于第二区域16上形成栅极结构20。在本实施例中，形成栅极结构18、20的方式优选依序形成一栅极介电层22、一栅极材料层、一第一硬掩模以及一第二硬掩模于基底12上，并利用一图案化光致抗蚀剂(图未示)当作掩模进行一图案转移制作工艺，以单次蚀刻或逐次蚀刻步骤，去除部分第二硬掩模、部分第一硬掩模与部分栅极材料层，然后剥除图案化光致抗蚀剂，以于第一区域14与第二区域16上分别形成多个由图案化的栅极材料层24、图案化的硬掩模26以及图案化的硬掩模28所构成的栅极结构18、20。在本实施例中，第一区域14与第二区域16中的栅极结构18、20的数量以四颗为例，但不局限于此，又可依据制作工艺需求任意调整。
在本实施例中，基底12例如是硅基底、外延硅基底、碳化硅基底或硅覆绝缘(silicon-on-insulator,SOI)基底等的半导体基底，但不以此为限。栅极介电层22可包含二氧化硅(SiO2)、氮化硅(SiN)或高介电常数(high dielectric constant,high-k)材料；栅极材料层24可包含金属材料、多晶硅或金属硅化物(silicide)等导电材料；硬掩模26优选包含氮化硅；硬掩模28则优选包含氧化硅。需注意的是，本实施例虽将氧化硅所构成的硬掩模28设于氮化硅所构成的硬掩模26上，但硬掩模28与硬掩模26的材料配置并不局限于此。例如硬掩模26与硬掩模28可选自由二氧化硅、氮化硅、碳化硅(SiC)以及氮氧化硅(SiON)所构成的群组且两者优选包含不同材料，此实施例也属本发明所涵盖的范围。
此外，基底12中可设有多个作为电性隔离之用的浅沟隔离(shallow trenchisolation,STI)30，且本实施例虽以平面型晶体管为例，但在其他变化实施例中，本发明的半导体制作工艺也可应用于非平面晶体管，例如是鳍状结构晶体管(Fin-FET)，此时，图1所标示的基底12即相对应代表为形成于一基底12上的鳍状结构。
接着依序形成一硬掩模32、一硬掩模34以及一硬掩模层36于基底12上并覆盖第一区域14与第二区域16的栅极结构18、20，其中硬掩模32优选包含碳氮氧化硅(SiOCN)，硬掩模34优选包含更厚的SiOCN，硬掩模层36优选包含氮化硅。在本实施例中，硬掩模34的厚度优选介于硬掩模32厚度的两倍至三倍之间，但不局限于此。
如图2所示，然后形成一图案化掩模，例如一图案化光致抗蚀剂(图未示)于第二区域16，并利用图案化光致抗蚀剂为掩模进行一蚀刻制作工艺，去除第一区域14上的部分硬掩模层36、部分硬掩模34与部分硬掩模32，以形成间隙壁38以及凹槽40于栅极结构18旁的基底12内。之后再拔除图案化光致抗蚀剂。值得注意的是，第一区域14的硬掩模32与硬掩模34优选在蚀刻过程中被部分去除形成间隙壁38，大部分的硬掩模层36则于形成凹槽40的过程中被去除，而仅留部分硬掩模层36于间隙壁38的侧壁。
接着如图3所示，先选择性进行一清洗制作工艺完全去除残留于间隙壁38侧壁的硬掩模层36与凹槽40内的不纯物，再进行一外延成长制作工艺形成一外延层42于凹槽40内作为第一区域14的源极/漏极区域。在本实施例中，外延层42优选包含磷化硅(SiP)。
随后如图4所示，形成另一硬掩模层44于第一区域14与第二区域16并覆盖第一区域14的栅极结构18与外延层42以及第二区域16的硬掩模层36。在本实施例中，硬掩模层44优选由氮化硅所构成，但不局限于此。
如图5所示，然后形成一图案化掩模，例如一图案化光致抗蚀剂(图未示)于第一区域14，并利用图案化光致抗蚀剂为掩模进行一蚀刻制作工艺，去除第二区域16上的硬掩模层44、部分硬掩模层36、部分硬掩模34以及部分硬掩模32，以形成间隙壁46与凹槽48于栅极结构20旁的基底12内。值得注意的是，第二区域16的硬掩模层44优选于蚀刻过程中被消耗殆尽，硬掩模32与硬掩模34优选在蚀刻过程中被部分去除形成间隙壁46，大部分的硬掩模层36则于形成凹槽48的过程中被去除，而仅留部分硬掩模层36设于间隙壁46的侧壁。
然后如图6所示，选择性进行一清洗制作工艺完全去除残留于第二区域16间隙壁46侧壁的硬掩模层36与凹槽48内的不纯物，并同时去除第一区域14的部分硬掩模层44，但仍使第一区域14所剩余的硬掩模层44覆盖于各栅极结构18顶部与侧壁以及外延层42上表面。接着形成一外延层50于凹槽48内作为第二区域16的源极/漏极区域，其中外延层50优选包含锗化硅。
值得注意的是，进行前述清洗制作工艺后残留于第一区域14栅极结构18侧壁与外延层42表面的硬掩模层44通常具有不同厚度。在本实施例中，残留于栅极结构18正上方与栅极结构18侧壁的硬掩模层44厚度约为残留于外延层42表面硬掩模层44厚度的两倍，例如残留于栅极结构18正上方与栅极结构18侧壁的硬掩模层44厚度约略为40埃，而残留于外延层42表面的硬掩模层44厚度则约略为20埃。
请接着参照图7至图10，图7至图10为后续利用清洗制作工艺去除第一区域14的硬掩模层44并形成接触插塞72的制作工艺示意图。需注意的是，为了凸显第一区域14，即NMOS区域去除硬掩模层44以及形成接触插塞72的步骤，图7至图10仅绘示第一区域14的部分栅极结构18与外延层42以及单一连接外延层42的接触插塞72。
如图7所示，首先可选择性形成一图案化掩模(图未示)覆盖第二区域16，并进行一第一清洗制作工艺去除部分第一区域14栅极结构18侧壁的部分硬掩模层44与外延层42表面的硬掩模层44并同时形成一保护层52于外延层42上，其中所形成的保护层52优选由氧化硅所构成，且第一清洗制作工艺所使用的清洗溶液优选选自由稀释氢氟酸(dilutedhydrofluoric acid,dHF)、磷酸(H3PO4)以及含有氢氧化铵(NH4OH)、过氧化氢(H2O2)的标准清洗溶液SC1所构成的群组。
更具体而言，清洗溶液中的稀释氢氟酸优选用来去除残留于外延层42表面的原生氧化物，磷酸优选用来去除由氮化硅所构成的硬掩模层44，标准清洗溶液SC1则优选用来形成由氧化硅所构成的保护层52。若从细部来看，本实施例以上述清洗溶液进行第一清洗制作工艺时优选先完全去除外延层42表面的所有硬掩模层44与部分设于栅极结构18侧壁且位于外延层42两侧的硬掩模层44，然后再形成一保护层52于裸露出的外延层42表面。
另外在本实施例中，清洗溶液中稀释氢氟酸的时间参数优选约为15秒，磷酸的温度优选介于150℃至190℃或最佳为161℃，磷酸的时间优选小于60秒或最佳为30秒，标准清洗溶液SC1的温度介于25℃至60℃或最佳为25℃，标准清洗溶液SC1的时间则小于120秒或最佳为90秒。
如图8所示，接着进行一第二清洗制作工艺去除栅极结构18上所剩余的硬掩模层44并暴露出间隙壁38，其中第二清洗制作工艺所使用的清洗溶液优选选自由磷酸(H3PO4)以及含有氢氧化铵(NH4OH)、过氧化氢(H2O2)的标准清洗溶液SC1所构成的群组。
更具体而言，本实施例优选于进行第二清洗制作工艺时利用磷酸去除设于栅极结构18上的所有硬掩模层44，包括所有残留于栅极结构18顶部与侧壁的所有硬掩模层44。通过保护层52的保护，外延层42表面可于清洗过程中不受到清洗溶液的伤害而耗损。甚至在清洗过程中若发生保护层52消耗的情形，可通过标准清洗溶液SC1再次形成保护层52。换句话说，在利用清洗溶液去除硬掩模层44的过程中外延层42表面的保护层52会一直存在，且在硬掩模层44完全去除后外延层42表面仍可留有部分保护层52，或使保护层52完全消耗殆尽，这些均属本发明所涵盖的范围。
另外需注意的是，完成上述两道清洗制作工艺后本实施例优选略微改变外延层42表面的轮廓。如图8所示，处理过后的外延层42优选包含一平坦表面54以及突起部56设于平坦表面54两侧。
如图9所示，然后可选择性去除未完全去除的保护层52，并选择性形成一由氮化硅所构成的接触洞蚀刻停止层(contact etch stop layer,CESL)58于基底12上并覆盖栅极结构18，以及形成一层间介电层60于CESL 58上。接着后进行一平坦化制作工艺，例如利用CMP去除部分层间介电层60、部分接触洞蚀刻停止层58、硬掩模28以及硬掩模26并暴露出由多晶硅材料所构成的栅极材料层24，使栅极材料层24上表面与层间介电层60上表面齐平。
随后进行一金属栅极置换制作工艺将第一区域14与第二区域16的栅极结构18、20转换为金属栅极。以第一区域14为例，可先进行一选择性的干蚀刻或湿蚀刻制作工艺，例如利用氨水(ammonium hydroxide,NH4OH)或氢氧化四甲铵(TetramethylammoniumHydroxide,TMAH)等蚀刻溶液来去除栅极结构18中栅极材料层24，以于层间介电层60中形成多个凹槽(图未示)。之后依序形成一高介电常数介电层62以及至少包含U型功函数金属层64与低阻抗金属层66的导电层于各凹槽内，并再搭配进行一平坦化制作工艺使U型高介电常数介电层62、U型功函数金属层64与低阻抗金属层66的表面与层间介电层60表面齐平。
在本实施例中，高介电常数介电层62包含介电常数大于4的介电材料，例如是选自氧化铪(hafnium oxide，HfO2)、硅酸铪氧化合物(hafnium silicon oxide，HfSiO4)、硅酸铪氮氧化合物(hafnium silicon oxynitride，HfSiON)、氧化铝(aluminum oxide，Al2O3)、氧化镧(lanthanum oxide，La2O3)、氧化钽(tantalum oxide，Ta2O5)、氧化钇(yttrium oxide，Y2O3)、氧化锆(zirconium oxide，ZrO2)、钛酸锶(strontium titanate oxide，SrTiO3)、硅酸锆氧化合物(zirconium silicon oxide，ZrSiO4)、锆酸铪(hafnium zirconium oxide，HfZrO4)、锶铋钽氧化物(strontium bismuth tantalate,SrBi2Ta2O9,SBT)、锆钛酸铅(leadzirconate titanate,PbZrxTi1-xO3,PZT)、钛酸钡锶(barium strontium titanate,BaxSr1- xTiO3,BST)、或其组合所组成的群组。
功函数金属层64优选用以调整形成金属栅极的功函数，使其适用于N型晶体管(NMOS)或P型晶体管(PMOS)。若晶体管为N型晶体管，功函数金属层64可选用功函数为3.9电子伏特(eV)～4.3eV的金属材料，如铝化钛(TiAl)、铝化锆(ZrAl)、铝化钨(WAl)、铝化钽(TaAl)、铝化铪(HfAl)或TiAlC(碳化钛铝)等，但不以此为限；若晶体管为P型晶体管，功函数金属层64可选用功函数为4.8eV～5.2eV的金属材料，如氮化钛(TiN)、氮化钽(TaN)或碳化钽(TaC)等，但不以此为限。功函数金属层64与低阻抗金属层66之间可包含另一阻障层(图未示)，其中阻障层的材料可包含钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)等材料。低阻抗金属层66则可选自铜(Cu)、铝(Al)、钨(W)、钛铝合金(TiAl)、钴钨磷化物(cobalttungsten phosphide，CoWP)等低电阻材料或其组合。由于依据金属栅极置换制作工艺将虚置栅极转换为金属栅极是此领域者所熟知技术，在此不另加赘述。接着可去除部分高介电常数介电层62、部分功函数金属层64与部分低阻抗金属层66形成凹槽(图未示)，然后再填入一硬掩模68于凹槽内并使硬掩模68与层间介电层60表面齐平，其中硬掩模68可选自由氧化硅、氮化硅、氮氧化硅以及氮碳化硅所构成的群组。
如图10所示，接着进行一接触插塞制作工艺搭配金属硅化物制作工艺形成一金属硅化物于外延层42表面以及一接触插塞72电连接栅极结构18两侧的源极/漏极区域与外延层42。在本实施例中，接触插塞制作工艺可利用图案化掩模进行一蚀刻制作工艺，去除栅极结构18之间的部分层间介电层60以形成一接触洞(图未示)暴露外延层42表面。然后依序沉积一第一金属层74与第二金属层76于接触洞中，其中第一金属层74与第二金属层76优选共形地(conformally)形成于外延层42表面及接触洞的内侧侧壁。在本实施例中，第一金属层74优选选自钛、钴、镍及铂等所构成的群组，且最佳为钛，而第二金属层76则优选包含氮化钛、氮化钽等金属化合物。
在连续沉积第一金属层74与第二金属层76之后，依序进行一第一热处理制作工艺与一第二热处理制作工艺以形成一金属硅化物78于外延层42上。在本实施例中，第一热处理制作工艺包含一常温退火(soak anneal)制作工艺，其温度优选介于500℃至600℃，且最佳为550℃，而其处理时间则优选介于10秒至60秒，且最佳为30秒。第二热处理制作工艺包含一峰值退火(spike anneal)制作工艺，其温度优选介于600℃至950℃，且最佳为600℃，而其处理优选时间则优选介于100毫秒至5秒，且最佳为5秒。
进行两次热处理制作工艺后，形成一第三金属层80并填满接触洞。在本实施例中，第三金属层80优选包含钨，但不局限于此。最后进行一平坦化制作工艺，例如以CMP制作工艺部分去除第三金属层80、部分第二金属层76及部分第一金属层74，甚至可视制作工艺需求接着去除部分层间介电层60，以形成接触插塞72电连接外延层42。至此即完成本发明优选实施例一半导体元件的制作。
请继续参照图10，其另公开本发明优选实施例的一半导体元件结构。如图10所示，半导体元件优选包含至少一栅极结构18设于基底12上，一外延层42设于栅极结构18两侧的基底12内，一接触插塞72镶嵌于部分外延层42中以及一金属硅化物78设于接触插塞72底部。更具体而言，外延层42包含一平坦表面54以及突起部56设于平坦表面54两侧，接触插塞72的一底表面包含弧形，金属硅化物78的一底表面，即与外延层42接触的表面也包含弧形。
综上所述，本发明优选于栅极结构两侧形成外延层后依序进行两道清洗制作工艺，其中第一道清洗制作工艺优选去除栅极结构侧壁的部分硬掩模层之外又同时形成一保护层于外延层表面，第二道清洗制作工艺则用来完全去除栅极结构上所剩余的硬掩模层。依据本发明优选实施例，本发明可于第二道清洗制作工艺时利用保护层的遮蔽来防止清洗溶液侵蚀保护层下方的外延层，进而影响元件的运作。此外，本发明所公开的两道清洗制作工艺虽优选应用至NMOS晶体管，但并不局限于此，又可视制作工艺需求对PMOS晶体管区也比照进行前述的清洗制作工艺，使PMOS晶体管区也可同样形成如图10所揭露具有突起部的外延层结构，此变化型也属本发明所涵盖的范围。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (15)

1.一种制作半导体元件的方法，包含：
提供一基底；
形成一第一栅极结构于该基底上以及一第一间隙壁于该第一栅极结构旁；
形成一第一外延层于该第一栅极结构旁的该基底内；
形成一第一硬掩模层于该第一栅极结构上；
进行一第一清洗制作工艺去除部分该第一栅极结构侧壁的部分该第一硬掩模层并同时形成保护层于该第一外延层上；以及
进行一第二清洗制作工艺去除该第一栅极结构上剩余的该第一硬掩模层。
2.如权利要求1所述的方法，其中该基底上具有一第一区域以及一第二区域，该方法包含：
形成该第一栅极结构于该第一区域以及一第二栅极结构于该第二区域；
形成一第二硬掩模层于该第一区域及该第二区域；
去除该第一区域上的部分该第二硬掩模层并形成该第一间隙壁以及一第一凹槽于该第一栅极结构旁；
形成该第一外延层于该第一凹槽内；
形成该第一硬掩模层于该第一区域及该第二区域；
去除该第二区域上的部分该第一硬掩模层并形成一第二间隙壁于该第二区域上、该第一硬掩模层于该第一区域的该第一栅极结构上以及一第二凹槽于该第二栅极结构旁；以及
形成一第二外延层于该第二凹槽内。
3.如权利要求2所述的方法，其中该第一外延层包含磷化硅以及该第二外延层包含锗化硅。
4.如权利要求2所述的方法，其中该第二硬掩模层包含氮化硅。
5.如权利要求1所述的方法，其中该第一硬掩模层包含氮化硅。
6.如权利要求1所述的方法，其中该第一间隙壁包含碳氮氧化硅(SiOCN)。
7.如权利要求1所述的方法，其中该保护层包含氧化硅。
8.如权利要求1所述的方法，还包含去除剩余的该第一硬掩模层但不去除该保护层。
9.如权利要求1所述的方法，其中第一清洗制作工艺所使用的清洗溶液选自由稀释氢氟酸(diluted hydrofluoric acid,dHF)、磷酸以及标准清洗溶液SC1所构成的群组。
10.如权利要求1所述的方法，其中第二清洗制作工艺所使用的清洗溶液选自由磷酸以及标准清洗溶液SC1所构成的群组。
11.一种采用如权利要求1所述方法制得的半导体元件，包含：
基底；
栅极结构，设于该基底上；以及
外延层，设于该栅极结构旁的该基底内，该外延层包含一平坦表面以及突起部设于该平坦表面两侧。
12.如权利要求11所述的半导体元件，还包含一接触插塞，镶嵌于部分该外延层中，该接触插塞的一底表面包含弧形。
13.如权利要求12所述的半导体元件，还包含一金属硅化物，设于该接触插塞下方。
14.如权利要求13所述的半导体元件，其中该金属硅化物的一底表面包含弧形。
15.如权利要求11所述的半导体元件，其中该外延层包含磷化硅。
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