CN108022842B - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

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CN108022842B
CN108022842B CN201610957169.5A CN201610957169A CN108022842B CN 108022842 B CN108022842 B CN 108022842B CN 201610957169 A CN201610957169 A CN 201610957169A CN 108022842 B CN108022842 B CN 108022842B
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layer
substrate
raised epitaxial
gate structure
semiconductor device
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CN108022842A (zh
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何万迅
邢溯
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to US16/280,047 priority patent/US10978556B2/en
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Abstract

本发明公开一种半导体元件及其制作方法。该制作半导体元件的方法，首先提供一基底，然后形成一栅极结构于该基底上，形成一硬掩模于基底及栅极结构上，图案化硬掩模以形成多个沟槽暴露出部分基底表面，之后再形成垫高外延层于该多个沟槽内。

Description

半导体元件及其制作方法
技术领域
本发明涉及一种制作半导体元件的方法，尤其是涉及一种于基底与栅极结构上形成图案化硬掩模暴露部分基底并于所暴露出的基底表面形成垫高外延层的方法。
背景技术
为了能增加半导体结构的载流子迁移率，可以选择对于栅极通道施加压缩应力或是伸张应力。举例来说，若需要施加的是压缩应力，现有技术常利用选择性外延成长(selective epitaxial growth,SEG)技术于一硅基底内形成晶格排列与该硅基底相同的外延结构，例如硅锗(silicon germanium,SiGe)外延结构。利用硅锗外延结构的晶格常数(lattice constant)大于该硅基底晶格的特点，对P型金属氧化物半导体晶体管的通道区产生应力，增加通道区的载流子迁移率(carrier mobility)，并用于增加金属氧化物半导体晶体管的速度。反之，若是N型半导体晶体管则可选择于硅基底内形成硅碳(siliconcarbide,SiC)外延结构，对栅极通道区产生伸张应力。
然而，现今以外延成长方式形成外延层的过程中对阻值的平衡以及抑制短通道效应(short channel effect,SCE)等方面仍不尽理想。因此，如何改良现有制作工艺技术以解决现有瓶颈即为现今一重要课题。
发明内容
本发明较佳实施例公开一种制作半导体元件的方法。首先提供一基底，然后形成一栅极结构于该基底上，形成一硬掩模于基底及栅极结构上，图案化硬掩模以形成多个沟槽暴露出部分基底表面，之后再形成垫高外延层于该多个沟槽内。
本发明另一实施例公开一种半导体元件，其主要包含一栅极结构沿着一第一方向延伸并设置于一基底上，以及多个垫高外延层沿着一第二方向延伸设于基底上并设于栅极结构两侧。在本实施例中，基底包含一第一半导体层、一绝缘层设于第一半导体层上以及一第二半导体层设于绝缘层上。
附图说明
图1为本发明较佳实施例制作一半导体元件的立体示意图；
图2为图1中沿着切线AA’的剖面示意图；
图3为接续图1制作半导体元件的立体示意图；
图4为图3中沿着切线BB’的剖面示意图；
图5为接续图3制作半导体元件的立体示意图；
图6为图5中沿着切线CC’与切线DD’的剖面示意图；
图7为接续图5制作半导体元件的立体示意图；
图8为图7中沿着切线EE’与切线FF’的剖面示意图；
图9为接续图7制作半导体元件的立体示意图；
图10为图9中沿着切线GG’与切线HH’的剖面示意图；
图11为接续图9制作半导体元件的立体示意图；
图12为图11中沿着切线II’与切线JJ’的剖面示意图；
图13为本发明一实施例的半导体元件的剖面示意图。
主要元件符号说明
12 基底 14 第一半导体层
16 绝缘层 18 第二半导体层
20 栅极结构 22 栅极介电层
24 栅极材料层 26 硬掩模
28 第一间隙壁 30 硬掩模
32 图案化硬掩模 34 沟槽
36 垫高外延层 38 轻掺杂漏极
40 斜角离子注入 42 第二间隙壁
44 硅化金属层 46 层间介电层
48 接触插塞 50 源极/漏极区域
52 高介电常数介电层 54 功函数金属层
56 低阻抗金属层 58 硬掩模
具体实施方式
请参照图1至图12，图1至图12则为本发明较佳实施例制作一半导体元件的制作工艺示意图。首先请参照图1至图2，图1为本发明较佳实施例制作一半导体元件的立体示意图，图2则为图1中沿着切线AA’的剖面示意图。如图1至图2所示，首先提供一基底12，且基底12上较佳定义有一主动区域。
在本实施例中，基底12较佳为一由硅覆绝缘(silicon-on-insulator,SOI)基底所构成的半导体基底，其中基底12主要包含一第一半导体层14、一绝缘层16设于第一半导体层14上以及一第二半导体层18设于绝缘层16上。更具体而言，第一半导体层14与第二半导体层18可包含相同或不同材料且可分别选自由硅、锗以及锗化硅所构成的群组，设置于第一半导体层14与第二半导体层18之间的绝缘层16较佳包含二氧化硅(SiO2)，但不局限于此。需注意的是，本实施例虽较佳选用硅覆绝缘基底作为半导体元件的基底，但依据本发明的其他实施例，基底12又可选用例如是硅基底、外延硅基底、碳化硅基底等的半导体基底，这些材料选择也均属本发明所涵盖的范围。
然后形成一栅极结构20于基底12上。在本实施例中，形成栅极结构20的方式可依序形成一栅极介电层22、一栅极材料层24以及一硬掩模26于基底12上，并利用一图案化光阻(图未示)当作掩模进行一图案转移制作工艺，以单次蚀刻或逐次蚀刻步骤去除部分硬掩模26、部分栅极材料层24与部分栅极介电层22，然后剥除图案化光阻，以于主动区上形成由图案化的栅极介电层22、图案化的栅极材料层24以及图案化的硬掩模26所构成的栅极结构20。在本实施例中，栅极介电层22可包含二氧化硅、氮化硅(SiN)或高介电常数(highdielectric constant,high-k)材料，栅极材料层24可包含金属材料、多晶硅或金属硅化物(silicide)等导电材料，而硬掩模26可选自由二氧化硅、氮化硅、碳化硅(SiC)以及氮氧化硅(SiON)所构成的群组。
然后在栅极结构20侧壁形成至少一第一间隙壁28，例如一偏位间隙壁。在本实施例中，第一间隙壁28较佳为单一间隙壁，其可选自由氧化硅、氮化硅、氮氧化硅以及氮碳化硅所构成的群组，但不局限于此。除此之外，依据本发明一实施例，第一间隙壁28又可依据制作工艺需求为一复合式间隙壁，例如又可细部包含一第一子间隙壁(图未示)与第二子间隙壁(图未示)，第一子间隙壁与第二子间隙壁的其中一者的剖面可呈现L型或I型，第一子间隙壁与第二子间隙壁可包含相同或不同材料，且两者均可选自由氧化硅、氮化硅、氮氧化硅以及氮碳化硅所构成的群组。以下制作工艺均以第一间隙壁28为单一间隙壁的实施例进行说明。
请接着参照图3至图4，图3为接续图1制作半导体元件的立体示意图，图4则为图3中沿着切线BB’的剖面示意图。如图3至图4所示，然后形成一硬掩模30覆盖基底12与栅极结构20上，其中硬掩模30较佳全面性覆盖并接触第二半导体层18表面、栅极结构20上表面以及第一间隙壁28表面。在本实施例中，硬掩模30较佳由介电材料所构成，其可包含二氧化硅、氮化硅、碳化硅(SiC)、氮氧化硅(SiON)或其组合，但不局限于此。
请接着参照图5至图6，图5为接续图3制作半导体元件的立体示意图，图6上半部为图5中沿着切线CC’的剖面示意图，而图6下半部则为图5中沿着切线DD’的剖面示意图。如图5至图6所示，然后对硬掩模30进行一图案转移制作工艺，例如可先形成一图案化光阻(图未示)于硬掩模30上，接着利用图案化光阻为掩模去除部分硬掩模30以形成一图案化硬掩模32，并同时形成多个沟槽34暴露出部分第二半导体层18表面。
请接着参照图7至图8，图7为接续图5制作半导体元件的立体示意图，图8上半部为图7中沿着切线EE’的剖面示意图，图8下半部则为图7中沿着切线FF’的剖面示意图。如图7至图8所示，随后进行一成长制作工艺，例如可利用一选择性外延成长制作工艺形成多个垫高外延层36于图案化硬掩模32的沟槽34内。更具体而言，垫高外延层36较佳形成于所有被沟槽34所暴露出的第二半导体层18表面并沿着沟槽34的形状填满沟槽34，因此由图7的立体图来看所形成的多个垫高外延层36较佳为多个长条状的垫高外延层36延伸于栅极结构20两侧。从另一角度来看，栅极结构20较佳沿着一第一方向D1延伸并设置于基底12或第二半导体层18上，多个垫高外延层36则沿着一第二方向D2延伸于栅极结构20两侧，其中第一方向D1与第二方向D2大约成90度。
从图8下方的剖面来看，垫高外延层36上表面虽较佳略高于图案化硬掩模32上表面，但又可依据制作工艺需求切齐图案化硬掩模32上表面，此实施例也属本发明所涵盖的范围。另外在本实施例中，所形成的垫高外延层36可依据元件的导电型态包含例如锗化硅、碳化硅或磷化硅等材料，且依据本发明一实施例又可依据制作工艺需求选择性于形成垫高外延层36时利用现场(in-situ)掺植的方式形成轻掺杂漏极。
请接着参照图9至图10，图9为接续图7制作半导体元件的立体示意图，图10上半部为图9中沿着切线GG’的剖面示意图，图10下半部则为图9中沿着切线HH’的剖面示意图。如图9至图10所示，然后先完全去除图案化硬掩模32暴露出垫高外延层36两侧的第二半导体层18表面，随后利用栅极结构20与第一间隙壁28为掩模进行一离子注入制作工艺，将离子注入垫高外延层36中以形成一轻掺杂漏极38。需注意的是，本实施例中所进行的离子注入制作工艺可依据制作工艺需求选用斜角离子注入40的方式注入离子，且进行离子注入制作工艺时可选择性调整注入离子的能量，使离子仅注入垫高外延层36内或可注入垫高外延层36外再向下穿过垫高外延层36并同时注入部分第二半导体层18内，这些实施例均属本发明所涵盖的范围。另外本实施例虽于形成图案化硬掩模32之后才形成轻掺杂漏极38，但不局限于此，依据本发明其他实施例又可选择于图3形成硬掩模30之前或图5形成图案化硬掩模32之前形成轻掺杂漏极，这些实施例均属发明所涵盖的范围。
随后形成一第二间隙壁42于第一间隙壁28旁并同时设于垫高外延层36上。在本实施例中，第二间隙壁42与第一间隙壁28可选用相同或不同材料，其中第二间隙壁42较佳为单一间隙壁，且可选自由氧化硅、氮化硅、氮氧化硅以及氮碳化硅所构成的群组，但不局限于此。如同前述第一间隙壁28的实施例，第二间隙壁42又可依据制作工艺需求为一复合式间隙壁，例如又可细部包含一第一子间隙壁(图未示)与第二子间隙壁(图未示)，第一子间隙壁与第二子间隙壁的其中一者的剖面可呈现L型或I型，第一子间隙壁与第二子间隙壁可包含相同或不同材料，且两者均可选自由氧化硅、氮化硅、氮氧化硅以及氮碳化硅所构成的群组。之后可再选择性进行另一离子注入制作工艺，利用例如前述形成轻掺杂漏极的方式将离子注入第二间隙壁42两侧的垫高外延层36或垫高外延层36与第二半导体层18中形成源极/漏极区域50。
请接着参照图11至图12，图11为接续图9制作半导体元件的立体示意图，图12上半部为图11中沿着切线II’的剖面示意图，图12下半部则为图11中沿着切线JJ’的剖面示意图。如图11至图12所示，之后可进行一硅化金属制作工艺，例如可先形成一金属层(图未示)于第二半导体层18、垫高外延层36与栅极结构20表面，其中金属层可选自钨、钴、钛、镍、铂、钯、钼等或上述金属的合金。接着进行一热处理，例如一快速升温退火制作工艺(rapidthermal anneal,RTA)，以于垫高外延层36以及未被垫高外延层36所覆盖的第二半导体层18上形成硅化金属层44。之后再利用湿蚀刻化学溶液，例如氨水、过氧化氢、盐酸、硫酸、硝酸、以及醋酸等混和溶液来移除未反应的金属层。值得注意的是，由于多个垫高外延层36是以长条状排列于栅极结构20两侧的基底12上，因此所形成的硅化金属层44除了设于第二半导体层18上表面又同时覆盖于垫高外延层36的上表面与侧壁，而构成一种连续的阶梯形状。
此外，依据本发明一实施例，又可选择于图9形成源极/漏极区域50后再进行另一外延成长制作工艺，以于第二半导体层18表面与垫高外延层36上形成一外延层(图未示)，其中外延层可选自由硅、锗以及锗化硅所构成的群组。换句话说，所形成的外延层较佳覆盖于所有第二半导体层18上表面以及垫高外延层36上表面与侧壁且不暴露出任何第二半导体层18表面。从剖面来看，所形成的外延层较佳与图11的硅化金属层44一般呈现出连续的阶梯状剖面结构。之后可比照图11与图12进行一硅化金属制作工艺，以于外延层上形成一硅化金属层。由于硅化金属层是沿着外延层的轮廓成长，因此形成于外延层表面的硅化金属层同样具有连续的阶梯状剖面。
之后可选择性形成一由氮化硅所构成的接触洞蚀刻停止层(contact etch stoplayer,CESL)(图未示)于基底12上覆盖栅极结构20，再形成一层间介电层46于接触洞蚀刻停止层上。
然后进行一接触插塞制作工艺，例如可先以蚀刻方式去除部分层间介电层46形成多个接触洞(图未示)暴露栅极结构20两侧的部分硅化金属层44，再填入导电材料于接触洞中并形成接触插塞48电连接垫高外延层36或源极/漏极区域50。在本实施例中，形成接触插塞48的方式可先依序沉积一阻隔层(图未示)与一金属层(图未示)于接触洞内，再利用一平坦化制作工艺，例如以CMP去除部分金属层、部分阻隔层甚至部分层间介电层46，以于接触洞中形成接触插塞48，其中接触插塞48上表面较佳与层间介电层46上表面切齐。在本实施例中，阻隔层较佳选自由钛、钽、氮化钛、氮化钽以及氮化钨所构成的群组，金属层较佳选自由铝、钛、钽、钨、铌、钼以及铜所构成的群组，但不局限于此。至此即完成本发明的半导体元件的制作。
值得注意的是，上述实施例虽于栅极结构20两侧分别形成多个接触插塞连接垫高外延层36，但不局限于此，依据本发明的一实施例，又可选择以沟槽式接触插塞(slotcontact)的制作工艺方式分别形成一接触插塞连接栅极结构20两侧的源极/漏极区域50。更具体而言，由于栅极结构20两侧的沟槽式接触插塞同时横跨多个垫高外延层36，因此所形成的沟槽式接触插塞底部较佳同时接触垫高外延层36上方的硅化金属层44与第二半导体层18上方的硅化金属层44，使沟槽式接触插塞的底部呈现如硅化金属层44般的阶梯状剖面。
此外，除了上述以先栅极(gate first)制作工艺所制作的半导体元件，本发明又可将上述制作工艺应用至后栅极(gate last)制作工艺。以后栅极制作工艺的后高介电常数介电层(high-k last)制作工艺为例，如图13的剖视图所示，本发明可于图11至图12形成层间介电层46之后进行一平坦化制作工艺，例如利用化学机械研磨(chemical mechanicalpolishing,CMP)去除部分层间介电层46与硬掩模26并暴露出由多晶硅材料所构成的栅极材料层24，使各栅极材料层24上表面与层间介电层46上表面齐平。
随后进行一金属栅极置换制作工艺将栅极结构20转换为金属栅极。例如可先进行一选择性的干蚀刻或湿蚀刻制作工艺，例如利用氨水(ammonium hydroxide,NH4OH)或氢氧化四甲铵(Tetramethylammonium Hydroxide,TMAH)等蚀刻溶液来去除栅极结构20中的栅极材料层24，以于层间介电层46中形成凹槽(图未示)。之后依序形成一高介电常数介电层52、一功函数金属层54以及一低阻抗金属层56于凹槽内，然后进行一平坦化制作工艺，例如利用CMP去除部分低阻抗金属层56、部分功函数金属层54与部分高介电常数介电层52以形成金属栅极。以本实施例利用后高介电常数介电层制作工艺所制作的栅极结构为例，栅极结构20较佳包含一介质层或栅极介电层22、一U型高介电常数介电层52、一U型功函数金属层54以及一低阻抗金属层56。
在本实施例中，高介电常数介电层52包含介电常数大于4的介电材料，例如选自氧化铪(hafnium oxide，HfO2)、硅酸铪氧化合物(hafnium silicon oxide,HfSiO4)、硅酸铪氮氧化合物(hafnium silicon oxynitride,HfSiON)、氧化铝(aluminum oxide,Al2O3)、氧化镧(lanthanum oxide,La2O3)、氧化钽(tantalum oxide,Ta2O5)、氧化钇(yttrium oxide,Y2O3)、氧化锆(zirconium oxide,ZrO2)、钛酸锶(strontium titanate oxide,SrTiO3)、硅酸锆氧化合物(zirconium silicon oxide,ZrSiO4)、锆酸铪(hafnium zirconium oxide,HfZrO4)、锶铋钽氧化物(strontium bismuth tantalate,SrBi2Ta2O9,SBT)、锆钛酸铅(leadzirconate titanate,PbZrxTi1-xO3,PZT)、钛酸钡锶(barium strontium titanate,BaxSr1- xTiO3,BST)、或其组合所组成的群组。
功函数金属层54较佳用以调整形成金属栅极的功函数，使其适用于N型晶体管(NMOS)或P型晶体管(PMOS)。若晶体管为N型晶体管，功函数金属层54可选用功函数为3.9电子伏特(eV)～4.3eV的金属材料，如铝化钛(TiAl)、铝化锆(ZrAl)、铝化钨(WAl)、铝化钽(TaAl)、铝化铪(HfAl)或TiAlC(碳化钛铝)等，但不以此为限；若晶体管为P型晶体管，功函数金属层54可选用功函数为4.8eV～5.2eV的金属材料，如氮化钛(TiN)、氮化钽(TaN)或碳化钽(TaC)等，但不以此为限。功函数金属层54与低阻抗金属层56之间可包含另一阻障层(图未示)，其中阻障层的材料可包含钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)等材料。低阻抗金属层56则可选自铜(Cu)、铝(Al)、钨(W)、钛铝合金(TiAl)、钴钨磷化物(cobalttungsten phosphide，CoWP)等低电阻材料或其组合。
接着去除部分高介电常数介电层52、部分功函数金属层54与部分低阻抗金属层56形成凹槽(图未示)，然后再填入硬掩模58于凹槽内并使硬掩模58与层间介电层46表面齐平，其中硬掩模44可选自由氧化硅、氮化硅、氮氧化硅以及氮碳化硅所构成的群组。最后再依据前述接触插塞制作工艺形成接触插塞48于层间介电层46中电连接垫高外延层36或源极/漏极区域50。
以上所述仅为本发明的较佳实施例，凡依本发明权利要求所做的均等变化与修饰，皆应属本发明的涵盖范围。

Claims (18)

1.一种制作半导体元件的方法，包含：
提供一基底，具有上表面；
形成一栅极结构于该基底上，其中该栅极结构具有连续平坦的下表面；
形成一硬掩模于该基底及该栅极结构上，该硬掩模直接接触该上表面；
图案化该硬掩模以形成多个沟槽暴露出部分该基底的该上表面；
形成垫高外延层于该多个沟槽内且直接接触该上表面；以及
注入离子至该垫高外延层及该基底的至少一部分以于该栅极结构的两侧形成源极/漏极区域，其中该源极/漏极区域包含连续的阶梯状剖面结构。
2.如权利要求1所述的方法，其中该基底包含：
第一半导体层；
绝缘层设于该第一半导体层上；以及
第二半导体层设于该绝缘层上。
3.如权利要求2所述的方法，其中该垫高外延层的侧壁以及该第二半导体层的上表面包含一直角。
4.如权利要求2所述的方法，另包含于形成该硬掩模之前形成一第一间隙壁于该栅极结构旁。
5.如权利要求4所述的方法，另包含：
在形成该垫高外延层之后去除该硬掩模；
注入离子至该垫高外延层中以形成一轻掺杂漏极；以及
形成一第二间隙壁于该第一间隙壁旁并设于该垫高外延层上。
6.如权利要求5所述的方法，另包含注入离子至该垫高外延层及该第二半导体层中以形成该轻掺杂漏极。
7.如权利要求1所述的方法，另包含形成一硅化金属层于该垫高外延层的上表面及侧壁。
8.如权利要求1所述的方法，另包含形成一硅化金属层于该垫高外延层的上表面及侧壁以及该基底的上表面。
9.如权利要求1所述的方法，其中该垫高外延层的下表面切齐该栅极结构的下表面。
10.如权利要求1所述的方法，其中该栅极结构沿着一第一方向延伸于该基底上，且该垫高外延层沿着一第二方向延伸于该栅极结构两侧。
11.一种如采用权利要求8所述方法制备的半导体元件，包含：
栅极结构，沿着一第一方向延伸并设置于一基底上；
多个垫高外延层，沿着一第二方向延伸设于该基底上并设于该栅极结构两侧；
硅化金属层，设于该多个垫高外延层的上表面及侧壁以及该基底的上表面而构成一连续的阶梯形状。
12.如权利要求11所述的半导体元件，其中该基底包含：
第一半导体层；
绝缘层设于该第一半导体层上；以及
第二半导体层设于该绝缘层上。
13.如权利要求12所述的半导体元件，其中该多个垫高外延层的侧壁以及该第二半导体层的上表面包含一直角。
14.如权利要求12所述的半导体元件，另包含一轻掺杂漏极设于该多个垫高外延层内以及该第二半导体层内。
15.如权利要求11所述的半导体元件，另包含一第一间隙壁设于该栅极结构旁。
16.如权利要求15所述的半导体元件，其中该间隙壁的下表面切齐该多个垫高外延层的下表面。
17.如权利要求15所述的半导体元件，另包含一第二间隙壁设于该第一间隙壁旁并设于该多个垫高外延层上。
18.如权利要求11所述的半导体元件，其中该多个垫高外延层的下表面切齐该栅极结构的下表面。
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