CN114300363A - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

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CN114300363A
CN114300363A CN202111637731.3A CN202111637731A CN114300363A CN 114300363 A CN114300363 A CN 114300363A CN 202111637731 A CN202111637731 A CN 202111637731A CN 114300363 A CN114300363 A CN 114300363A
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layer
semiconductor device
forming
germanium
gate structure
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吕佳霖
林俊贤
陈俊隆
廖琨垣
张峰溢
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Blue Gun Semiconductor Co ltd
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Abstract

本发明公开一种半导体元件及其制作方法。其中，该半导体元件包含一鳍状结构，一栅极结构，一外延层，一锗层，一层间介电层以及一第一插塞。该鳍状结构设置在一基底上。该栅极结构横跨该鳍状结构。该外延层设置在该鳍状结构内且邻接该栅极结构。该锗层设置在该外延层上。该层间介电层覆盖在该基底及该鳍状结构上。该第一插塞设置在该层间介电层内并接触该锗层。

Description

半导体元件及其制作方法
本申请是申请日为2015年9月16日且发明名称为“半导体元件及其制造方法”的中国专利申请201510589504.6的分案申请。
技术领域
本发明涉及一种半导体元件及其形成方法，尤其是涉及一种具有插塞结构的半导体元件及其形成方法。
背景技术
随着半导体制作工艺的线宽不断缩小，半导体元件的尺寸不断地朝微型化发展，然而，由于目前半导体制作工艺的线宽微小化至一定程度后，具金属栅极的半导体结构的整合制作工艺也浮现出更多挑战与瓶颈。
其中，为了使微型化的半导体元件满足高度集成及高速运作的效果，现有技术利用微型化的布线通孔与层间介电层形成多层互联的配线结构，以分别电连接晶体管的金属栅极以及源极/漏极，作为和对外电子信号的输入/输出端。然而，现有技术在结合金属栅极与接触插塞等元件的制作工艺时仍因光学的限制遇到一些瓶颈，例如所形成电连接源极/漏极的接触插塞常因所设置的位置不佳而直接贯穿金属栅极，影响元件的整体电性表现。有鉴于此，如何有效改良半导体元件制作工艺与架构即为现今一重要课题。
发明内容
本发明的一目的在于提供一种形成具有插塞结构的半导体元件的方法，以改善整体半导体元件的电性表现。
本发明的另一目的在于提供一种具有插塞结构的半导体元件，其源极/漏极区上方设有锗层，有利于获得优化的电性表现。
为达上述目的，本发明的一优选实施例提供一种形成半导体元件的方法，其包含以下步骤。首先，提供一基底，该基底上形成有一鳍状结构。接着，形成一栅极结构，该栅极结构横跨该鳍状结构。然后，在该鳍状结构内形成一外延层，该外延层邻接该栅极结构。之后，在该栅极结构及该鳍状结构上形成一层间介电层，并且，在该层间介电层内形成一第一开口，以暴露出该外延层。最后，再于该外延层上形成一锗层。
为达上述目的，本发明的一优选实施例提供一种半导体元件。该半导体元件包含一鳍状结构，一栅极结构，一外延层，一锗层，一层间介电层以及一第一插塞。该鳍状结构设置在一基底上。该栅极结构横跨该鳍状结构。该外延层设置在该鳍状结构内且邻接该栅极结构。该锗层设置在该外延层上。该层间介电层覆盖在该基底及该鳍状结构上。该第一插塞设置在该层间介电层内并接触该锗层。
本发明的半导体元件及其形成方法，其主要是在形成暴露出源极/漏极区的开口之后，随即在该源极/漏极区上进行选择性外延成长制作工艺，形成可完全覆盖该源极/漏极区的顶表面的一锗层。由此，在后续进行其他开口的蚀刻制作工艺中，该锗层可保护下方的源极/漏极区，避免直接暴露该源极/漏极区，而导致损伤。需注意的是，该锗层优选是具有适当的厚度，例如是约为30纳米至60纳米，使该锗层可位于不超过栅极结构约二分之一高度的位置，以避免影响后续元件的形成，如插塞结构等元件。
附图说明
图1至图11为本发明第一实施例中形成半导体元件的步骤示意图，其中，图1、图6及图9为半导体元件形成阶段的上视图，图2、图7及图10则分别为图1、图6及图9沿剖面线A-A’的剖面示意图；
图12为本发明第二实施例中形成半导体元件的步骤示意图。
主要元件符号说明
300 基底
301 鳍状结构
302 浅沟隔离
340 栅极结构
344 衬垫层
345 间隙壁
346 轻掺杂源极/漏极
347 外延层
347a 顶表面
348 栅极介电层
349 功函数金属层
350 金属层
351 盖层
352 锗层
353 锗盖层
360 凹槽
380 层间介电层
400 层间介电层
420 阻挡图案
440、480 开口
460 图案化牺牲掩模层
500、520 插塞结构
501、521 阻障层
502、522 接触金属层
t 厚度
具体实施方式
为使熟悉本发明所属技术领域的一般技术者能更进一步了解本发明，下文特列举本发明的数个优选实施例，并配合所附的附图，详细说明本发明的构成内容及所欲达成的功效。
请参照图1至图11，所绘示者为本发明第一优选实施例中形成半导体装置的制作工艺示意图，其中，图1、图6及图10为半导体元件形成阶段的上视图，图2、图7及图11则分别为图1、图6及图10沿剖面线A-A’的剖面示意图。半导体元件形成阶段的剖面示意图。首先，提供一基底300，例如一硅基底(silicon substrate)、外延硅(epitaxial siliconsubstrate)、硅锗半导体基底(silicon germanium substrate)、碳化硅基底(siliconcarbide substrate)或硅覆绝缘(silicon on insulation,SOI)基底，且基底300上形成有至少一鳍状结构301，以及横跨基底300的至少一栅极结构340。本实施例虽是以形成三根鳍状结构301为例，但其数量并不以此为限，可依据产品需求进行调整，例如可形成一根或一根以上的鳍状结构301于基底300上。
具体来说，鳍状结构301的形成方法一般可利用光刻暨蚀刻(photolithography-etching process,PEP)制作工艺或多重曝光(multi-patterning)等制作工艺，优选是利用间隙壁自对准双图案法(spacer self-aligned double-patterning,SADP)，也就是侧壁图案转移(sidewall image transfer，SIT)技术，以在基底300上形成多个浅沟槽(shallowtrench,未绘示)，并接着于该些浅沟槽中填入一绝缘层，形成浅沟隔离(shallow trenchisolation,STI)302，同时使得突出于该浅沟隔离的基底300形成鳍状结构301，如图1所示。然而，鳍状结构301的形成方法并不以前述制作工艺为限，在另一实施例中，鳍状结构301的形成方式也可选择先形成一图案化硬掩模层(未绘示)于基底300上，再利用一外延制作工艺于暴露于该图案化掩模层外的基底300上长出例如包含硅或硅锗等的半导体层(未绘示)，以作为相对应的鳍状结构。或者，在其他实施例中，也可省略该鳍状结构，直接在一平面(plannar)基底(未绘示)上形成栅极结构(未绘示)。
接着，在基底300上形成栅极结构340。在一实施例中，栅极结构340包含一栅极介电层(gate dielectric layer)341、一虚置栅极(dummy gate)342、一盖层(cappinglayer)343、一衬垫层(liner layer)344、一间隙壁(spacer)345以及一轻掺杂源极/漏极(LDD)346。其中，介质层341例如可包含氧化硅或氮化硅。虚置栅极342则可包含不具有任何掺质多晶硅(undoped polysilicon)材料、具有掺质的多晶硅材料、非晶硅材料，或者也可以是上述材料的组合。盖层343可具有一单层结构或一多层结构，如图2所示，例如可包含二氧化硅、氮化硅、碳化硅或氮氧化硅；衬垫层344包含氧化硅；间隙壁345可具有一单层结构或多层结构，例如是包含高温氧化硅层(high temperature oxide,HTO)、氮化硅、氧化硅或氮氧化硅或使用六氯二硅烷(hexachlorodisilane,Si2Cl6)形成的氮化硅(HCD-SiN)，但不以此为限。
具体来说，在一实施例中，栅极结构340的形成步骤，例如包含先在基底300上形成依序堆叠的一介电材料层(未绘示)、一虚置栅极材料层(未绘示)、一帽盖材料层(未绘示)后，再图案化这些堆叠层，进而形成一栅极堆叠结构(未绘示)。接着，在该栅极堆叠结构的侧壁形成衬垫层344，并在该栅极堆叠结构两侧的鳍状结构301内形成轻掺杂源极/漏极346，最后在衬垫层344的侧壁上形成间隙壁345。
接着，在栅极结构340两侧的鳍状结构301内形成邻接该栅极结构340的一外延层347，作为源极/漏极区。具体来说，例如是先进行一蚀刻制作工艺，例如是干蚀刻、湿蚀刻或依序进行干蚀刻及湿蚀刻，以在栅极结构340两侧的鳍状结构301中形成至少一凹槽(recess)360，如图3所示。接着，进行一选择性外延成长(selective epitaxial growth,SEG)制作工艺，以于凹槽360中形成外延层347，如第4图所示。
根据后续形成金属氧化物半导体(MOS)晶体管的类型不同，外延层347可以具有不同的材质。举例来说，若该金属氧化物半导体晶体管为一P型晶体管(PMOS)，外延层347可选择包含硅化锗(silicon germanium,SiGe)、硅化锗硼(silicon-germanium-boron,SiGeB)或硅化锗锡(silicon-germanium-tin,SiGeSn)，并且可以用同步(in-situ)选择性外延成长制作工艺进行P型离子掺杂，形成P+的硅锗外延层等，同时可省略后续该P型晶体管的源极/漏极注入步骤。另一方面，若该金属氧化物半导体晶体管为一N型晶体管(NMOS)时，则外延层347则可选择包含碳化硅(silicon carbide,SiC)、碳磷化硅(silicon carbide-phosphate,SiCP)或磷化硅(silicon phosphate,SiP)，且也可以用同步选择性外延成长制作工艺进行N型离子掺杂，形成N+的碳化硅外延层等，但不以此为限。此外，在一实施例中，可选择在形成外延层347之后或之前，再额外再进行一离子注入制作工艺以在外延层347中形成适当的掺质，形成该源极/漏极区；或是，在另一实施例中，也可选择以渐层的方式形成掺质或异质原子(例如锗原子或碳原子)等，或是直接省略外延层，直接于栅极结构340两侧的鳍状结构301或基底300内进行离子注入制作工艺，形成源极/漏极区(未绘示)。
然后，在基底300上形成一层间介电层380，并进行一金属栅极置换(replacementmetal gate,RMG)制作工艺，以将该栅极结构340的虚置栅极342转换为一金属栅极。具体来说，该金属栅极的形成方式例如包含先在基底300上全面性地形成一层间介电材料层(未绘示)，例如是一氧化硅层，以覆盖栅极结构340，通过一平坦化制作工艺，如化学机械研磨制作工艺、蚀刻制作工艺或两者的组合，部分移除该层间介电材料层至暴露栅极结构340，然后移除部分的衬垫层344、部分的间隙壁345以及盖层343，以形成层间介电层380。之后，再进行一选择性的干蚀刻或湿蚀刻制作工艺，去除虚置栅极342及介质层341，以形成一栅极沟槽(未绘示)。最后，依序于该栅极沟槽内填入一高介电常数(high dielectricconstant,high-k)层(未绘示)、一功函数金属材料层(未绘示)以及一低电阻值金属材料层(未绘示)，使其至少填入该栅极沟槽，再通过一化学机械研磨制作工艺移除该栅极沟槽外的上述材料层，形成一栅极介电层(未绘示)、一功函数金属层(未绘示)以及一金属层(未绘示)。最后再进行一回蚀刻制作工艺，移除一部分的该栅极介电层、该功函数金属层该以及该金属层，形成一栅极介电层348、一功函数金属层349以及一金属层350，如图5所示，并形成一盖层351。
然而，本发明中该金属栅极的形成方式并不以前述制作工艺为限，还可包含其他步骤。举例来说，在一实施例中，可选择在该高介电常数层与该功函数金属材料层之间进一步形成一底阻障材料层(未绘示)，例如是包含钽与氮化钽(Ta/TaN)或钛与氮化钛(Ti/TiN)等金属材质；或者是选择在该功函数金属材料层与该低电阻值金属材料层之间额外形成一顶阻障材料层(未绘示)，其大体上包含与该底阻障层相同的金属材质。该底阻障材料层及/或该顶阻障材料层可通过后续的化学机械研磨制作工艺而形成仅位于该栅极沟槽内的一底阻障层(未绘示)及/或一顶阻障层(未绘示)。
此外，在本发明的一实施例中，栅极介电层348例如是包含氧化铪(hafniumoxide，HfO2)、硅酸铪氧化合物(hafnium silicon oxide，HfSiO4)或硅酸铪氮氧化合物(hafnium silicon oxynitride，HfSiON)等高介电常数材料；而功函数金属层349优选用以调整形成金属栅极的功函数，其可视该金属氧化物半导体晶体管的类型而做调整。举例说明，若该金属氧化物晶体管为N型晶体管，功函数金属层349可选用功函数为3.9电子伏特(eV)～4.3eV的金属材料，如铝化钛(TiAl)、铝化锆(ZrAl)、铝化钨(WAl)、铝化钽(TaAl)、铝化铪(HfAl)或碳化钛铝(TiAlC)等，但不以此为限；若该金属氧化物晶体管为P型晶体管，功函数金属层349则可选用功函数为4.8eV～5.2eV的金属材料，如氮化钛(TiN)、氮化钽(TaN)或碳化钽(TaC)等，但不以此为限。金属层348则例如是包含铝(Al)、钛、钽或钨(W)等，但不以此为限。
然而，本领域通常知识者也应了解，栅极结构340的形成方式并不限于前述的制作工艺，也可能包含其他步骤。例如，在另一实施例中，还可选择在形成该层间介电材料层之前，先于基底300上形成单层或多层的一接触洞蚀刻停止层(contact etch stop layer,CESL,未绘示)，以进一步对栅极结构340的通道区施加所需的压缩应力或是伸张应力。再者，前述实施例中的栅极结构340虽是采用“后栅极(gate-last)制作工艺”并搭配“后高介电常数介电层(high-k last)制作工艺”为实施样态进行说明，但在其他实施例中，也可选择配合“前栅极(gate first)”、“前高介电常数层(high-k first)”或直接于该基底上形成一金属栅极结构(未绘示)，该金属栅极结构至少包含一功函数金属层(未绘示)及一金属栅极(未绘示)。或者，若原始栅极结构340已能符合产品需求，也可选择性省略此金属栅极置换步骤。
后续，进行接触孔蚀刻制作工艺。具体来说，先在层间介电层380上形成一层间介电层400，其可包含相同于层间介电层380的材质或是其他适合的介电材质。接着在层间介电层400以及层间介电层380中形成至少一开口440以暴露下方的外延层347(即该源极/漏极区)。该接触孔蚀刻制作工艺，例如是利用光刻蚀刻制作工艺，其包含先在介电层400上形成一阻挡图案(slot cut pattern)420，以及部分重叠阻挡图案420的一图案化光致抗蚀剂层(未绘示)，接着进行一蚀刻制作工艺，同时以阻挡图案420及该图案化光致抗蚀剂层为掩模，去除部分介电层400与栅极结构340两侧的层间介电层380，以形成多个开口440，如图6所示。值得说明的是，在本实施例中，阻挡图案420恰好是横跨在该图案化光致抗蚀剂层的开口图案的下方，并在一投影方向上与开口440部分重叠，因而可将开口440分隔成两部分，如图6所示。
再者，另需说明的是，本实施例的开口440优选具有较大的孔径，使得间隙壁345以及外延层347(亦即该源极/漏极区)的顶表面347a可被完全暴露，如图7所示。也就是说，开口440是由间隙壁345以及外延层347的顶表面347a共同定义而形成。随后，可选择进行一清洗制作工艺，去除开口440内经由前述光刻蚀刻制作工艺后所剩余的残留物。
后续，可再进行一选择性外延成长制作工艺，以在外延层347(亦即该源极/漏极区)的顶表面347a形成一锗层352。具体来说，锗层352是形成在外延层347(亦即该源极/漏极区)自开口440暴露出的所有表面上，即顶表面347a。需注意的是，锗层352优选是具有适当的厚度t，例如是约为30纳米至60纳米，由此，使锗层352可被形成在不超过栅极结构340的金属层350约二分之一高度的位置，如图8所示，避免影响后续元件的形成。
之后，进行另一接触孔制作工艺，在层间介电层400中形成一开口480，以暴露下方的栅极结构340。具体来说，先在基底300的层间介电层400上形成一图案化牺牲掩模层460并填满开口420，图案化牺牲掩模层460具有可定义开口480的图案，接着进行一蚀刻制作工艺，去除部分的层间介电层400以及栅极结构340的部分盖层351，以形成开口480，如图9所示。
最后，完全移除图案化牺牲掩模层460，并可选择性进行一清洗制作工艺，例如以氩气(Ar)对开口440、480的表面进行清洗，随即于开口440内选择性地进行金属硅化物(silicidation)制作工艺。之后，则可继续进行插塞制作工艺，以在开口440、480内分别形成直接电连接外延层347(即该源极/漏极区)及栅极结构340的插塞结构500、520。插塞结构500、520的形成方法，例如是先于开口520、580内依序形成一阻障材料层(未绘示)以及一金属材料层(未绘示)，并通过一平坦化制作工艺，如化学机械抛光制作工艺、蚀刻制作工艺或两者的组合，移除一部分的该金属材料层及该阻障材料层，以同时形成插塞结构500、520。因此，插塞结构500、520可与层间介电层400的顶表面齐平，并分别包含一阻障层(barrierlayer)501、521以及一接触金属层(contact metal layer)502、522，如图11所示。其中，插塞结构500可直接且完全接触栅极结构340的间隙壁345。在本发明的一实施例中，阻障层501、521例如是钛层、氮化钛层、钽层或氧化钽层，而接触金属层502、522例如是钨或其他低电阻的金属，但不以此为限。
由此，即可完成本发明一实施例中提供的半导体元件。本发明主要是在形成暴露出源极/漏极区的开口之后，随即在该源极/漏极区上进行选择性外延成长制作工艺，形成可完全覆盖该源极/漏极区的顶表面的一锗层。由此，在后续进行其他开口的蚀刻制作工艺中，可避免直接暴露该源极/漏极区，而导致损伤。需注意的是，该锗层优选是具有适当的厚度，例如是约为30纳米至60纳米，使该锗层可位于不超过栅极结构约二分之一高度的位置，以适当地保护下方的该源极/漏极区，同时避免影响后续元件的形成，如插塞结构等元件。
然而，本领域者应可轻易了解，本发明的半导体元件也可能以其他方式形成，并不限于前述的制作步骤。是以，下文将进一步针对本发明半导体元件及其形成方法的其他实施例或变化型进行说明。且为简化说明，以下说明主要针对各实施例不同之处进行详述，而不再对相同之处作重复赘述。此外，本发明的各实施例中相同的元件以相同的标号进行标示，以利于各实施例间互相对照。
请参照图12所示，其绘示本发明第二实施例中形成半导体元件的方法的步骤示意图。本实施例的半导体元件的形成方法大体上和前述第一实施例相同，是依序在基底300上形成鳍状结构301、栅极结构340、外延层347(即该源极/漏极区)及开口420等。并且，本领域者应可清楚理解，在本实施例中鳍状结构301、栅极结构340、外延层347及开口420等元件的具体形成方式及详细材质大体上与前述第一实施例相同，或者应为本领域者所熟知，在此不再赘述。
本实施例与前述第一实施例的差异处在于形成如前述第一实施例的图7所示结构后，先进行一离子注入制作工艺，例如是一预非晶化离子注入(pre-amorphousimplantation,PAI)制作工艺，以在外延层347(亦即该源极/漏极区)的至少一部分注入适当掺质，例如是锗离子。也就是说，本实施例是在形成锗层352之前，进行该离子注入制作工艺，以在外延层347(亦即该源极/漏极区)的至少一部分，优选是在外延层347(亦即该源极/漏极区)的至少上半部或是全部内，形成一锗盖层(germanium cap layer)353，然后再形成锗层352，如图12所示。意即，在锗层352下方再形成锗盖层353，以进一步保护外延层347(亦即该源极/漏极区)，避免外延层347于后续制作工艺中，如插塞制作工艺等，受到损伤。此外，在一实施例中，该掺质也可以选择以渐层的方式形成。
后续，则可继续进行如前述第一实施例的图8至图11所示制作工艺，即可完成本发明第三实施例的半导体元件，如图12所示。本实施例是该锗层形成之前，额外进行赭离子注入制作工艺，以在该锗层下方另形成一锗盖层，以进一步保护该源极/漏极区，避免后续进行其他开口的蚀刻制作工艺中，使该源极/漏极区直接暴露而受损伤。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (20)

1.一种形成半导体元件的方法，其特征在于包含以下步骤：
提供一基底，该基底上形成有一鳍状结构；
形成一栅极结构，该栅极结构横跨该鳍状结构；
在该鳍状结构内形成一外延层，该外延层邻接该栅极结构；
在该栅极结构及该鳍状结构上形成一层间介电层；
在该层间介电层内形成一第一开口，以暴露出该外延层；以及
在该外延层上形成一锗层。
2.如权利要求1所述的形成半导体元件的方法，其特征在于，该锗层完全覆盖该外延层的顶表面。
3.如权利要求1所述的形成半导体元件的方法，其特征在于，还包含：
在该锗层形成之前进行一离子注入步骤。
4.如权利要求3所述的形成半导体元件的方法，其特征在于，该离子注入步骤包含注入锗离子。
5.如权利要求1所述的形成半导体元件的方法，其特征在于，还包含：
形成一第二开口，以暴露出该栅极结构。
6.如权利要求5所述的形成半导体元件的方法，其特征在于，还包含：
在该第一开口内形成一第一插塞，以接触该锗层；以及
在该第二开口内形成一第二插塞，以接触该栅极结构。
7.如权利要求6所述的形成半导体元件的方法，其特征在于，还包含：
形成一间隙壁，该间隙壁环绕该栅极结构，其中该第一开口还暴露出该间隙壁。
8.如权利要求7所述的形成半导体元件的方法，其特征在于，该第一插塞直接接触该间隙壁。
9.如权利要求5所述的形成半导体元件的方法，其特征在于，该第二开口是形成于该第一开口形成之后。
10.如权利要求1所述的形成半导体元件的方法，其特征在于，还包含：
在该层间介电层上形成一阻挡图案。
11.如权利要求1所述的形成半导体元件的方法，其特征在于，该阻挡图案在一投影方向上与该第一开口部分重叠。
12.如权利要求1所述的形成半导体元件的方法，其特征在于，还包含：
在该基底形成一浅沟隔离，该浅沟隔离环绕该鳍状结构。
13.一种半导体元件，其特征在于包含：
鳍状结构，设置在一基底上；
栅极结构，横跨该鳍状结构；
外延层，设置在该鳍状结构内且邻接该栅极结构；
锗层，设置在该外延层上；
层间介电层，覆盖在该基底及该鳍状结构上；以及
第一插塞，设置在该层间介电层内并接触该锗层。
14.如权利要求13所述的半导体元件，其特征在于，该锗层完全覆盖该外延层的顶表面。
15.如权利要求13所述的半导体元件，其特征在于，该外延层包含碳化硅、磷化硅、碳磷化硅、硅化锗或锗。
16.如权利要求13所述的半导体元件，其特征在于，该锗层具有一厚度，该厚度约为30纳米至60纳米。
17.如权利要求13所述的半导体元件，其特征在于，还包含：
锗盖层，设置于该锗层下方。
18.如权利要求13所述的半导体元件，其特征在于，还包含：
第二插塞，设置在该层间介电层内并接触该栅极结构。
19.如权利要求13所述的半导体元件，其特征在于，还包含：
一间隙壁，环绕该栅极结构，其中该第一插塞直接接触该间隙壁。
20.如权利要求13所述的半导体元件，其特征在于，还包含：
浅沟隔离，设置于该基底且环绕该鳍状结构。
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