TW201822263A - 半導體元件及其製作方法 - Google Patents

半導體元件及其製作方法 Download PDF

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Publication number
TW201822263A
TW201822263A TW105141215A TW105141215A TW201822263A TW 201822263 A TW201822263 A TW 201822263A TW 105141215 A TW105141215 A TW 105141215A TW 105141215 A TW105141215 A TW 105141215A TW 201822263 A TW201822263 A TW 201822263A
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Taiwan
Prior art keywords
layer
recess
contact hole
forming
etch stop
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TW105141215A
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English (en)
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TWI722073B (zh
Inventor
劉安淇
林俊賢
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聯華電子股份有限公司
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Priority to TW105141215A priority Critical patent/TWI722073B/zh
Priority to US15/401,092 priority patent/US9899522B1/en
Priority to US15/861,700 priority patent/US10069009B2/en
Publication of TW201822263A publication Critical patent/TW201822263A/zh
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Publication of TWI722073B publication Critical patent/TWI722073B/zh

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    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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Abstract

本發明揭露一種製作半導體元件的方法。首先形成一閘極結構於一基底上，然後形成一第一凹槽於閘極結構兩側，形成一磊晶層於第一凹槽內，去除部分磊晶層以形成一第二凹槽以及形成一層間介電層於第二凹槽內以及閘極結構上。

Description

半導體元件及其製作方法
本發明是關於一種製作半導體元件的方法，尤指一種於磊晶層中形成凹槽的方法。
為了能增加半導體結構的載子遷移率，可以選擇對於閘極通道施加壓縮應力或是伸張應力。舉例來說，若需要施加的是壓縮應力，習知技術常利用選擇性磊晶成長(selective epitaxial growth, SEG)技術於一矽基底內形成晶格排列與該矽基底相同之磊晶結構，例如矽鍺(silicon germanium, SiGe)磊晶結構。利用矽鍺磊晶結構之晶格常數(lattice constant)大於該矽基底晶格之特點，對P型金氧半導體電晶體的通道區產生應力，增加通道區的載子遷移率(carrier mobility)，並藉以增加金氧半導體電晶體的速度。反之，若是N型半導體電晶體則可選擇於矽基底內形成矽碳(silicon carbide, SiC)磊晶結構，對閘極通道區產生伸張應力。
然而，現今以磊晶成長方式形成磊晶層的過程中對阻值的平衡以及抑制短通道效應(short channel effect, SCE)等方面仍不盡理想。因此，如何改良現有製程技術以解決現有瓶頸即為現今一重要課題。
本發明較佳實施例揭露一種製作半導體元件的方法。首先形成一閘極結構於一基底上，形成一第一凹槽於閘極結構兩側，形成一磊晶層於第一凹槽內，去除部分磊晶層以形成一第二凹槽，之後再形成一層間介電層於第二凹槽內以及閘極結構上。
本發明又一實施例揭露一種半導體元件，其包含：一基底；一閘極結構設於基底上；一第一凹槽設於閘極結構兩側；一磊晶層設於第一凹槽內以及一接觸洞蝕刻停止層設於磊晶層上以及第一凹槽內。
請參照第1圖至第8圖，第1圖至第8圖為本發明一較佳實施例製作一半導體元件之方法示意圖。如第1圖所示，首先提供一基底12，例如一矽基底或矽覆絕緣(SOI)基板。基底12上可定義有一電晶體區，例如一PMOS電晶體區或一NMOS電晶體區，而基底12中可設有例如由氧化矽所構成的淺溝隔離(shallow trench isolation, STI)隔開電晶體區。
需注意的是，本實施例雖以製作平面型(planar)場效電晶體為例，但不侷限於此，本發明又可應用至一般非平面型場效電晶體(non-planar)鰭狀結構場效電晶體，例如可於基底12上形成至少一鰭狀結構，而鰭狀結構的底部則較佳被淺溝隔離所圍繞，此實施例也屬本發明所涵蓋的範圍。
依據本發明一實施例，鰭狀結構較佳透過側壁圖案轉移(sidewall image transfer, SIT)技術製得，其程序大致包括：提供一佈局圖案至電腦系統，並經過適當地運算以將相對應之圖案定義於光罩中。後續可透過光微影及蝕刻製程，以形成多個等距且等寬之圖案化犧牲層於基底上，使其個別外觀呈現條狀。之後依序施行沉積及蝕刻製程，以於圖案化犧牲層之各側壁形成側壁子。繼以去除圖案化犧牲層，並在側壁子的覆蓋下施行蝕刻製程，使得側壁子所構成之圖案被轉移至基底內，再伴隨鰭狀結構切割製程(fin cut)而獲得所需的圖案化結構，例如條狀圖案化鰭狀結構。
除此之外，鰭狀結構之形成方式又可包含先形成一圖案化遮罩(圖未示)於基底12上，再經過一蝕刻製程，將圖案化遮罩之圖案轉移至基底12中以形成鰭狀結構。另外，鰭狀結構之形成方式也可以先形成一圖案化硬遮罩層(圖未示)於基底12上，並利用磊晶製程於暴露出於圖案化硬遮罩層之基底12上成長出例如包含矽鍺的半導體層，而此半導體層即可作為相對應的鰭狀結構。這些形成鰭狀結構的實施例均屬本發明所涵蓋的範圍。
接著可於基底12上形成複數個閘極結構，例如閘極結構14、16、18或虛置閘極。在本實施例中，閘極結構14、16、18之製作方式可依據製程需求以先閘極(gate first)製程、後閘極(gate last)製程之先高介電常數介電層(high-k first)製程以及後閘極製程之後高介電常數介電層(high-k last)製程等方式製作完成。以本實施例之後高介電常數介電層製程為例，可先依序形成一閘極介電層或介質層、一閘極材料層以及一選擇性硬遮罩於基底12上，並利用一圖案化光阻(圖未示)當作遮罩進行一圖案轉移製程，以單次蝕刻或逐次蝕刻步驟，去除部分閘極材料層與部分閘極介電層，然後剝除圖案化光阻，以於基底12上形成由圖案化之閘極介電層20與圖案化之閘極材料層22所構成的閘極結構14、16、18。
然後在各閘極結構14、16、18側壁形成至少一側壁子24，並於側壁子24兩側的基底12中形成一輕摻雜汲極26。在本實施例中，側壁子24可為單一側壁子或複合式側壁子，例如可細部包含一偏位側壁子28以及一主側壁子30。其中偏位側壁子28與主側壁子30可包含相同或不同材料，且兩者均可選自由氧化矽、氮化矽、氮氧化矽以及氮碳化矽所構成的群組。輕摻雜汲極26可依據所置備電晶體的導電型式而包含不同摻質，例如可包含P型摻質或N型摻質。
接著如第2圖所示，進行一蝕刻製程以於側壁子24兩側的基底12中形成第一凹槽32。舉例來說，該蝕刻製程可包含先進行一乾蝕刻步驟以在閘極結構16兩側的基底12中預先形成一初始溝槽(未繪示)，再接著進行一濕蝕刻製程，等向性地加大初始溝槽以形成第一凹槽32。在本發明一實施例中，濕蝕刻製程可選擇使用例如氫氧化銨(ammonium hydroxide, NH4 OH)或氫氧化四甲基銨(tetramethylammonium hydroxide, TMAH)等蝕刻液體。值得注意的是，形成第一凹槽32的方式不限於前述乾蝕刻搭配濕蝕刻的方式，亦可以透過單次或多次的乾蝕刻及/或濕蝕刻的方式來形成。例如於一實施例中，第一凹槽32可具有不同的截面形狀，例如是圓弧、六邊形(hexagon；又稱sigma Σ)或八邊形(octagon)等截面形狀，本實施例是以六邊形的截面形狀為實施樣態說明，但並不以此為限。
隨後如第3圖所示，進行一選擇性磊晶成長(selective epitaxial growth, SEG)製程，以於第一凹槽32中形成一磊晶層34，如第3圖所示。在本實施例中，磊晶層34的一頂表面較佳與基底12一頂表面齊平，且較佳與第一凹槽32具有相同的截面形狀，如圓弧、六邊形(hexagon；又稱sigma Σ)或八邊形(octagon)之截面形狀，但也可以是其他截面形狀。於本發明較佳實施例中，磊晶層34根據不同之金氧半導體(MOS)電晶體類型而可以具有不同的材質，舉例來說，若該金氧半導體電晶體為一P型電晶體(PMOS)時，磊晶層34可選擇包含矽化鍺(SiGe)、矽化鍺硼(SiGeB)或矽化鍺錫(SiGeSn)。而於本發明另一實施例中，若該金氧半導體電晶體為一N型電晶體(NMOS)時，磊晶層34可選擇包含碳化矽(SiC)、碳磷化矽(SiCP)或磷化矽(SiP)。此外，選擇性磊晶製程可以用單層或多層的方式來形成，且其異質原子(例如鍺原子或碳原子)亦可以漸層的方式改變，但較佳是使磊晶層34的表面較淡或者無鍺原子，以利後續金屬矽化物層的形成。另一方面，本實施例雖是以頂表面與基底12頂表面齊平的磊晶層34為實施樣態說明，但在本發明的其他實施例中，亦可選擇使磊晶層34進一步向上延伸至高於基底12頂表面。
後續進行一離子佈植製程，以在磊晶層34的一部分或全部形成一源極/汲極區域36。在另一實施例中，源極/汲極區域36的形成亦可同步(in-situ)於選擇性磊晶成長製程進行，例如金氧半導體是PMOS時，形成矽化鍺磊晶層、矽化鍺硼磊晶層或矽化鍺錫磊晶層，可以伴隨著注入P型摻質；或是當金氧半導體是NMOS時，形成矽化碳磊晶層、矽化碳磷磊晶層或矽化磷磊晶層，可以伴隨著注入N型摻質。藉此可省略後續利用額外離子佈植步驟形成P型/N型電晶體之源極/汲極區域。此外在另一實施例中，源極/汲極區域36的摻質亦可以漸層的方式形成。
然後如第4圖所示，先形成一圖案化遮罩(圖未示)，例如圖案化光阻層覆蓋閘極結構14、16、18與部分磊晶層34上，接著利用圖案化遮罩為遮罩以蝕刻方式去除部分磊晶層34，以於磊晶層34中形成第二凹槽38，隨後再去除圖案化遮罩。在本實施例中，此階段所進行的蝕刻製程可利用乾蝕刻的方式來去除部分磊晶層34而於磊晶層34中所形成的第二凹槽38則較佳為約略矩形的凹槽。
接著如第5圖所示，先形成一接觸洞蝕刻停止層40於第二凹槽38內並覆蓋基底12表面與閘極結構14、16、18，再形成一層間介電層42於接觸洞蝕刻停止層40上。然後進行一平坦化製程，例如利用化學機械研磨(chemical mechanical polishing, CMP)去除部分層間介電層42與部分接觸洞蝕刻停止層40並暴露出由多晶矽材料所構成的閘極材料層22，使各閘極材料層22上表面與層間介電層42上表面齊平。
如第6圖所示，隨後進行一金屬閘極置換製程將閘極結構14、16、18轉換為金屬閘極。舉例來說，可先進行一選擇性之乾蝕刻或濕蝕刻製程，例如利用氨水(ammonium hydroxide, NH4 OH)或氫氧化四甲銨(Tetramethylammonium Hydroxide, TMAH)等蝕刻溶液來去除閘極結構14、16、18中的閘極材料層22甚至閘極介電層20，以於層間介電層42中形成凹槽(圖未示)。之後依序形成一選擇性介質層或閘極介電層(圖未示)、一高介電常數介電層44、一功函數金屬層46以及一低阻抗金屬層48於各凹槽內，然後進行一平坦化製程，例如利用CMP去除部分低阻抗金屬層48、部分功函數金屬層46與部分高介電常數介電層44以形成金屬閘極。以本實施例利用後高介電常數介電層製程所製作的閘極結構為例，各閘極結構14、16、18較佳包含一介質層或閘極介電層(圖未示)、一U型高介電常數介電層44、一U型功函數金屬層46以及一低阻抗金屬層48。
在本實施例中，高介電常數介電層44包含介電常數大於4的介電材料，例如選自氧化鉿(hafnium oxide，HfO2 )、矽酸鉿氧化合物(hafnium silicon oxide, HfSiO4 )、矽酸鉿氮氧化合物(hafnium silicon oxynitride, HfSiON)、氧化鋁(aluminum oxide, Al2 O3 )、氧化鑭(lanthanum oxide, La2 O3 )、氧化鉭(tantalum oxide, Ta2 O5 )、氧化釔(yttrium oxide, Y2 O3 )、氧化鋯(zirconium oxide, ZrO2 )、鈦酸鍶（strontium titanate oxide, SrTiO3 ）、矽酸鋯氧化合物(zirconium silicon oxide, ZrSiO4 )、鋯酸鉿(hafnium zirconium oxide, HfZrO4 )、鍶鉍鉭氧化物(strontium bismuth tantalate, SrBi2 Ta2 O9 , SBT)、鋯鈦酸鉛(lead zirconate titanate, PbZrx Ti1-x O3 , PZT)、鈦酸鋇鍶(barium strontium titanate, Bax Sr1-x TiO3 , BST)、或其組合所組成之群組。
功函數金屬層46較佳用以調整形成金屬閘極之功函數，使其適用於N型電晶體(NMOS)或P型電晶體(PMOS)。若電晶體為N型電晶體，功函數金屬層46可選用功函數為3.9電子伏特(eV)～4.3 eV的金屬材料，如鋁化鈦(TiAl)、鋁化鋯(ZrAl)、鋁化鎢(WAl)、鋁化鉭(TaAl)、鋁化鉿(HfAl)或TiAlC (碳化鈦鋁)等，但不以此為限；若電晶體為P型電晶體，功函數金屬層46可選用功函數為4.8 eV～5.2 eV的金屬材料，如氮化鈦(TiN)、氮化鉭(TaN)或碳化鉭(TaC)等，但不以此為限。功函數金屬層46與低阻抗金屬層48之間可包含另一阻障層(圖未示)，其中阻障層的材料可包含鈦(Ti)、氮化鈦(TiN)、鉭(Ta)、氮化鉭(TaN)等材料。低阻抗金屬層48則可選自銅(Cu)、鋁(Al)、鎢(W)、鈦鋁合金(TiAl)、鈷鎢磷化物(cobalt tungsten phosphide，CoWP)等低電阻材料或其組合。
接著去除部分高介電常數介電層44、部分功函數金屬層46與部分低阻抗金屬層48形成凹槽(圖未示)，然後再填入硬遮罩50於凹槽內並使硬遮罩50與層間介電層42表面齊平，其中硬遮罩50可選自由氧化矽、氮化矽、氮氧化矽以及氮碳化矽所構成的群組。
如第7圖所示，先全面形成一介電層52於層間介電層42上並覆蓋閘極結構14、16、18，然後利用一圖案化遮罩(圖未示)，例如圖案化光阻為遮罩去除閘極結構16兩側的部分介電層52與部分層間介電層42以形成接觸洞54暴露出磊晶層34上的接觸洞蝕刻停止層40，並同時去除閘極結構16正上方的部分介電層52形成接觸洞56暴露出硬遮罩50表面。在本實施例中，介電層52可包含氧化物，例如四乙氧基矽烷(Tetraethyl orthosilicate, TEOS)，但不侷限於此。
之後如第8圖所示，先以蝕刻方式同時去除位於磊晶層34正上方的部分接觸洞蝕刻停止層40與閘極結構16正上方的部分硬遮罩50，再進行一接觸插塞製程搭配金屬矽化物製程形成一金屬矽化物58於接觸洞54中，並分別形成接觸插塞60電連接並接觸閘極結構16與接觸插塞62電連接並接觸閘極結構16兩側的磊晶層34或源極/汲極區域36。在本實施例中，接觸插塞製程可依序沉積一第一應力層64與阻隔層66於接觸洞54、56中，其中第一應力層64與阻隔層66較佳共形地(conformally)形成於磊晶層34表面及接觸洞54、56的內側側壁。在本實施例中，第一應力層64較佳包含具有應力之金屬材料，例如可選自鈦、鈷、鎳及鉑等所構成的群組，且最佳為鈦，阻隔層66則較佳包含氮化鈦、氮化鉭等金屬化合物。
在連續沉積第一應力層64與阻隔層66之後，依序進行一第一熱處理製程與一第二熱處理製程以形成金屬矽化物58於磊晶層34表面。在本實施例中，第一熱處理製程包含一常溫退火(soak anneal)製程，其溫度較佳介於500℃至600℃，且最佳為550℃，而其處理時間則較佳介於10秒至60秒，且最佳為30秒。第二熱處理製程包含一峰值退火(spike anneal)製程，其溫度較佳介於600℃至950℃，且最佳為600℃，而其處理較佳時間則較佳介於100毫秒至5秒，且最佳為5秒。
迨進行兩次熱處理製程後，形成一第二應力層68並填滿接觸洞54、56。在本實施例中，第二應力層68較佳包含具有應力之金屬材料，例如鎢，但不侷限於此。最後進行一平坦化製程，例如以CMP製程部分去除第二應力層68、部分阻隔層66及部分第一應力層64，甚至可視製程需求接著去除部分介電層52，以形成接觸插塞60、62電連接閘極結構16與源極/汲極區域36。至此即完成本發明較佳實施例一半導體元件的製作。
需注意的是，本實施例所揭露之第一應力層64與第二應力層68雖各別為單層結構，但依據本發明一實施例，第一應力層64與第二應力層68又可分別由兩層以上之多層結構所組成。例如原本第一應力層64可由一金屬層與具有應力之第一應力層一同構成，其中金屬層與第一應力層可包含相同材料且均可選自由鈦、鈷、鎳及鉑等所構成的群組，但金屬層並不具任何應力而僅有第一應力層具有應力。同樣地，第二應力層68可由一金屬層與具有應力之第二應力層一同構成，其中金屬層與第二應力層可包含相同材料且均可包含鎢，但金屬層並不具任何應力而僅有第二應力層具有應力。這些實施例均屬本發明所涵蓋的範圍。
請再參照第8圖，其另揭露本發明較佳實施例一半導體元件之結構示意圖。如第8圖所示，半導體元件主要包含至少一閘極結構16設於基底12上、一第一凹槽32設於閘極結構16兩側、一磊晶層34設於第一凹槽32內、一第二凹槽38設於磊晶層34內、一接觸洞蝕刻停止層40設於第二凹槽38內、一層間介電層42設於接觸洞蝕刻停止層40上以及接觸插塞62設於閘極結構16兩側的層間介電層42中並向下延伸至第二凹槽38與第一凹槽32內。
更具體而言，接觸洞蝕刻停止層40較佳直接接觸第一凹槽32內的磊晶層34，接觸插塞62直接接觸該接觸洞蝕刻停止層40及第一凹槽32內之磊晶層34，或層另一角度來看接觸插塞62較佳同時直接接觸高於基底12表面之接觸洞蝕刻停止層40與低於基底12表面之接觸洞蝕刻停止層40。
請再參照第9圖，第9圖為本發明一實施例之一半導體元件之結構示意圖。如第9圖所示，本發明可於第4圖於磊晶層34中形成第二凹槽38後再進行一橫向蝕刻製程，例如可以濕蝕刻方式等向性擴大第二凹槽38，使原本約為矩形的第二凹槽改變為六邊形，甚至是圓弧狀或八邊形等其他截面形狀，其中本實施例是以六邊形的截面形狀為實施樣態說明，但並不以此為限。在本發明一實施例中，濕蝕刻製程可選擇使用例如氫氧化銨(ammonium hydroxide, NH4 OH)或氫氧化四甲基銨(tetramethylammonium hydroxide, TMAH)等蝕刻液體。之後可比照第5圖至第8圖的製程形成金屬矽化物58、接觸插塞60以及接觸插塞62等元件。
請再參照第10圖，第10圖為本發明一實施例之一半導體元件之結構示意圖。如第10圖所示，本發明可於第3圖形成磊晶層34之後於側壁子24側壁再額外形成一側壁子70，並利用側壁子70為遮罩形成如第4圖的第二凹槽38。如同前述側壁子24之材料，側壁子70同樣可選自由氧化矽、氮化矽、氮氧化矽以及氮碳化矽所構成的群組。之後再比照第5圖至第8圖的製程形成接觸洞蝕刻停止層40、層間介電層42，金屬矽化物58、接觸插塞60以及接觸插塞62等元件。相較於前述實施例，本實施例中第二凹槽38邊緣較佳切齊側壁子70邊緣，而層間介電層42則可於接觸插塞製程時被完全去除，使基底12表面以上的接觸洞蝕刻停止層40可直接接觸接觸插塞62，此實施例也屬本發明所涵蓋的範圍。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
12‧‧‧基底
14‧‧‧閘極結構
16‧‧‧閘極結構
18‧‧‧閘極結構
20‧‧‧閘極介電層
22‧‧‧閘極材料層
24‧‧‧側壁子
26‧‧‧輕摻雜汲極
28‧‧‧偏位側壁子
30‧‧‧主側壁子
32‧‧‧第一凹槽
34‧‧‧磊晶層
36‧‧‧源極/汲極區域
38‧‧‧第二凹槽
40‧‧‧接觸洞蝕刻停止層
42‧‧‧層間介電層
44‧‧‧高介電常數介電層
46‧‧‧功函數金屬層
48‧‧‧低阻抗金屬層
50‧‧‧硬遮罩
52‧‧‧介電層
54‧‧‧接觸洞
56‧‧‧接觸洞
58‧‧‧金屬矽化物
60‧‧‧接觸插塞
62‧‧‧接觸插塞
64‧‧‧第一應力層
66‧‧‧阻隔層
68‧‧‧第二應力層
70‧‧‧側壁子
第1圖至第8圖為本發明一較佳實施例製作一半導體元件之方法示意圖。 第9圖為本發明一實施例之一半導體元件之結構示意圖。 第10圖為本發明一實施例之一半導體元件之結構示意圖。

Claims (17)

  1. 一種製作半導體元件的方法，包含： 形成一閘極結構於一基底上； 形成一第一凹槽於該閘極結構兩側； 形成一磊晶層於該第一凹槽內； 去除部分該磊晶層以形成一第二凹槽；以及 形成一層間介電層於該第二凹槽內以及該閘極結構上。
  2. 如申請專利範圍第1項所述之方法，另包含： 形成一側壁子於該閘極結構旁； 形成該第一凹槽於該側壁子旁； 形成該磊晶層； 形成該第二凹槽於該磊晶層內； 形成一接觸洞蝕刻停止層於該第二凹槽內以及該閘極結構上； 形成該層間介電層於該接觸洞蝕刻停止層上； 平坦化部分該層間介電層；以及 將該閘極結構轉換為一金屬閘極。
  3. 如申請專利範圍第2項所述之方法，另包含： 形成一硬遮罩於該金屬閘極上； 去除部分該層間介電層以形成一第一接觸洞於該磊晶層上； 去除部分該層間介電層以形成一第二接觸洞於該硬遮罩上；以及 同時去除部分該接觸洞蝕刻停止層以及部分該硬遮罩。
  4. 如申請專利範圍第3項所述之方法，另包含： 形成一第一應力層於該第一接觸洞及該第二接觸洞內； 形成一第二應力層於該第一接觸洞及該第二接觸洞內； 平坦化部分該第一應力層及部分該第二應力層以形成一第一接觸插塞及一第二接觸插塞。
  5. 如申請專利範圍第4項所述之方法，其中該第一應力層包含鈦。
  6. 如申請專利範圍第4項所述之方法，其中該第二應力層包含鎢。
  7. 如申請專利範圍第1項所述之方法，另包含： 進行一第一蝕刻製程以形成該第一凹槽； 形成該磊晶層於該第一凹槽內；以及 進行一第二蝕刻製程以形成該第二凹槽。
  8. 如申請專利範圍第7項所述之方法，其中該第二蝕刻製程包含一橫向蝕刻製程。
  9. 如申請專利範圍第1項所述之方法，其中該第一凹槽包含一六角形。
  10. 如申請專利範圍第1項所述之方法，其中該第二凹槽包含一六角形或矩形。
  11. 一種半導體元件，包含： 一基底； 一閘極結構設於該基底上； 一第一凹槽設於該閘極結構兩側； 一磊晶層設於該第一凹槽內；以及 一接觸洞蝕刻停止層設於該磊晶層上以及該第一凹槽內。
  12. 如申請專利範圍第11項所述之半導體元件，另包含： 一第二凹槽設於該磊晶層內；以及 該接觸洞蝕刻停止層設於該第二凹槽內。
  13. 如申請專利範圍第11項所述之半導體元件，其中該接觸洞蝕刻停止層接觸該第一凹槽內之該磊晶層。
  14. 如申請專利範圍第11項所述之半導體元件，另包含一層間介電層設於該接觸洞蝕刻停止層上。
  15. 如申請專利範圍第14項所述之半導體元件，另包含一接觸插塞設於該層間介電層及該第一凹槽內。
  16. 如申請專利範圍第15項所述之半導體元件，其中該接觸插塞直接接觸該接觸洞蝕刻停止層及該第一凹槽內之該磊晶層。
  17. 如申請專利範圍第15項所述之半導體元件，其中該接觸插塞直接接觸高於該基底表面之該接觸洞蝕刻停止層以及低於該基底表面之該接觸洞蝕刻停止層。
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