TWI620234B - 一種製作半導體元件的方法 - Google Patents

一種製作半導體元件的方法 Download PDF

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TWI620234B
TWI620234B TW103123508A TW103123508A TWI620234B TW I620234 B TWI620234 B TW I620234B TW 103123508 A TW103123508 A TW 103123508A TW 103123508 A TW103123508 A TW 103123508A TW I620234 B TWI620234 B TW I620234B
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metal
layer
metal layer
heat treatment
substrate
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TW201603126A (zh
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洪慶文
吳家榮
張宗宏
林靜齡
李怡慧
黃志森
陳意維
林俊賢
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聯華電子股份有限公司
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Priority to TW103123508A priority Critical patent/TWI620234B/zh
Priority to CN202110417853.5A priority patent/CN113284892B/zh
Priority to CN201410379206.XA priority patent/CN105321810B/zh
Priority to US14/455,939 priority patent/US9324610B2/en
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Abstract

本發明是揭露一種製作半導體元件的方法。首先提供一基底，該基底包含至少一金屬閘極設於其上、一源極/汲極區域設於金屬閘極兩側的基底中以及一層間介電層環繞金屬閘極。然後形成複數個接觸洞於層間介電層中並暴露出源極/汲極區域，形成一第一金屬層於接觸洞內，進行一第一熱處理製程，並接著進行一第二熱處理製程。

Description

一種製作半導體元件的方法
本發明是關於一種製作半導體元件的方法，尤指一種於形成接觸洞後以兩次熱處理製程形成金屬矽化物的方法。
在半導體積體電路的製程中，金氧半導體(metal-oxide-semiconductor,MOS)電晶體是一種極重要的電子元件，而隨著半導體元件的尺寸越來越小，MOS電晶體的製程步驟也有許多的改進，以製造出體積小而高品質的MOS電晶體。
習知的MOS電晶體製程是在半導體基底上形成閘極結構之後，再於閘極結構相對兩側的基底中形成輕摻雜汲極結構(lightly doped drain,LDD)。接著於閘極結構側邊形成側壁子(spacer)，並以此閘極結構及側壁子做為遮罩，再進行離子植入步驟，以於半導體基底中形成源極/汲極區域。而為了要將電晶體的閘極與源極/汲極區域適當電連接於電路中，因此需要形成接觸插塞(contact plug)來進行導通。通常接觸插塞的材質為鎢(W)、鋁、銅等金屬導體，然其與閘極結構、源極/汲極區域等多晶或單晶矽等材質之間的直接導通並不理想；因此為了改善金屬插塞與閘極結構、源極/汲極區之間的歐米接觸(Ohmi contact)，通常會在閘極結構與源極/汲極區域的表面再形成一金屬矽化物(silicide)。
然而，現階段之金屬矽化物製程仍有許多待改進的缺點，因此如何改良現行製程以提升MOS電晶體的效能即為現今一重要課題。
本發明是揭露一種製作半導體元件的方法。首先提供一基底，該基底包含至少一金屬閘極設於其上、一源極/汲極區域設於金屬閘極兩側的基底中以及一層間介電層環繞金屬閘極。然後形成複數個接觸洞於層間介電層中並暴露出源極/汲極區域，形成一第一金屬層於接觸洞內，進行一第一熱處理製程，並接著進行一第二熱處理製程。
本發明另一實施例是揭露一種半導體元件，包含一基底、一金屬閘極設於基底上、一源極/汲極區域設於鄰近金屬閘極之基底中、一層間介電層設於基底上並圍繞金屬閘極、複數個接觸插塞電連接源極/汲極區域以及一金屬矽化物設於接觸插塞及該源極/汲極區域之間，其中金屬矽化物包含一C54相位之結構。
12‧‧‧基底
14‧‧‧鰭狀結構
16‧‧‧絕緣層
18‧‧‧金屬閘極
20‧‧‧金屬閘極
22‧‧‧金屬閘極
24‧‧‧側壁子
26‧‧‧源極/汲極區域
28‧‧‧磊晶層
30‧‧‧接觸洞蝕刻停止層
32‧‧‧層間介電層
34‧‧‧功函數金屬層
36‧‧‧低阻抗金屬層
38‧‧‧硬遮罩
40‧‧‧介電層
42‧‧‧接觸洞
44‧‧‧接觸洞
46‧‧‧預清洗製程
48‧‧‧第一金屬層
50‧‧‧第二金屬層
52‧‧‧金屬矽化物
54‧‧‧第三金屬層
56‧‧‧接觸插塞
58‧‧‧接觸插塞
第1圖至第8圖為本發明較佳實施例製作一半導體元件之方法示意圖。
請參照第1圖至第8圖，第1圖至第8圖為本發明較佳實施例製作一半導體元件之方法示意圖。如第1圖所示，首先提供一 基底12，例如一矽基底或矽覆絕緣(SOI)基板，其上定義有一電晶體區，例如一PMOS電晶體區或一NMOS電晶體區。
基底12上具有至少一鰭狀結構14及一絕緣層16，其中鰭狀結構14之底部係被絕緣層16，例如氧化矽所包覆而形成淺溝隔離，且部分的鰭狀結構14上另分別設有一金屬閘極18與複數個選擇性設置之金屬閘極20。在後續製得的電晶體元件中，鰭狀結構14與金屬閘極18間的重疊區域可以作為載子流通之通道。另外在本實施例中，除了鰭狀結構14上所設置的金屬閘極18、20，絕緣層16上也可依據製程需求而形成有其他MOS電晶體的金屬閘極22穿過。
上述鰭狀結構14之形成方式可以包含先形成一圖案化遮罩(圖未示)於基底12上，再經過一蝕刻製程，將圖案化遮罩之圖案轉移至基底12中。接著，對應三閘極電晶體元件及雙閘極鰭狀電晶體元件結構特性的不同，而可選擇性去除或留下圖案化遮罩，並利用沈積、化學機械研磨(chemical mechanical polishing,CMP)及回蝕刻製程而形成一環繞鰭狀結構14底部之絕緣層16。除此之外，鰭狀結構14之形成方式另也可以是先製作一圖案化硬遮罩層(圖未示)於基底12上，並利用磊晶製程於暴露出於圖案化硬遮罩層之基底12上成長出半導體層，此半導體層即可作為相對應的鰭狀結構14。同樣的，另可以選擇性去除或留下圖案化硬遮罩層，並透過沈積、CMP及回蝕刻製程形成一絕緣層16以包覆住鰭狀結構14之底部。另外，當基底12為矽覆絕緣(SOI)基板時，則可利用圖案化遮罩來蝕刻基底上之一半導體層，並停止於此半導體層下方的一底氧化層以形成鰭狀結構，故可省略前述製作絕緣層16的步驟。
金屬閘極18、20、22之製作方式可先於鰭狀結構14與絕緣層16上形成一較佳包含高介電常數介電層與多晶矽材料所構成的虛置閘極(圖未示)，然後於虛置閘極側壁形成側壁子24。接著於側壁子24兩側的鰭狀結構14以及/或基底12中形成一源極/汲極區域26與磊晶層28、形成一接觸洞蝕刻停止層30覆蓋虛置閘極，並形成一層間介電層32於接觸洞蝕刻停止層30上。
之後可進行一金屬閘極置換(replacement metal gate)製程，以平坦化部分之層間介電層32及接觸洞蝕刻停止層30，並將虛置閘極轉換為一金屬閘極。金屬閘極置換製程可包括先進行一選擇性之乾蝕刻或濕蝕刻製程，例如利用氨水(ammonium hydroxide,NH4OH)或氫氧化四甲銨(Tetramethylammonium Hydroxide,TMAH)等蝕刻溶液來去除虛置閘極中的多晶矽材料以於層間介電層32中形成一凹槽。之後形成一至少包含U型功函數金屬層34與低阻抗金屬層36的導電層於該凹槽內，並再搭配進行一平坦化製程以形成金屬閘極18、20、22。
在本實施例中，功函數金屬層34較佳用以調整形成金屬閘極之功函數，使其適用於N型電晶體(NMOS)或P型電晶體(PMOS)。若電晶體為N型電晶體，功函數金屬層34可選用功函數為3.9電子伏特(eV)~4.3eV的金屬材料，如鋁化鈦(TiAl)、鋁化鋯(ZrAl)、鋁化鎢(WAl)、鋁化鉭(TaAl)、鋁化鉿(HfAl)或TiAlC(碳化鈦鋁)等，但不以此為限；若電晶體為P型電晶體，功函數金屬層34可選用功函數為4.8eV~5.2eV的金屬材料，如氮化鈦(TiN)、氮化鉭(TaN)或碳化鉭(TaC)等，但不以此為限。功函數金屬層34與低 阻抗金屬層36之間可包含另一阻障層(圖未示)，其中阻障層的材料可包含鈦(Ti)、氮化鈦(TiN)、鉭(Ta)、氮化鉭(TaN)等材料。低阻抗金屬層44則可選自銅(Cu)、鋁(Al)、鎢(W)、鈦鋁合金(TiAl)、鈷鎢磷化物(cobalt tungsten phosphide，CoWP)等低電阻材料或其組合。由於依據金屬閘極置換製程將虛置閘極轉換為金屬閘極乃此領域者所熟知技藝，在此不另加贅述。
形成金屬閘極18、20、22後可選擇性先去除部分功函數金屬層34與低阻抗金屬層36，然後填入一硬遮罩38於功函數金屬層34與低阻抗金屬層36上。其中硬遮罩38可為單一材料層或複合材料層，例如一包含氧化矽與氮化矽之複合層。接著平坦化後再沉積一介電層40，例如一前金屬介電層(pre-metal dielectric,PMD)於層間介電層32上並覆蓋金屬閘極18、20、22。
然後如第2圖所示，進行一微影暨蝕刻製程，例如先形成一圖案化光阻層(圖未示)於介電層40上，接著進行一蝕刻製程，去除部分介電層40與金屬閘極18兩側的層間介電層32，以形成複數個接觸洞42並暴露出源極/汲極區域26上的磊晶層28。在本實施例中，為了製作後續與源極/汲極區域26電性連接的插塞而進行之前述微影暨蝕刻製程較佳稱為第零金屬接觸圖案轉移(M0CT patterning)。
接著如第3圖所示，進行另一微影暨蝕刻製程，例如可再形成一圖案化光阻層(圖未示)於介電層40上，然後進行一蝕刻製程，去除部分介電層40與金屬閘極22上方的部分介電層40、部分層間介電層32以及硬遮罩38，以形成一接觸洞44並暴露出金屬閘 極22表面。在本實施例中，為了製作後續與金屬閘極22電性連接的插塞而進行之前述微影暨蝕刻製程較佳稱為第零金屬閘極接觸圖案轉移(M0PY patterning)。
在完成前述雙重成像暨雙重蝕刻(double-patterning and double-etching,2P2E)製成以形成接觸洞42、44之後。隨後如第4圖所示，進行一預清洗製程46，以去除接觸洞42、44內經由前述微影暨蝕刻製程後所剩餘的殘留物。
接著如第5圖所示，依序沉積一第一金屬層48及第二金屬層50於接觸洞42、44中，其中第一金屬層48與第二金屬層50較佳共形地(conformally)形成於介電層40與磊晶層28的表面及各接觸洞42、44的內側側壁。在本實施例中，第一金屬層48較佳選自鈦、鈷、鎳及鉑等所構成的群組，且最佳為鈦，而第二金屬層50則較佳包含氮化鈦、氮化鉭等金屬化合物。
在連續沉積第一金屬層48與第二金屬層50之後，然後如第6圖所示，依序進行一第一熱處理製程與一第二熱處理製程以形成一金屬矽化物52於磊晶層28上。在本實施例中，第一熱處理製程包含一常溫退火(soak anneal)製程，其溫度較佳介於500℃至600℃，且最佳為550℃，而其處理時間則較佳介於10秒至60秒，且最佳為30秒。第二熱處理製程包含一峰值退火(spike anneal)製程，其溫度較佳介於600℃至950℃，且最佳為600℃，而其處理較佳時間則較佳介於100毫秒至5秒，且最佳為5秒。
迨進行兩次熱處理製程後，如第7圖所示，形成一第三金 屬層54並填滿接觸洞42、44。在本實施例中，第三金屬層54較佳包含鎢，但不侷限於此。
最後如第8圖所示，進行一平坦化製程，例如以化學機械研磨(chemical mechanical polishing,CMP)製程部分去除第三金屬層54、部分第二金屬層50及部分第一金屬層48，甚至可視製程需求接著去除部分介電層40，以形成複數個接觸插塞56分別電連接源極/汲極區域26以及接觸插塞58電連接金屬閘極22。至此即完成本發明較佳實施例製作一鰭狀場效電晶體的流程。
依據本發明之較佳實施例，第6圖所進行之兩次熱處理製程較佳將第一金屬層48轉化為一金屬矽化物52。更具體而言，第一次熱處理製程較佳將第一金屬層48接觸磊晶層28的部分完全轉換為具有C49相位之二矽化鈦(TiSi2)金屬矽化物。而在經過第二次熱處理後，C49相位之金屬矽化物會進而轉換為阻值較低且具有C54相位的金屬矽化物。需注意的是，由於僅有與磊晶層28接觸的第一金屬層48會轉化為金屬矽化物52，亦即位於接觸洞42底部的第一金屬層48會完全轉化為金屬矽化物52，因此未與磊晶層28接觸的第一金屬層48在經過兩次熱處理製程後將不會被轉化為金屬矽化物52，且仍以原始金屬層型態設於接觸洞42、44側壁。同樣地，在接觸洞44內，與金屬閘極22接觸的第一金屬層48，在經過兩次熱處理製程後亦仍為原始金屬層型態，而不會被轉化為金屬矽化物52。
其次，由於第二金屬層50較佳用來避免第三金屬層54之金屬原子擴散至周圍的材料層中並同時增加第三金屬層54與介 電層40之間的附著力，因此從頭到尾均未反應為金屬矽化物52。以結構來看，經過兩次熱處理製程後的第二金屬層50較佳同時覆蓋於金屬矽化物52上以及未反應並設於接觸洞42、44側壁的第一金屬層48上。
請再參照第8圖，本發明另揭露一種半導體元件結構，其包含一基底12、至少一金屬閘極18設於基底12上、一鰭狀結構14設於基底12與金屬閘極18之間、一源極/汲極區域26設於鄰近金屬閘極18之基底12中、一層間介電層32設於基底12上並圍繞金屬閘極18、複數個接觸插塞56電連接源極/汲極區域26以及一金屬矽化物52設於接觸插塞56與源極/汲極區域26之間。依據本發明之較佳實施例，金屬矽化物52包含一C54相位之結構。而與金屬閘極22相接觸的接觸插塞58中仍具有二層完整的第一金屬層48與第二金屬層50。
此外，半導體元件另包含一磊晶層28設於金屬矽化物52與源極/汲極區域26之間，接觸插塞56包含一第一金屬層48環繞一第二金屬層50及一第三金屬層54，且第二金屬層50較佳直接接觸金屬矽化物52。在本實施例中，第一金屬層48是選自由鈦、鈷、鎳及鉑所構成的群組，第二金屬層50包含氮化鈦，第三金屬層54包含鎢，但不侷限於此。
綜上所述，本發明主要揭露一種鰭狀場效電晶體(FinFET)製程，其較佳於形成金屬閘極與接觸洞後(post contact)依序以兩道熱處理製程將接觸洞中的金屬層形成金屬矽化物並藉此電晶體的整體效能。更具體而言，本發明較佳於形成接觸洞後先依序沉積一第 一金屬層與第二金屬層於接觸洞內，然後利用第一道熱處理製程將接觸磊晶層或源極/汲極區域等含矽區域的第一金屬層轉換為C49相位之金屬矽化物，接著再利用第二道熱處理製程將已形成的金屬矽化物再次轉換為阻值較低且具有C54相位的金屬矽化物。之後在不去除任何未反應第一金屬層的情況下直接將一第三金屬層填入接觸洞內，並搭配化學機械研磨製程去除部分第三金屬層、第二金屬層及第一金屬層以形成複數個接觸插塞電連接源極/汲極區域及金屬閘極。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。

Claims (18)

  1. 一種製作半導體元件的方法，包含：提供一基底，該基底包含至少一金屬閘極設於其上、一源極/汲極區域設於該金屬閘極兩側的基底中以及一層間介電層環繞該金屬閘極；形成複數個接觸洞於該層間介電層中並暴露出該源極/汲極區域；形成一第一金屬層以及一第二金屬層於該接觸洞內；於形成該第一金屬層以及該第二金屬層之後進行一第一熱處理製程；以及進行一第二熱處理製程。
  2. 如申請專利範圍第1項所述之方法，另包含：形成一鰭狀結構於該基底上；以及形成該金屬閘極於該鰭狀結構上。
  3. 如申請專利範圍第1項所述之方法，其中該第一熱處理製程包含一常溫退火(soak anneal)製程，且該第二熱處理製程包含一峰值退火(spike anneal)製程。
  4. 如申請專利範圍第1項所述之方法，其中該第一熱處理製程之溫度介於500℃至600℃。
  5. 如申請專利範圍第1項所述之方法，其中該第二熱處理製程之溫度介於600℃至950℃。
  6. 如申請專利範圍第1項所述之方法，其中該第一熱處理製程之時間介於10秒至60秒。
  7. 如申請專利範圍第1項所述之方法，其中該第二熱處理製程之時間介於100毫秒至5秒。
  8. 如申請專利範圍第1項所述之方法，其中該第一金屬層選自由鈦、鈷、鎳及鉑所構成的群組，且該第二金屬層包含氮化鈦。
  9. 如申請專利範圍第1項所述之方法，另包含：形成一磊晶層於該源極/汲極上；形成一介電層於該層間介電層上；形成該等接觸洞於該介電層與該層間介電層中、形成該第一金屬層及該第二金屬層於該等接觸洞中；進行該第一熱處理製程及該第二熱處理製程以形成一金屬矽化物於該磊晶層上；形成一第三金屬層並填滿該等接觸洞；進行一平坦化製程以部分去除該第三金屬層、該第二金屬層及該第一金屬層。
  10. 如申請專利範圍第9項所述之方法，其中該第三金屬層包含鎢。
  11. 如申請專利範圍第9項所述之方法，其中該金屬矽化物包含一C54相位之結構。
  12. 如申請專利範圍第1項所述之方法，另包含於形成該第一金屬 層之前進行一預清洗製程。
  13. 一種半導體元件，包含：一基底；一金屬閘極設於該基底上；一接觸洞蝕刻停止層環繞該金屬閘極；一源極/汲極區域設於鄰近該金屬閘極之基底中；一層間介電層設於該基底上並圍繞該金屬閘極；複數個接觸插塞電連接該源極/汲極區域；以及一金屬矽化物設於該等接觸插塞及該源極/汲極區域之間，其中該金屬矽化物包含一C54相位之結構，其中該金屬矽化物兩側切齊該接觸洞蝕刻停止層之二側壁。
  14. 如申請專利範圍第13項所述之半導體元件，另包含一鰭狀結構設於該基底與該金屬閘極之間。
  15. 如申請專利範圍第13項所述之半導體元件，另包含一磊晶層設於該金屬矽化物與該源極/汲極區域之間。
  16. 如申請專利範圍第13項所述之半導體元件其中該等接觸插塞包含一第一金屬層環繞一第二金屬層及一第三金屬層。
  17. 如申請專利範圍第16項所述之半導體元件，其中該第二金屬層直接接觸該金屬矽化物。
  18. 如申請專利範圍第16項所述之半導體元件，其中該第一金屬層選自由鈦、鈷、鎳及鉑所構成的群組，該第二金屬層包含氮化鈦， 該第三金屬層包含鎢。
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