CN113097177B - 半导体元件 - Google Patents

半导体元件 Download PDF

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CN113097177B
CN113097177B CN202110275091.XA CN202110275091A CN113097177B CN 113097177 B CN113097177 B CN 113097177B CN 202110275091 A CN202110275091 A CN 202110275091A CN 113097177 B CN113097177 B CN 113097177B
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gate line
semiconductor device
gate
doped region
disposed
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CN113097177A (zh
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马瑞吉
林家辉
杨国裕
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United Microelectronics Corp
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United Microelectronics Corp
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Abstract

本发明公开一种半导体元件，其包含第一栅极线与第二栅极线仅沿着第一方向延伸、第三栅极线与第四栅极线沿着第一方向延伸并设于第一栅极线与第二栅极线之间，第五栅极线与第六栅极线沿着第二方向延伸，以及多个第一接触插塞设于第一栅极线上。其中第五栅极线以及第六栅极线设于第一栅极线以及第二栅极线之间并交错第三栅极线及第四栅极线，第一方向垂直于第二方向且第一栅极线与第二栅极线接触第五栅极线与第六栅极线。

Description

半导体元件
本发明是中国发明专利申请(申请号：201810035168.4，申请日：2018年01月15日，发明名称：半导体元件)的分案申请。
技术领域
本发明涉及一种半导体元件，尤其是涉及一种应用于低噪声放大器(Low NoiseAmplifier,LNA)的晶体管结构。
背景技术
随着科技的发展，无线通讯已成为人们生活中相当重要的一环，各种不同电子装置如智能型手机、智能型穿戴装置、平板计算机中通过无线射频系统来传送或接收无线信号。在无线射频系统中，低噪声放大器(Low Noise Amplifier,LNA)与功率放大器(PowerAmplifier,PA)为必要的放大电路。为了使放大电路具有最佳的效能(如线性度)，放大电路需要施加以一适当偏压，常见的作法为将放大电路电连接于一偏压模块，利用偏压模块来提供放大电路一适当偏压。
然而在现有技术中，例如低噪声放大器中的晶体管设计在部分参数上包括高栅极阻值、高栅极对基体掺杂区电容值(gate to body capacitance)以及最低噪声指数(minnoise figure)的表现仍不尽理想。由于这些参数在低噪声放大器效能表面上具有举足轻重的影响，因此如何改良现有晶体管架构进而改善这些参数表现即为现今一重要课题。
发明内容
本发明一实施例揭露一种半导体元件，其主要包含第一栅极线与第二栅极线仅沿着第一方向延伸、第三栅极线与第四栅极线沿着第一方向延伸并设于第一栅极线与第二栅极线之间，第五栅极线与第六栅极线沿着第二方向延伸，以及多个第一接触插塞设于第一栅极线上。其中第五栅极线以及第六栅极线设于第一栅极线以及第二栅极线之间并交错第三栅极线及第四栅极线，第一方向垂直于第二方向且第一栅极线与第二栅极线接触第五栅极线与第六栅极线。
附图说明
图1为本发明一实施例的应用于低噪声放大器的一半导体元件的上视图；
图2为本发明一实施例的应用于低噪声放大器的一半导体元件的上视图。
主要元件符号说明
12 基底 14 第一栅极线
16 第二栅极线 18 第三栅极线
20 第四栅极线 22 第五栅极线
24 第六栅极线 26 源极区域
28 第一漏极区域 30 第二漏极区域
32 掺杂区 34 掺杂区
36 掺杂区 38 掺杂区
40 掺杂区 42 掺杂区
44 掺杂区 46 掺杂区
48 掺杂区 50 接触插塞
52 第一金属内连线 54 第二金属内连线
56 第三金属内连线
62 基底 64 第一栅极线
66 第二栅极线 68 第三栅极线
70 第四栅极线 72 第五栅极线
74 第一源极区域 76 第一漏极区域
78 第二源极区域 80 第二漏极区域
82 掺杂区 84 掺杂区
86 掺杂区 88 掺杂区
90 掺杂区 92 掺杂区
94 掺杂区 96 掺杂区
98 突出部 100 突出部
102 突出部 104 接触插塞
106 第一金属内连线 108 第二金属内连线
110 第三金属内连线 112 第四金属内连线
具体实施方式
请参照图1，图1为本发明一实施例的应用于低噪声放大器的一半导体元件的上视图。如图1所示，半导体元件主要包含多条栅极线，包括第一栅极线14、第二栅极线16、第三栅极线18、第四栅极线20、第五栅极线22以及第六栅极线24设于一基底12上，其中基底12较佳为一硅覆绝缘(silicon-on-insulator,SOI)基底，例如可细部包含第一半导体层、一绝缘层设于第一半导体层上以及第二半导体层设于绝缘层上，其中第一半导体层以及第二半导体层可包含例如硅、锗或锗或硅等半导体材料而绝缘层可包含例如氧化硅等绝缘材料。
从细部来看，第一栅极线14以及第二栅极线16沿着第一方向(例如X方向)延伸，第三栅极线18以及第四栅极线20同样沿着第一方向延伸并设于第一栅极线以及第二栅极线之间，第五栅极线22以及第六栅极线24则沿着第二方向(例如Y方向)延伸，其中第五栅极线22以及第六栅极线24设于第一栅极线14以及第二栅极线16之间并交错第三栅极线18以及第四栅极线20。
此外，半导体元件又包含一源极区域26设于第五栅极线22以及第六栅极线24之间，第一漏极区域28设于第五栅极线22一侧以及第二漏极区域30设于第六栅极线24一侧。更具体而言，源极区域26较佳沿着第二方向延伸且更细部包含掺杂区32、掺杂区34以及掺杂区36，其中掺杂区32位于第一栅极线12以及第三栅极线18之间，掺杂区34位于第三栅极线18以及第四栅极线20之间，掺杂区36则位于第二栅极线16以及第四栅极线20之间。如同源极区域26，第一漏极区域28沿着第二方向延伸且更细部包含掺杂区38、掺杂区40以及掺杂区42，其中掺杂区38位于第一栅极线12以及第三栅极线18之间，掺杂区40位于第三栅极线18以及第四栅极线20之间，掺杂区42则位于第二栅极线16以及第四栅极线20之间。另外第二漏极区域30也较佳沿着第二方向延伸且更细部包含掺杂区44、掺杂区46以及掺杂区48，其中掺杂区44位于第一栅极线12以及第三栅极线18之间，掺杂区46位于第三栅极线18以及第四栅极线20之间，掺杂区48则位于第二栅极线16以及第四栅极线20之间。
在本实施例中，第一栅极线12与第三栅极线18之间的掺杂区32、38、44以及第二栅极线16与第四栅极线20之间的掺杂区36、42、48较佳包含相同导电型式或第一导电型式，第三栅极线18以及第四栅极线20之间的掺杂区34、40、46则包含第二导电型式，其中本实施例的第一导电型式较佳为N型而第二导电型式则为P型。但不局限于此，依据本发明其他实施例第一导电型式又可为P型而第二导电型式为N型，此实施例也属本发明所涵盖的范围。
另外本实施例各栅极线或栅极结构，包括第一栅极线14、第二栅极线16、第三栅极线18、第四栅极线20、第五栅极线22以及第六栅极线24均可依据制作工艺需求以先栅极(gate first)制作工艺、后栅极(gate last)制作工艺的先高介电常数介电层(high-kfirst)制作工艺以及后栅极制作工艺的后高介电常数介电层(high-k last)制作工艺等方式制作完成，而为一一体成型的结构。换句话说，各栅极线可依据制作工艺或产品需求为多晶硅所构成的多晶硅栅极线，或可经由金属栅极置换(replacement metal gate,RMG)制作工艺将原本由多晶硅所构成的栅极线转换为金属栅极线，这两种变化型均属本发明所涵盖的范围。由于多晶硅栅极线以及金属栅极线的制作均属本领域所熟知技术，在此不另加赘述。
此外，半导体元件又包含多个接触插塞50设于第一栅极线14、第二栅极线16、源极区域26、第一漏极区域28以及第二漏极区域30。其中接触插塞50的制作可先形成一层间介电层(图未示)于基底12上，然后进行一图案转移制作工艺，例如可利用一图案化掩模去除各栅极线旁的部分的层间介电层以形成多个接触洞(图未示)并暴露出下面的第一栅极线14、第二栅极线16、源极区域26、第一漏极区域28以及第二漏极区域30。随后于各接触洞中填入所需的金属材料，例如包含钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)等的阻障层材料以及选自钨(W)、铜(Cu)、铝(Al)、钛铝合金(TiAl)、钴钨磷化物(cobalt tungstenphosphide，CoWP)等低电阻材料或其组合的低阻抗金属层。接着进行一平坦化制作工艺，例如以化学机械研磨制作工艺去除部分金属材料以分别形成接触插塞50于各接触洞内电连接第一栅极线14、第二栅极线16、源极区域26、第一漏极区域28以及第二漏极区域30。
之后可进行后续金属内连线制作工艺以于层间介电层上形成金属间介电层(图未示)以及金属内连线分别连接各接触插塞50。在本实施例中，半导体元件主要包含第一金属内连线52沿着第二方向延伸于第五栅极线22以及第六栅极线24之间并电连接源极区域26、第二金属内连线54沿着第二方向延伸于第五栅极线22一侧并电连接第一漏极区域28以及第三金属内连线56沿着第二方向延伸于第六栅极24线一侧并电连接第二漏极区域30，其中第一金属内连线52、第二金属内连线54以及第三金属内连线56交错第三栅极线18以及第四栅极线20。
请再参照图2，图2为本发明一实施例的应用于低噪声放大器的一半导体元件的上视图。如图2所示，半导体元件主要包含多条栅极线，包括第一栅极线64、第二栅极线66、第三栅极线68、第四栅极线70以及第五栅极线72设于一基底62上，其中基底62较佳为一硅覆绝缘(silicon-on-insulator,SOI)基底，例如可细部包含第一半导体层、一绝缘层设于第一半导体层上以及第二半导体层设于绝缘层上，其中第一半导体层以及第二半导体层可包含例如硅、锗或锗或硅等半导体材料而绝缘层可包含例如氧化硅等绝缘材料。
在本实施例中，第一栅极线64以及第二栅极线66沿着第一方向(例如X方向)延伸，第三栅极线68、第四栅极线70以及第五栅极线72则沿着第二方向(例如Y方向)延伸。此外，半导体元件又包含一第一源极区域74设于第三栅极线68一侧，第一漏极区域76设于第三栅极68线以及第四栅极线70之间、第二源极区域78设于第四栅极线70以及第五栅极线72之间以及第二漏极区域80设于第五栅极线72一侧。更具体而言，第一源极区域74较佳沿着第二方向延伸且更细部包含掺杂区82、掺杂区84以及掺杂区86，第一漏极区域76是沿着第二方向延伸且更细部包含掺杂区88，第二源极区域78是沿着第二方向延伸且更细部包含掺杂区90、掺杂区92以及掺杂区94，第二漏极区域80是沿着第二方向延伸且更细部包含掺杂区96。
值得注意的是，第三栅极线68较佳包含一突出部98重叠或覆盖部分第一漏极区域76，第四栅极线70较佳包含一突出部100重叠部分第一漏极区域，且第五栅极线72包含一第一突出部102重叠部分第二漏极区域80。更具体而言，第三栅极线68以及第四栅极线70的突出部98、100较佳为对称设计且第三栅极线68以及第四栅极线70的对称突出部结构可被重复拷贝至左右两侧所有的栅极线。举例来说，本实施例虽仅于第四栅极线70右侧绘示出一条第五栅极线72具有类似的突出部102，但第五栅极线72右侧又可比照第四栅极线70的突出部100态样设置另一条具有与第四栅极线70相同突出部100的第六栅极线(图未示)，使第五栅极线72的突出部102以及第六栅极线的突出部同时重叠部分第二漏极区域80。
另外在本实施例中，第一源极区域74的掺杂区82、86、第一漏极区域76的掺杂区88、第二源极区域78的掺杂区90、94以及第二漏极区域80的掺杂区96较佳包含相同导电型式或第一导电型式，第一源极区域74的掺杂区84以及第二源极区域78的掺杂区92则包含第二导电型式，其中本实施例的第一导电型式较佳为N型而第二导电型式则为P型。但不局限于此，依据本发明其他实施例第一导电型式又可为P型而第二导电型式为N型，此实施例也属本发明所涵盖的范围。
如同前述实施例，各栅极线或栅极结构，包括第一栅极线64、第二栅极线66、第三栅极线68、第四栅极线70以及第五栅极线72均可依据制作工艺需求以先栅极(gate first)制作工艺、后栅极(gate last)制作工艺的先高介电常数介电层(high-k first)制作工艺以及后栅极制作工艺的后高介电常数介电层(high-k last)制作工艺等方式制作完成。换句话说，各栅极线可依据制作工艺或产品需求为多晶硅所构成的多晶硅栅极线，或可经由金属栅极置换(replacement metal gate,RMG)制作工艺将原本由多晶硅所构成的栅极线转换为金属栅极线，这两种变化型均属本发明所涵盖的范围。由于多晶硅栅极线以及金属栅极线的制作均属本领域所熟知技术，在此不另加赘述。
此外，半导体元件又包含多个接触插塞104设于第一栅极线64、第二栅极线66、第一源极区域74、第一漏极区域76、第二源极区域78以及第二漏极区域80。其中接触插塞104的制作可先形成一层间介电层(图未示)于基底12上，然后进行一图案转移制作工艺，例如可利用一图案化掩模去除各栅极线旁的部分的层间介电层以形成多个接触洞(图未示)并暴露出下面的源极区域、第一漏极区域20以及第二漏极区域24。随后于各接触洞中填入所需的金属材料，例如包含钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)等的阻障层材料以及选自钨(W)、铜(Cu)、铝(Al)、钛铝合金(TiAl)、钴钨磷化物(cobalt tungsten phosphide，CoWP)等低电阻材料或其组合的低阻抗金属层。接着进行一平坦化制作工艺，例如以化学机械研磨制作工艺去除部分金属材料以分别形成接触插塞104于各接触洞内电连接第一栅极线64、第二栅极线66、第一源极区域74、第一漏极区域76、第二源极区域78以及第二漏极区域80。
之后可进行后续金属内连线制作工艺以于层间介电层上形成金属间介电层(图未示)以及金属内连线分别连接各接触插塞104。在本实施例中，半导体元件主要包含第一金属内连线106沿着第二方向延伸于第三栅极线68以及第四栅极线70之间并电连接第一漏极区域76、第二金属内连线108沿着第二方向延伸于第三栅极线68一侧并电连接第一源极区域74、第三金属内连线110沿着第二方向延伸于第四栅极线70以及第五栅极线72之间并电连接第二源极区域78以及第四金属内连线112沿着第二方向延伸于第五栅极线72一侧并电连接第二漏极区域80。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (10)

1.一种半导体元件，其特征在于，包含：
第一栅极线以及第二栅极线，仅沿着第一方向延伸；
第三栅极线以及第四栅极线，沿着该第一方向延伸并设于该第一栅极线以及该第二栅极线之间；
第五栅极线以及第六栅极线，沿着第二方向延伸，其中该第五栅极线以及该第六栅极线设于该第一栅极线以及该第二栅极线之间并交错该第三栅极线以及该第四栅极线，该第一方向垂直于该第二方向且该第一栅极线，该第一栅极线以及该第二栅极线直接连接到该第五栅极线以及该第六栅极线，该第一栅极线的边缘与该第三栅极线的边缘之间的距离和该第二栅极线的边缘与该第四栅极线的边缘之间的距离都大于该第三栅极线的边缘与该第四栅极线的边缘之间的距离，而该第一栅极线直接相邻于该第三栅极线且该第二栅极线直接相邻于该第四栅极线；
多个第一接触插塞，设于该第一栅极线以及该第二栅极线上且没有接触插塞设于该第三栅极线、该第四栅极线、该第五栅极线以及该第六栅极线上；以及
第一金属内连线，沿着该第二方向延伸，设于该第五栅极线以及该第六栅极线之间并重叠该第三栅极线以及该第四栅极线，其中与具有该第一接触插塞的该第一栅极线正交的该第一金属内连线包含沿着该第一方向延伸的第一侧以及沿着该第二方向延伸的第二侧。
2.如权利要求1所述的半导体元件，另包含：
源极区域，设于该第五栅极线以及该第六栅极线之间；
第一漏极区域，设于该第五栅极线一侧；以及
第二漏极区域，设于该第六栅极线一侧。
3.如权利要求2所述的半导体元件，另包含接触插塞，设于该第三栅极线以及该第四栅极线之间的该源极区域、该第一漏极区域以及该第二漏极区域的每一者上。
4.如权利要求2所述的半导体元件，另包含：
第二金属内连线，沿着该第二方向延伸于该第五栅极线一侧并电连接该第一漏极区域；以及
第三金属内连线，沿着该第二方向延伸于该第六栅极线一侧并电连接该第二漏极区域。
5.如权利要求4所述的半导体元件，其中该第一金属内连线、该第二金属内连线以及该第三金属内连线交错该第三栅极线以及该第四栅极线。
6.如权利要求1所述的半导体元件，另包含第一掺杂区，设于该第一栅极线以及该第三栅极线之间。
7.如权利要求6所述的半导体元件，另包含第二掺杂区，设于该第二栅极线以及该第四栅极线之间。
8.如权利要求7所述的半导体元件，其中该第一掺杂区以及该第二掺杂区包含相同导电型式。
9.如权利要求7所述的半导体元件，另包含第三掺杂区设于该第三栅极线以及该第四栅极线之间。
10.如权利要求9所述的半导体元件，其中该第一掺杂区以及该第三掺杂区包含不同导电型式。
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Publication number Priority date Publication date Assignee Title
JP3266644B2 (ja) * 1991-04-08 2002-03-18 テキサス インスツルメンツ インコーポレイテツド ゲートアレイ装置
US5420447A (en) * 1993-01-29 1995-05-30 Sgs-Thomson Microelectronics, Inc. Double buffer base gate array cell
US5355008A (en) 1993-11-19 1994-10-11 Micrel, Inc. Diamond shaped gate mesh for cellular MOS transistor array
US6387739B1 (en) 1998-08-07 2002-05-14 International Business Machines Corporation Method and improved SOI body contact structure for transistors
KR20080082426A (ko) * 2007-03-07 2008-09-11 삼성전자주식회사 스태틱 메모리 소자
US8178908B2 (en) 2008-05-07 2012-05-15 International Business Machines Corporation Electrical contact structure having multiple metal interconnect levels staggering one another
JP5363044B2 (ja) * 2008-07-22 2013-12-11 ルネサスエレクトロニクス株式会社 半導体集積回路装置
KR101865840B1 (ko) * 2011-08-10 2018-06-08 삼성전자주식회사 반도체 소자
KR101852512B1 (ko) * 2012-01-03 2018-04-26 삼성전자주식회사 반도체 소자
US9508396B2 (en) * 2014-04-02 2016-11-29 Ememory Technology Inc. Array structure of single-ploy nonvolatile memory
US10192875B2 (en) * 2014-10-14 2019-01-29 Ememory Technology Inc. Non-volatile memory with protective stress gate
US9559644B2 (en) 2014-11-03 2017-01-31 Qorvo Us, Inc. Low noise amplifier
JP6648489B2 (ja) 2015-10-30 2020-02-14 セイコーエプソン株式会社 バッファー回路、半導体集積回路装置、発振器、電子機器及び基地局
US10062697B2 (en) 2016-02-16 2018-08-28 Samsung Electronics Co., Ltd. Semiconductor device without a break region
US10128365B2 (en) * 2016-03-17 2018-11-13 Cree, Inc. Bypassed gate transistors having improved stability

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105321810A (zh) * 2014-07-08 2016-02-10 联华电子股份有限公司 制作半导体元件的方法
CN107017164A (zh) * 2015-11-30 2017-08-04 台湾积体电路制造股份有限公司 半导体装置及其制造方法

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