CN110047813B - 半导体元件 - Google Patents

半导体元件 Download PDF

Info

Publication number
CN110047813B
CN110047813B CN201810035168.4A CN201810035168A CN110047813B CN 110047813 B CN110047813 B CN 110047813B CN 201810035168 A CN201810035168 A CN 201810035168A CN 110047813 B CN110047813 B CN 110047813B
Authority
CN
China
Prior art keywords
gate line
doped region
region
gate
drain region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201810035168.4A
Other languages
English (en)
Other versions
CN110047813A (zh
Inventor
马瑞吉
林家辉
杨国裕
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
United Microelectronics Corp
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to CN202110275091.XA priority Critical patent/CN113097177B/zh
Priority to CN202110265888.1A priority patent/CN112968057B/zh
Priority to CN201810035168.4A priority patent/CN110047813B/zh
Priority to US15/893,676 priority patent/US10600734B2/en
Priority to US16/122,897 priority patent/US11201115B2/en
Publication of CN110047813A publication Critical patent/CN110047813A/zh
Priority to US16/734,373 priority patent/US11476192B2/en
Application granted granted Critical
Publication of CN110047813B publication Critical patent/CN110047813B/zh
Priority to US17/520,725 priority patent/US11658118B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/294—Indexing scheme relating to amplifiers the amplifier being a low noise amplifier [LNA]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/04—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
    • H03F3/16—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only with field-effect devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

本发明公开一种半导体元件，其主要包含一第一栅极线以及一第二栅极线沿着一第一方向延伸、一第三栅极线沿着一第二方向延伸并设于第一栅极线以及第二栅极线之间以及一漏极区域设于第三栅极线一侧，其中第三栅极线包含一第一突出部且该第一突出部重叠漏极区域。

Description

半导体元件
技术领域
本发明涉及一种于硅覆绝缘基底上的半导体元件，尤其是涉及一种应用于低噪声放大器(Low Noise Amplifier,LNA)的晶体管结构。
背景技术
随着科技的发展，无线通讯已成为人们生活中相当重要的一环，各种不同电子装置如智能型手机、智能型穿戴装置、平板电脑中通过无线射频系统来传送或接收无线信号。在无线射频系统中，低噪声放大器(Low Noise Amplifier,LNA)与功率放大器(PowerAmplifier,PA)为必要的放大电路。为了使放大电路具有最佳的效能(如线性度)，放大电路需要施加以一适当偏压，常见的作法为将放大电路电连接于一偏压模块，利用偏压模块来提供放大电路一适当偏压。
然而于现有技术中，例如低噪声放大器中的晶体管设计在部分参数上包括高栅极阻值、高栅极对基体掺杂区电容值(gate to body capacitance)以及最低噪声指数(minnoise figure)的表现仍不尽理想。由于这些参数在低噪声放大器效能表面上具有举足轻重的影响，因此如何改良现有晶体管架构进而改善这些参数表现即为现今一重要课题。
发明内容
本发明一实施例公开一种半导体元件，其主要包含：一第一栅极线以及一第二栅极线沿着第一方向延伸；一第三栅极线以及一第四栅极线沿着第一方向延伸并设于第一栅极线以及第二栅极线之间；以及一第五栅极线以及一第六栅极线沿着一第二方向延伸，其中第五栅极线以及第六栅极线设于第一栅极线以及第二栅极线之间并交错第三栅极线以及第四栅极线。
本发明另一实施例公开一种半导体元件，其主要包含一第一栅极线以及一第二栅极线沿着一第一方向延伸、一第三栅极线沿着一第二方向延伸并设于第一栅极线以及第二栅极线之间以及一漏极区域设于第三栅极线一侧，其中第三栅极线包含一第一突出部且该第一突出部重叠漏极区域。
附图说明
图1为本发明一实施例的应用于低噪声放大器的一半导体元件的上视图；
图2为本发明一实施例的应用于低噪声放大器的一半导体元件的上视图。
主要元件符号说明
12 基底 14 第一栅极线
16 第二栅极线 18 第三栅极线
20 第四栅极线 22 第五栅极线
24 第六栅极线 26 源极区域
28 第一漏极区域 30 第二漏极区域
32 掺杂区 34 掺杂区
36 掺杂区 38 掺杂区
40 掺杂区 42 掺杂区
44 掺杂区 46 掺杂区
48 掺杂区 50 接触插塞
52 第一金属内连线 54 第二金属内连线
56 第三金属内连线
62 基底 64 第一栅极线
66 第二栅极线 68 第三栅极线
70 第四栅极线 72 第五栅极线
74 第一源极区域 76 第一漏极区域
78 第二源极区域 80 第二漏极区域
82 掺杂区 84 掺杂区
86 掺杂区 88 掺杂区
90 掺杂区 92 掺杂区
94 掺杂区 96 掺杂区
98 突出部 100 突出部
102 突出部 104 接触插塞
106 第一金属内连线 108 第二金属内连线
110 第三金属内连线 112 第四金属内连线
具体实施方式
请参照图1，图1为本发明一实施例的应用于低噪声放大器的一半导体元件的上视图。如图1所示，半导体元件主要包含多条栅极线，包括第一栅极线14、第二栅极线16、第三栅极线18、第四栅极线20、第五栅极线22以及第六栅极线24设于一基底12上，其中基底12较佳为一硅覆绝缘(silicon-on-insulator,SOI)基底，例如可细部包含第一半导体层、一绝缘层设于第一半导体层上以及第二半导体层设于绝缘层上，其中第一半导体层以及第二半导体层可包含例如硅、锗或锗或硅等半导体材料而绝缘层可包含例如氧化硅等绝缘材料。
从细部来看，第一栅极线14以及第二栅极线16沿着第一方向(例如X方向)延伸，第三栅极线18以及第四栅极线20同样沿着第一方向延伸并设于第一栅极线以及第二栅极线之间，第五栅极线22以及第六栅极线24则沿着第二方向(例如Y方向)延伸，其中第五栅极线22以及第六栅极线24设于第一栅极线14以及第二栅极线16之间并交错第三栅极线18以及第四栅极线20。
此外，半导体元件又包含一源极区域26设于第五栅极线22以及第六栅极线24之间，第一漏极区域28设于第五栅极线22一侧以及第二漏极区域30设于第六栅极线24一侧。更具体而言，源极区域26较佳沿着第二方向延伸且更细部包含掺杂区32、掺杂区34以及掺杂区36，其中掺杂区32位于第一栅极线12以及第三栅极线18之间，掺杂区34位于第三栅极线18以及第四栅极线20之间，掺杂区36则位于第二栅极线16以及第四栅极线20之间。如同源极区域26，第一漏极区域28沿着第二方向延伸且更细部包含掺杂区38、掺杂区40以及掺杂区42，其中掺杂区38位于第一栅极线12以及第三栅极线18之间，掺杂区40位于第三栅极线18以及第四栅极线20之间，掺杂区42则位于第二栅极线16以及第四栅极线20之间。另外第二漏极区域30也较佳沿着第二方向延伸且更细部包含掺杂区44、掺杂区46以及掺杂区48，其中掺杂区44位于第一栅极线12以及第三栅极线18之间，掺杂区46位于第三栅极线18以及第四栅极线20之间，掺杂区48则位于第二栅极线16以及第四栅极线20之间。
在本实施例中，第一栅极线12与第三栅极线18之间的掺杂区32、38、44以及第二栅极线16与第四栅极线20之间的掺杂区36、42、48较佳包含相同导电型式或第一导电型式，第三栅极线18以及第四栅极线20之间的掺杂区34、40、46则包含第二导电型式，其中本实施例的第一导电型式较佳为N型而第二导电型式则为P型。但不局限于此，依据本发明其他实施例第一导电型式又可为P型而第二导电型式为N型，此实施例也属本发明所涵盖的范围。
另外本实施例各栅极线或栅极结构，包括第一栅极线14、第二栅极线16、第三栅极线18、第四栅极线20、第五栅极线22以及第六栅极线24均可依据制作工艺需求以先栅极(gate first)制作工艺、后栅极(gate last)制作工艺的先高介电常数介电层(high-kfirst)制作工艺以及后栅极制作工艺的后高介电常数介电层(high-k last)制作工艺等方式制作完成，而为一一体成型的结构。换句话说，各栅极线可依据制作工艺或产品需求为多晶硅所构成的多晶硅栅极线，或可经由金属栅极置换(replacement metal gate,RMG)制作工艺将原本由多晶硅所构成的栅极线转换为金属栅极线，这两种变化型均属本发明所涵盖的范围。由于多晶硅栅极线以及金属栅极线的制作均属本领域所熟知技术，在此不另加赘述。
此外，半导体元件又包含多个接触插塞50设于第一栅极线14、第二栅极线16、源极区域26、第一漏极区域28以及第二漏极区域30。其中接触插塞50的制作可先形成一层间介电层(图未示)于基底12上，然后进行一图案转移制作工艺，例如可利用一图案化掩模去除各栅极线旁的部分的层间介电层以形成多个接触洞(图未示)并暴露出下面的第一栅极线14、第二栅极线16、源极区域26、第一漏极区域28以及第二漏极区域30。随后于各接触洞中填入所需的金属材料，例如包含钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)等的阻障层材料以及选自钨(W)、铜(Cu)、铝(Al)、钛铝合金(TiAl)、钴钨磷化物(cobalt tungstenphosphide，CoWP)等低电阻材料或其组合的低阻抗金属层。接着进行一平坦化制作工艺，例如以化学机械研磨制作工艺去除部分金属材料以分别形成接触插塞50于各接触洞内电连接第一栅极线14、第二栅极线16、源极区域26、第一漏极区域28以及第二漏极区域30。
之后可进行后续金属内连线制作工艺以于层间介电层上形成金属间介电层(图未示)以及金属内连线分别连接各接触插塞50。在本实施例中，半导体元件主要包含第一金属内连线52沿着第二方向延伸于第五栅极线22以及第六栅极线24之间并电连接源极区域26、第二金属内连线54沿着第二方向延伸于第五栅极线22一侧并电连接第一漏极区域28以及第三金属内连线56沿着第二方向延伸于第六栅极24线一侧并电连接第二漏极区域30，其中第一金属内连线52、第二金属内连线54以及第三金属内连线56交错第三栅极线18以及第四栅极线20。
请再参照图2，图2为本发明一实施例的应用于低噪声放大器的一半导体元件的上视图。如图2所示，半导体元件主要包含多条栅极线，包括第一栅极线64、第二栅极线66、第三栅极线68、第四栅极线70以及第五栅极线72设于一基底62上，其中基底62较佳为一硅覆绝缘(silicon-on-insulator,SOI)基底，例如可细部包含第一半导体层、一绝缘层设于第一半导体层上以及第二半导体层设于绝缘层上，其中第一半导体层以及第二半导体层可包含例如硅、锗或锗或硅等半导体材料而绝缘层可包含例如氧化硅等绝缘材料。
在本实施例中，第一栅极线64以及第二栅极线66沿着第一方向(例如X方向)延伸，第三栅极线68、第四栅极线70以及第五栅极线72则沿着第二方向(例如Y方向)延伸。此外，半导体元件又包含一第一源极区域74设于第三栅极线68一侧，第一漏极区域76设于第三栅极68线以及第四栅极线70之间、第二源极区域78设于第四栅极线70以及第五栅极线72之间以及第二漏极区域80设于第五栅极线72一侧。更具体而言，第一源极区域74较佳沿着第二方向延伸且更细部包含掺杂区82、掺杂区84以及掺杂区86，第一漏极区域76是沿着第二方向延伸且更细部包含掺杂区88，第二源极区域78是沿着第二方向延伸且更细部包含掺杂区90、掺杂区92以及掺杂区94，第二漏极区域80是沿着第二方向延伸且更细部包含掺杂区96。
值得注意的是，第三栅极线68较佳包含一突出部98重叠或覆盖部分第一漏极区域76，第四栅极线70较佳包含一突出部100重叠部分第一漏极区域，且第五栅极线72包含一第一突出部102重叠部分第二漏极区域80。更具体而言，第三栅极线68以及第四栅极线70的突出部98、100较佳为对称设计且第三栅极线68以及第四栅极线70的对称突出部结构可被重复拷贝至左右两侧所有的栅极线。举例来说，本实施例虽仅于第四栅极线70右侧绘示出一条第五栅极线72具有类似的突出部102，但第五栅极线72右侧又可比照第四栅极线70的突出部100态样设置另一条具有与第四栅极线70相同突出部100的第六栅极线(图未示)，使第五栅极线72的突出部102以及第六栅极线的突出部同时重叠部分第二漏极区域80。
另外在本实施例中，第一源极区域74的掺杂区82、86、第一漏极区域76的掺杂区88、第二源极区域78的掺杂区90、94以及第二漏极区域80的掺杂区96较佳包含相同导电型式或第一导电型式，第一源极区域74的掺杂区84以及第二源极区域78的掺杂区92则包含第二导电型式，其中本实施例的第一导电型式较佳为N型而第二导电型式则为P型。但不局限于此，依据本发明其他实施例第一导电型式又可为P型而第二导电型式为N型，此实施例也属本发明所涵盖的范围。
如同前述实施例，各栅极线或栅极结构，包括第一栅极线64、第二栅极线66、第三栅极线68、第四栅极线70以及第五栅极线72均可依据制作工艺需求以先栅极(gate first)制作工艺、后栅极(gate last)制作工艺的先高介电常数介电层(high-k first)制作工艺以及后栅极制作工艺的后高介电常数介电层(high-k last)制作工艺等方式制作完成。换句话说，各栅极线可依据制作工艺或产品需求为多晶硅所构成的多晶硅栅极线，或可经由金属栅极置换(replacement metal gate,RMG)制作工艺将原本由多晶硅所构成的栅极线转换为金属栅极线，这两种变化型均属本发明所涵盖的范围。由于多晶硅栅极线以及金属栅极线的制作均属本领域所熟知技术，在此不另加赘述。
此外，半导体元件又包含多个接触插塞104设于第一栅极线64、第二栅极线66、第一源极区域74、第一漏极区域76、第二源极区域78以及第二漏极区域80。其中接触插塞104的制作可先形成一层间介电层(图未示)于基底12上，然后进行一图案转移制作工艺，例如可利用一图案化掩模去除各栅极线旁的部分的层间介电层以形成多个接触洞(图未示)并暴露出下面的源极区域、第一漏极区域20以及第二漏极区域24。随后于各接触洞中填入所需的金属材料，例如包含钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)等的阻障层材料以及选自钨(W)、铜(Cu)、铝(Al)、钛铝合金(TiAl)、钴钨磷化物(cobalttungsten phosphide，CoWP)等低电阻材料或其组合的低阻抗金属层。接着进行一平坦化制作工艺，例如以化学机械研磨制作工艺去除部分金属材料以分别形成接触插塞104于各接触洞内电连接第一栅极线64、第二栅极线66、第一源极区域74、第一漏极区域76、第二源极区域78以及第二漏极区域80。
之后可进行后续金属内连线制作工艺以于层间介电层上形成金属间介电层(图未示)以及金属内连线分别连接各接触插塞104。在本实施例中，半导体元件主要包含第一金属内连线106沿着第二方向延伸于第三栅极线68以及第四栅极线70之间并电连接第一漏极区域76、第二金属内连线108沿着第二方向延伸于第三栅极线68一侧并电连接第一源极区域74、第三金属内连线110沿着第二方向延伸于第四栅极线70以及第五栅极线72之间并电连接第二源极区域78以及第四金属内连线112沿着第二方向延伸于第五栅极线72一侧并电连接第二漏极区域80。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (5)

1.一种半导体元件，其特征在于，包含：
第一栅极线以及第二栅极线，沿着一第一方向延伸；
第三栅极线以及第四栅极线，沿着该第一方向延伸并设于该第一栅极线以及该第二栅极线之间；
第五栅极线以及第六栅极线，沿着一第二方向延伸，其中该第五栅极线以及该第六栅极线设于该第一栅极线以及该第二栅极线之间并交错该第三栅极线以及该第四栅极线；
第一掺杂区，设于该第一栅极线以及该第三栅极线之间；
第二掺杂区，设于该第二栅极线以及该第四栅极线之间；以及
第三掺杂区，设于该第三栅极线以及该第四栅极线之间，
其中该第一掺杂区以及该第二掺杂区包含相同导电型式，该第一掺杂区以及该第三掺杂区包含不同导电型式，在上视图中，该第三掺杂区的第一边缘与该第三栅极线的边缘重合，且该第三掺杂区的第二边缘于该第四栅极线的边缘重合。
2.如权利要求1所述的半导体元件，另包含：
源极区域，设于该第五栅极线以及该第六栅极线之间；
第一漏极区域，设于该第五栅极线一侧；以及
第二漏极区域，设于该第六栅极线一侧。
3.如权利要求2所述的半导体元件，另包含至少一接触插塞设于该第三栅极线以及该第四栅极线之间的该源极区域、该第一漏极区域以及该第二漏极区域。
4.如权利要求2所述的半导体元件，另包含：
第一金属内连线，沿着该第二方向延伸于该第五栅极线以及该第六栅极线之间并电连接该源极区域；
第二金属内连线，沿着该第二方向延伸于该第五栅极线一侧并电连接该第一漏极区域；以及
第三金属内连线，沿着该第二方向延伸于该第六栅极线一侧并电连接该第二漏极区域。
5.如权利要求4所述的半导体元件，其中该第一金属内连线、该第二金属内连线以及该第三金属内连线交错该第三栅极线以及该第四栅极线。
CN201810035168.4A 2018-01-15 2018-01-15 半导体元件 Active CN110047813B (zh)

Priority Applications (7)

Application Number Priority Date Filing Date Title
CN202110275091.XA CN113097177B (zh) 2018-01-15 2018-01-15 半导体元件
CN202110265888.1A CN112968057B (zh) 2018-01-15 2018-01-15 半导体元件
CN201810035168.4A CN110047813B (zh) 2018-01-15 2018-01-15 半导体元件
US15/893,676 US10600734B2 (en) 2018-01-15 2018-02-11 Transistor structure in low noise amplifier
US16/122,897 US11201115B2 (en) 2018-01-15 2018-09-06 Semiconductor device
US16/734,373 US11476192B2 (en) 2018-01-15 2020-01-05 Transistor structure in low noise amplifier
US17/520,725 US11658118B2 (en) 2018-01-15 2021-11-08 Transistor structure in low noise amplifier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201810035168.4A CN110047813B (zh) 2018-01-15 2018-01-15 半导体元件

Related Child Applications (2)

Application Number Title Priority Date Filing Date
CN202110265888.1A Division CN112968057B (zh) 2018-01-15 2018-01-15 半导体元件
CN202110275091.XA Division CN113097177B (zh) 2018-01-15 2018-01-15 半导体元件

Publications (2)

Publication Number Publication Date
CN110047813A CN110047813A (zh) 2019-07-23
CN110047813B true CN110047813B (zh) 2021-04-06

Family

ID=67214232

Family Applications (3)

Application Number Title Priority Date Filing Date
CN202110275091.XA Active CN113097177B (zh) 2018-01-15 2018-01-15 半导体元件
CN201810035168.4A Active CN110047813B (zh) 2018-01-15 2018-01-15 半导体元件
CN202110265888.1A Active CN112968057B (zh) 2018-01-15 2018-01-15 半导体元件

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CN202110275091.XA Active CN113097177B (zh) 2018-01-15 2018-01-15 半导体元件

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN202110265888.1A Active CN112968057B (zh) 2018-01-15 2018-01-15 半导体元件

Country Status (2)

Country Link
US (4) US10600734B2 (zh)
CN (3) CN113097177B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115101540A (zh) * 2022-06-30 2022-09-23 惠科股份有限公司 晶体管结构、栅极驱动电路及其驱动方法和显示面板

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101635506A (zh) * 2008-07-22 2010-01-27 株式会社瑞萨科技 半导体集成电路器件
US20130037888A1 (en) * 2011-08-10 2013-02-14 Samsung Electronics Co., Ltd. Semiconductor device
CN107393924A (zh) * 2014-04-02 2017-11-24 力旺电子股份有限公司 具有辅助栅极的非易失性存储单元结构及其存储器数组

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3266644B2 (ja) * 1991-04-08 2002-03-18 テキサス インスツルメンツ インコーポレイテツド ゲートアレイ装置
US5420447A (en) * 1993-01-29 1995-05-30 Sgs-Thomson Microelectronics, Inc. Double buffer base gate array cell
US5355008A (en) 1993-11-19 1994-10-11 Micrel, Inc. Diamond shaped gate mesh for cellular MOS transistor array
US6387739B1 (en) 1998-08-07 2002-05-14 International Business Machines Corporation Method and improved SOI body contact structure for transistors
KR20080082426A (ko) * 2007-03-07 2008-09-11 삼성전자주식회사 스태틱 메모리 소자
US8178908B2 (en) 2008-05-07 2012-05-15 International Business Machines Corporation Electrical contact structure having multiple metal interconnect levels staggering one another
KR101852512B1 (ko) * 2012-01-03 2018-04-26 삼성전자주식회사 반도체 소자
TWI620234B (zh) * 2014-07-08 2018-04-01 聯華電子股份有限公司 一種製作半導體元件的方法
US10192875B2 (en) * 2014-10-14 2019-01-29 Ememory Technology Inc. Non-volatile memory with protective stress gate
US9559644B2 (en) 2014-11-03 2017-01-31 Qorvo Us, Inc. Low noise amplifier
JP6648489B2 (ja) 2015-10-30 2020-02-14 セイコーエプソン株式会社 バッファー回路、半導体集積回路装置、発振器、電子機器及び基地局
US9773879B2 (en) * 2015-11-30 2017-09-26 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and a method for fabricating the same
US10062697B2 (en) 2016-02-16 2018-08-28 Samsung Electronics Co., Ltd. Semiconductor device without a break region
US10128365B2 (en) * 2016-03-17 2018-11-13 Cree, Inc. Bypassed gate transistors having improved stability

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101635506A (zh) * 2008-07-22 2010-01-27 株式会社瑞萨科技 半导体集成电路器件
US20130037888A1 (en) * 2011-08-10 2013-02-14 Samsung Electronics Co., Ltd. Semiconductor device
CN107393924A (zh) * 2014-04-02 2017-11-24 力旺电子股份有限公司 具有辅助栅极的非易失性存储单元结构及其存储器数组

Also Published As

Publication number Publication date
CN113097177A (zh) 2021-07-09
CN113097177B (zh) 2023-07-18
US20220059459A1 (en) 2022-02-24
US20200144184A1 (en) 2020-05-07
US20190221518A1 (en) 2019-07-18
CN112968057A (zh) 2021-06-15
US11201115B2 (en) 2021-12-14
US20190221517A1 (en) 2019-07-18
US10600734B2 (en) 2020-03-24
CN112968057B (zh) 2024-02-13
US11476192B2 (en) 2022-10-18
CN110047813A (zh) 2019-07-23
US11658118B2 (en) 2023-05-23

Similar Documents

Publication Publication Date Title
US7977754B2 (en) Poly resistor and poly eFuse design for replacement gate technology
US8697511B2 (en) Method for producing semiconductor device and semiconductor device
CN108257944B (zh) 半导体器件及其制造方法
US9831235B2 (en) Method of making structure having a gate stack
US11342222B2 (en) Self-aligned scheme for semiconductor device and method of forming the same
TWI396254B (zh) 具有區域性內連線的半導體裝置
JP2001156182A (ja) 半導体装置およびその製造方法
US8354343B2 (en) Semiconductor structure and manufacturing method of the same
CN110047813B (zh) 半导体元件
US7723801B2 (en) Semiconductor device and method of fabricating the same, and nor gate circuit using the semiconductor device
US11056487B2 (en) Single diffusion break local interconnect
US9379199B2 (en) Semiconductor device including a contact plug with barrier materials
US6958541B2 (en) Low gate resistance layout procedure for RF transistor devices
US20240063282A1 (en) Semiconductor device on silicon-on-insulator substrate
TW202410202A (zh) 半導體元件
CN111696961B (zh) 半导体结构及其制作方法
KR20100079205A (ko) Ｍｉｍ 커패시터를 가지는 반도체 소자 및 방법
CN118116917A (zh) 一种决定无线射频元件的天线规则的方法
JP2005159347A (ja) 改善されたゲート構成を有する金属酸化膜半導体デバイス
CN110943066A (zh) 具有高电阻晶片的半导体结构及高电阻晶片的接合方法
KR20100079293A (ko) 커패시터 및 그 제조 방법

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant