CN101635506A - 半导体集成电路器件 - Google Patents
半导体集成电路器件 Download PDFInfo
- Publication number
- CN101635506A CN101635506A CN200910149191A CN200910149191A CN101635506A CN 101635506 A CN101635506 A CN 101635506A CN 200910149191 A CN200910149191 A CN 200910149191A CN 200910149191 A CN200910149191 A CN 200910149191A CN 101635506 A CN101635506 A CN 101635506A
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- pad
- semiconductor device
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 96
- 238000009792 diffusion process Methods 0.000 claims description 19
- 230000008878 coupling Effects 0.000 claims description 6
- 238000010168 coupling process Methods 0.000 claims description 6
- 238000005859 coupling reaction Methods 0.000 claims description 6
- 238000006243 chemical reaction Methods 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims description 2
- 230000007704 transition Effects 0.000 claims description 2
- 230000002093 peripheral effect Effects 0.000 abstract description 3
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 239000003990 capacitor Substances 0.000 description 12
- 239000000758 substrate Substances 0.000 description 8
- 102100036285 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Human genes 0.000 description 7
- 101000875403 Homo sapiens 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Proteins 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 238000005538 encapsulation Methods 0.000 description 4
- 238000013517 stratification Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
- H01L27/0218—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of field effect structures
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
Claims (8)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008188144A JP5363044B2 (ja) | 2008-07-22 | 2008-07-22 | 半導体集積回路装置 |
JP2008188144 | 2008-07-22 | ||
JP2008-188144 | 2008-07-22 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101635506A true CN101635506A (zh) | 2010-01-27 |
CN101635506B CN101635506B (zh) | 2016-08-17 |
Family
ID=41568095
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN200910149191.7A Expired - Fee Related CN101635506B (zh) | 2008-07-22 | 2009-06-26 | 半导体集成电路器件 |
Country Status (4)
Country | Link |
---|---|
US (2) | US7872520B2 (zh) |
JP (1) | JP5363044B2 (zh) |
CN (1) | CN101635506B (zh) |
TW (1) | TW201017867A (zh) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110047813A (zh) * | 2018-01-15 | 2019-07-23 | 联华电子股份有限公司 | 半导体元件 |
CN110392922A (zh) * | 2017-03-29 | 2019-10-29 | 株式会社索思未来 | 半导体集成电路装置 |
CN113540071A (zh) * | 2020-04-17 | 2021-10-22 | 爱思开海力士有限公司 | 包括电阻器元件的半导体装置 |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2008082586A2 (en) | 2006-12-28 | 2008-07-10 | Fuller Thomas A | Ex vivo antimicrobial devices and methods |
KR20130092110A (ko) * | 2012-02-10 | 2013-08-20 | 삼성전자주식회사 | 임베디드 솔리드 스테이트 디스크 및 솔리드 스테이트 디스크 |
JP2015170658A (ja) * | 2014-03-05 | 2015-09-28 | マイクロン テクノロジー, インク. | 半導体装置 |
JP2018133503A (ja) * | 2017-02-16 | 2018-08-23 | 東芝メモリ株式会社 | 半導体記憶装置 |
CN112088406B (zh) * | 2020-08-06 | 2023-10-03 | 长江存储科技有限责任公司 | 用于三维存储器的多管芯峰值功率管理 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60152038A (ja) * | 1984-01-20 | 1985-08-10 | Toshiba Corp | GaAsゲ−トアレイ集積回路 |
JP2004193475A (ja) * | 2002-12-13 | 2004-07-08 | Ricoh Co Ltd | 電源用ic及びその電源用icを使用した通信装置 |
CN1630093A (zh) * | 2003-12-18 | 2005-06-22 | 株式会社东芝 | 内置功率mos场效应晶体管和驱动电路的半导体装置 |
US20050250300A1 (en) * | 2004-05-07 | 2005-11-10 | Broadcom Corporation | Low ohmic layout technique for MOS transistors |
JP2007149885A (ja) * | 2005-11-25 | 2007-06-14 | Sanyo Electric Co Ltd | 化合物半導体スイッチ回路装置およびその製造方法 |
CN101207115A (zh) * | 2006-12-20 | 2008-06-25 | 三洋电机株式会社 | 半导体集成电路 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002008374A (ja) * | 2000-06-22 | 2002-01-11 | Mitsubishi Electric Corp | 電圧降圧回路 |
US7728565B2 (en) * | 2007-11-12 | 2010-06-01 | Itt Manufacturing Enterprises, Inc. | Non-invasive load current sensing in low dropout (LDO) regulators |
-
2008
- 2008-07-22 JP JP2008188144A patent/JP5363044B2/ja not_active Expired - Fee Related
-
2009
- 2009-06-01 US US12/475,867 patent/US7872520B2/en active Active
- 2009-06-26 TW TW098121504A patent/TW201017867A/zh unknown
- 2009-06-26 CN CN200910149191.7A patent/CN101635506B/zh not_active Expired - Fee Related
-
2010
- 2010-12-28 US US12/980,140 patent/US8063695B2/en active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60152038A (ja) * | 1984-01-20 | 1985-08-10 | Toshiba Corp | GaAsゲ−トアレイ集積回路 |
JP2004193475A (ja) * | 2002-12-13 | 2004-07-08 | Ricoh Co Ltd | 電源用ic及びその電源用icを使用した通信装置 |
US7209770B2 (en) * | 2002-12-13 | 2007-04-24 | Ricoh Company, Ltd. | Power supply IC having switching regulator and series regulator |
CN1630093A (zh) * | 2003-12-18 | 2005-06-22 | 株式会社东芝 | 内置功率mos场效应晶体管和驱动电路的半导体装置 |
US20050250300A1 (en) * | 2004-05-07 | 2005-11-10 | Broadcom Corporation | Low ohmic layout technique for MOS transistors |
JP2007149885A (ja) * | 2005-11-25 | 2007-06-14 | Sanyo Electric Co Ltd | 化合物半導体スイッチ回路装置およびその製造方法 |
CN101207115A (zh) * | 2006-12-20 | 2008-06-25 | 三洋电机株式会社 | 半导体集成电路 |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110392922A (zh) * | 2017-03-29 | 2019-10-29 | 株式会社索思未来 | 半导体集成电路装置 |
CN110392922B (zh) * | 2017-03-29 | 2022-09-30 | 株式会社索思未来 | 半导体集成电路装置 |
CN110047813A (zh) * | 2018-01-15 | 2019-07-23 | 联华电子股份有限公司 | 半导体元件 |
CN110047813B (zh) * | 2018-01-15 | 2021-04-06 | 联华电子股份有限公司 | 半导体元件 |
CN112968057A (zh) * | 2018-01-15 | 2021-06-15 | 联华电子股份有限公司 | 半导体元件 |
US11201115B2 (en) | 2018-01-15 | 2021-12-14 | United Microelectronics Corp. | Semiconductor device |
US11476192B2 (en) | 2018-01-15 | 2022-10-18 | United Microelectronics Corp. | Transistor structure in low noise amplifier |
US11658118B2 (en) | 2018-01-15 | 2023-05-23 | United Microelectronics Corp. | Transistor structure in low noise amplifier |
CN112968057B (zh) * | 2018-01-15 | 2024-02-13 | 联华电子股份有限公司 | 半导体元件 |
CN113540071A (zh) * | 2020-04-17 | 2021-10-22 | 爱思开海力士有限公司 | 包括电阻器元件的半导体装置 |
Also Published As
Publication number | Publication date |
---|---|
JP5363044B2 (ja) | 2013-12-11 |
US8063695B2 (en) | 2011-11-22 |
TW201017867A (en) | 2010-05-01 |
US7872520B2 (en) | 2011-01-18 |
US20100019835A1 (en) | 2010-01-28 |
JP2010027883A (ja) | 2010-02-04 |
US20110090001A1 (en) | 2011-04-21 |
CN101635506B (zh) | 2016-08-17 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
ASS | Succession or assignment of patent right |
Owner name: RENESAS ELECTRONICS Free format text: FORMER OWNER: RENESAS TECHNOLOGY CORP. Effective date: 20100917 |
|
C41 | Transfer of patent application or patent right or utility model | ||
COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: TOKYO, JAPAN TO: KANAGAWA PREFECTURE, JAPAN |
|
TA01 | Transfer of patent application right |
Effective date of registration: 20100917 Address after: Kanagawa Applicant after: Renesas Electronics Corporation Address before: Tokyo, Japan, Japan Applicant before: Renesas Technology Corp. |
|
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
CB02 | Change of applicant information |
Address after: Tokyo, Japan, Japan Applicant after: Renesas Electronics Corporation Address before: Kanagawa Applicant before: Renesas Electronics Corporation |
|
COR | Change of bibliographic data | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20160817 Termination date: 20180626 |