CN112968057B - 半导体元件 - Google Patents

半导体元件 Download PDF

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CN112968057B
CN112968057B CN202110265888.1A CN202110265888A CN112968057B CN 112968057 B CN112968057 B CN 112968057B CN 202110265888 A CN202110265888 A CN 202110265888A CN 112968057 B CN112968057 B CN 112968057B
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gate line
doped region
semiconductor device
gate
region
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CN112968057A (zh
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马瑞吉
林家辉
杨国裕
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United Microelectronics Corp
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Abstract

本发明公开一种半导体元件，其主要包含一第一栅极线以及一第二栅极线沿着一第一方向延伸、一第三栅极线沿着一第二方向延伸并设于第一栅极线以及第二栅极线之间以及一漏极区域设于第三栅极线一侧，其中第三栅极线包含一第一突出部且该第一突出部重叠漏极区域。

Description

半导体元件
本发明是中国发明专利申请(申请号：201810035168.4，申请日：2018年01月15日，发明名称：半导体元件)的分案申请。
技术领域
本发明设计一种半导体元件，尤其是设计一种应用于低噪声放大器(Low NoiseAmplifier,LNA)的晶体管结构。
背景技术
随着科技的发展，无线通讯已成为人们生活中相当重要的一环，各种不同电子装置如智能型手机、智能型穿戴装置、平板计算机中通过无线射频系统来传送或接收无线信号。在无线射频系统中，低噪声放大器(Low Noise Amplifier,LNA)与功率放大器(PowerAmplifier,PA)为必要的放大电路。为了使放大电路具有最佳的效能(如线性度)，放大电路需要施加以一适当偏压，常见的作法为将放大电路电连接于一偏压模块，利用偏压模块来提供放大电路一适当偏压。
然而在现有技术中，例如低噪声放大器中的晶体管设计在部分参数上包括高栅极阻值、高栅极对基体掺杂区电容值(gate to body capacitance)以及最低噪声指数(minnoise figure)的表现仍不尽理想。由于这些参数在低噪声放大器效能表面上具有举足轻重的影响，因此如何改良现有晶体管架构进而改善这些参数表现即为现今一重要课题。
发明内容
本发明一实施例揭露一种半导体元件，其主要包含一第一栅极线以及一第二栅极线沿着一第一方向延伸、一第三栅极线沿着一第二方向延伸并设于第一栅极线以及第二栅极线之间以及一漏极区域设于第三栅极线一侧，其中第三栅极线包含一第一突出部且该第一突出部重叠漏极区域。
附图说明
图1为本发明一实施例的应用于低噪声放大器的一半导体元件的上视图；
图2为本发明一实施例的应用于低噪声放大器的一半导体元件的上视图。
主要元件符号说明
12 基底 14 第一栅极线
16 第二栅极线 18 第三栅极线
20 第四栅极线 22 第五栅极线
24 第六栅极线 26 源极区域
28 第一漏极区域 30 第二漏极区域
32 掺杂区 34 掺杂区
36 掺杂区 38 掺杂区
40 掺杂区 42 掺杂区
44 掺杂区 46 掺杂区
48 掺杂区 50 接触插塞
52 第一金属内连线 54 第二金属内连线
56 第三金属内连线
62 基底 64 第一栅极线
66 第二栅极线 68 第三栅极线
70 第四栅极线 72 第五栅极线
74 第一源极区域 76 第一漏极区域
78 第二源极区域 80 第二漏极区域
82 掺杂区 84 掺杂区
86 掺杂区 88 掺杂区
90 掺杂区 92 掺杂区
94 掺杂区 96 掺杂区
98 突出部 100 突出部
102 突出部 104 接触插塞
106 第一金属内连线 108 第二金属内连线
110 第三金属内连线 112 第四金属内连线
具体实施方式
请参照图1，图1为本发明一实施例的应用于低噪声放大器的一半导体元件的上视图。如图1所示，半导体元件主要包含多条栅极线，包括第一栅极线14、第二栅极线16、第三栅极线18、第四栅极线20、第五栅极线22以及第六栅极线24设于一基底12上，其中基底12较佳为一硅覆绝缘(silicon-on-insulator,SOI)基底，例如可细部包含第一半导体层、一绝缘层设于第一半导体层上以及第二半导体层设于绝缘层上，其中第一半导体层以及第二半导体层可包含例如硅、锗或锗或硅等半导体材料而绝缘层可包含例如氧化硅等绝缘材料。
从细部来看，第一栅极线14以及第二栅极线16沿着第一方向(例如X方向)延伸，第三栅极线18以及第四栅极线20同样沿着第一方向延伸并设于第一栅极线以及第二栅极线之间，第五栅极线22以及第六栅极线24则沿着第二方向(例如Y方向)延伸，其中第五栅极线22以及第六栅极线24设于第一栅极线14以及第二栅极线16之间并交错第三栅极线18以及第四栅极线20。
此外，半导体元件又包含一源极区域26设于第五栅极线22以及第六栅极线24之间，第一漏极区域28设于第五栅极线22一侧以及第二漏极区域30设于第六栅极线24一侧。更具体而言，源极区域26较佳沿着第二方向延伸且更细部包含掺杂区32、掺杂区34以及掺杂区36，其中掺杂区32位于第一栅极线12以及第三栅极线18之间，掺杂区34位于第三栅极线18以及第四栅极线20之间，掺杂区36则位于第二栅极线16以及第四栅极线20之间。如同源极区域26，第一漏极区域28沿着第二方向延伸且更细部包含掺杂区38、掺杂区40以及掺杂区42，其中掺杂区38位于第一栅极线12以及第三栅极线18之间，掺杂区40位于第三栅极线18以及第四栅极线20之间，掺杂区42则位于第二栅极线16以及第四栅极线20之间。另外第二漏极区域30也较佳沿着第二方向延伸且更细部包含掺杂区44、掺杂区46以及掺杂区48，其中掺杂区44位于第一栅极线12以及第三栅极线18之间，掺杂区46位于第三栅极线18以及第四栅极线20之间，掺杂区48则位于第二栅极线16以及第四栅极线20之间。
在本实施例中，第一栅极线12与第三栅极线18之间的掺杂区32、38、44以及第二栅极线16与第四栅极线20之间的掺杂区36、42、48较佳包含相同导电型式或第一导电型式，第三栅极线18以及第四栅极线20之间的掺杂区34、40、46则包含第二导电型式，其中本实施例的第一导电型式较佳为N型而第二导电型式则为P型。但不局限于此，依据本发明其他实施例第一导电型式又可为P型而第二导电型式为N型，此实施例也属本发明所涵盖的范围。
另外本实施例各栅极线或栅极结构，包括第一栅极线14、第二栅极线16、第三栅极线18、第四栅极线20、第五栅极线22以及第六栅极线24均可依据制作工艺需求以先栅极(gate first)制作工艺、后栅极(gate last)制作工艺的先高介电常数介电层(high-kfirst)制作工艺以及后栅极制作工艺的后高介电常数介电层(high-k last)制作工艺等方式制作完成，而为一一体成型的结构。换句话说，各栅极线可依据制作工艺或产品需求为多晶硅所构成的多晶硅栅极线，或可经由金属栅极置换(replacement metal gate,RMG)制作工艺将原本由多晶硅所构成的栅极线转换为金属栅极线，这两种变化型均属本发明所涵盖的范围。由于多晶硅栅极线以及金属栅极线的制作均属本领域所熟知技术，在此不另加赘述。
此外，半导体元件又包含多个接触插塞50设于第一栅极线14、第二栅极线16、源极区域26、第一漏极区域28以及第二漏极区域30。其中接触插塞50的制作可先形成一层间介电层(图未示)于基底12上，然后进行一图案转移制作工艺，例如可利用一图案化掩模去除各栅极线旁的部分的层间介电层以形成多个接触洞(图未示)并暴露出下面的第一栅极线14、第二栅极线16、源极区域26、第一漏极区域28以及第二漏极区域30。随后于各接触洞中填入所需的金属材料，例如包含钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)等的阻障层材料以及选自钨(W)、铜(Cu)、铝(Al)、钛铝合金(TiAl)、钴钨磷化物(cobalt tungstenphosphide，CoWP)等低电阻材料或其组合的低阻抗金属层。接着进行一平坦化制作工艺，例如以化学机械研磨制作工艺去除部分金属材料以分别形成接触插塞50于各接触洞内电连接第一栅极线14、第二栅极线16、源极区域26、第一漏极区域28以及第二漏极区域30。
之后可进行后续金属内连线制作工艺以于层间介电层上形成金属间介电层(图未示)以及金属内连线分别连接各接触插塞50。在本实施例中，半导体元件主要包含第一金属内连线52沿着第二方向延伸于第五栅极线22以及第六栅极线24之间并电连接源极区域26、第二金属内连线54沿着第二方向延伸于第五栅极线22一侧并电连接第一漏极区域28以及第三金属内连线56沿着第二方向延伸于第六栅极24线一侧并电连接第二漏极区域30，其中第一金属内连线52、第二金属内连线54以及第三金属内连线56交错第三栅极线18以及第四栅极线20。
请再参照图2，图2为本发明一实施例的应用于低噪声放大器的一半导体元件的上视图。如图2所示，半导体元件主要包含多条栅极线，包括第一栅极线64、第二栅极线66、第三栅极线68、第四栅极线70以及第五栅极线72设于一基底62上，其中基底62较佳为一硅覆绝缘(silicon-on-insulator,SOI)基底，例如可细部包含第一半导体层、一绝缘层设于第一半导体层上以及第二半导体层设于绝缘层上，其中第一半导体层以及第二半导体层可包含例如硅、锗或锗或硅等半导体材料而绝缘层可包含例如氧化硅等绝缘材料。
在本实施例中，第一栅极线64以及第二栅极线66沿着第一方向(例如X方向)延伸，第三栅极线68、第四栅极线70以及第五栅极线72则沿着第二方向(例如Y方向)延伸。此外，半导体元件又包含一第一源极区域74设于第三栅极线68一侧，第一漏极区域76设于第三栅极68线以及第四栅极线70之间、第二源极区域78设于第四栅极线70以及第五栅极线72之间以及第二漏极区域80设于第五栅极线72一侧。更具体而言，第一源极区域74较佳沿着第二方向延伸且更细部包含掺杂区82、掺杂区84以及掺杂区86，第一漏极区域76是沿着第二方向延伸且更细部包含掺杂区88，第二源极区域78是沿着第二方向延伸且更细部包含掺杂区90、掺杂区92以及掺杂区94，第二漏极区域80是沿着第二方向延伸且更细部包含掺杂区96。
值得注意的是，第三栅极线68较佳包含一突出部98重叠或覆盖部分第一漏极区域76，第四栅极线70较佳包含一突出部100重叠部分第一漏极区域，且第五栅极线72包含一第一突出部102重叠部分第二漏极区域80。更具体而言，第三栅极线68以及第四栅极线70的突出部98、100较佳为对称设计且第三栅极线68以及第四栅极线70的对称突出部结构可被重复拷贝至左右两侧所有的栅极线。举例来说，本实施例虽仅于第四栅极线70右侧绘示出一条第五栅极线72具有类似的突出部102，但第五栅极线72右侧又可比照第四栅极线70的突出部100态样设置另一条具有与第四栅极线70相同突出部100的第六栅极线(图未示)，使第五栅极线72的突出部102以及第六栅极线的突出部同时重叠部分第二漏极区域80。
另外在本实施例中，第一源极区域74的掺杂区82、86、第一漏极区域76的掺杂区88、第二源极区域78的掺杂区90、94以及第二漏极区域80的掺杂区96较佳包含相同导电型式或第一导电型式，第一源极区域74的掺杂区84以及第二源极区域78的掺杂区92则包含第二导电型式，其中本实施例的第一导电型式较佳为N型而第二导电型式则为P型。但不局限于此，依据本发明其他实施例第一导电型式又可为P型而第二导电型式为N型，此实施例也属本发明所涵盖的范围。
如同前述实施例，各栅极线或栅极结构，包括第一栅极线64、第二栅极线66、第三栅极线68、第四栅极线70以及第五栅极线72均可依据制作工艺需求以先栅极(gate first)制作工艺、后栅极(gate last)制作工艺的先高介电常数介电层(high-k first)制作工艺以及后栅极制作工艺的后高介电常数介电层(high-k last)制作工艺等方式制作完成。换句话说，各栅极线可依据制作工艺或产品需求为多晶硅所构成的多晶硅栅极线，或可经由金属栅极置换(replacement metal gate,RMG)制作工艺将原本由多晶硅所构成的栅极线转换为金属栅极线，这两种变化型均属本发明所涵盖的范围。由于多晶硅栅极线以及金属栅极线的制作均属本领域所熟知技术，在此不另加赘述。
此外，半导体元件又包含多个接触插塞104设于第一栅极线64、第二栅极线66、第一源极区域74、第一漏极区域76、第二源极区域78以及第二漏极区域80。其中接触插塞104的制作可先形成一层间介电层(图未示)于基底12上，然后进行一图案转移制作工艺，例如可利用一图案化掩模去除各栅极线旁的部分的层间介电层以形成多个接触洞(图未示)并暴露出下面的源极区域、第一漏极区域20以及第二漏极区域24。随后于各接触洞中填入所需的金属材料，例如包含钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)等的阻障层材料以及选自钨(W)、铜(Cu)、铝(Al)、钛铝合金(TiAl)、钴钨磷化物(cobalt tungsten phosphide，CoWP)等低电阻材料或其组合的低阻抗金属层。接着进行一平坦化制作工艺，例如以化学机械研磨制作工艺去除部分金属材料以分别形成接触插塞104于各接触洞内电连接第一栅极线64、第二栅极线66、第一源极区域74、第一漏极区域76、第二源极区域78以及第二漏极区域80。
之后可进行后续金属内连线制作工艺以于层间介电层上形成金属间介电层(图未示)以及金属内连线分别连接各接触插塞104。在本实施例中，半导体元件主要包含第一金属内连线106沿着第二方向延伸于第三栅极线68以及第四栅极线70之间并电连接第一漏极区域76、第二金属内连线108沿着第二方向延伸于第三栅极线68一侧并电连接第一源极区域74、第三金属内连线110沿着第二方向延伸于第四栅极线70以及第五栅极线72之间并电连接第二源极区域78以及第四金属内连线112沿着第二方向延伸于第五栅极线72一侧并电连接第二漏极区域80。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (8)

1.一种半导体元件，其特征在于，包含：
第一栅极线以及第二栅极线，沿着第一方向延伸；
第三栅极线，沿着第二方向延伸并设于该第一栅极线以及该第二栅极线之间，其中该第三栅极线包含第一突出部；
第四栅极线，沿着第二方向延伸并设于该第一栅极线以及该第二栅极线之间，其中该第四栅极线包含第二突出部，所述第二突出部朝向所述第一突出部突出，第一突出部与第二突出部为对称结构，第一突出部沿着第一方向延伸的第一边与第二边分别切齐第二突出部沿着第一方向延伸的第一边与第二边，且第一栅极线与第二栅极线由第三栅极线一侧沿着第一方向不间断延伸至第四栅极线另一侧；以及
漏极区域，设于该第三栅极线和第四栅极线之间，其中该第三栅极线的该第一突出部以及该第四栅极线的第二突出部重叠该漏极区域；且
所述第一突出部和第二突出部在第一方向上间隔开。
2.如权利要求1所述的半导体元件，另包含第一源极区域，设于该第三栅极线另一侧以及第二源极区域设于该第四栅极线另一侧。
3.如权利要求2所述的半导体元件，另包含：
第一金属内连线，沿着该第二方向延伸于该第三栅极线以及该第四栅极线之间并电连接该漏极区域；
第二金属内连线，沿着该第二方向延伸于该第三栅极线另一侧并电连接该第一源极区域；以及
第三金属内连线，沿着该第二方向延伸于该第四栅极线另一侧并电连接该第二源极区域。
4.如权利要求1所述的半导体元件，另包含第一掺杂区，设于该第三栅极线另一侧。
5.如权利要求4所述的半导体元件，另包含第二掺杂区，设于该第一掺杂区上方。
6.如权利要求5所述的半导体元件，其中该第一掺杂区以及该第二掺杂区包含不同导电型式。
7.如权利要求4所述的半导体元件，另包含第三掺杂区，设于该第一掺杂区下方。
8.如权利要求7所述的半导体元件，其中该第一掺杂区以及该第三掺杂区包含不同导电型式。
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