CN107393924A - 具有辅助栅极的非易失性存储单元结构及其存储器数组 - Google Patents

具有辅助栅极的非易失性存储单元结构及其存储器数组 Download PDF

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CN107393924A
CN107393924A CN201611041736.9A CN201611041736A CN107393924A CN 107393924 A CN107393924 A CN 107393924A CN 201611041736 A CN201611041736 A CN 201611041736A CN 107393924 A CN107393924 A CN 107393924A
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volatile memory
memory array
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曹沐潆
陈纬仁
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eMemory Technology Inc
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Abstract

本发明公开了一种非易失性存储器数组，包含多条字线，沿着第一方向延伸、多条位线，沿着第二方向延伸以及多条源极线。各非易失性存储单元包含P型金氧半选择晶体管以及与P型金氧半选择晶体管串联的P型金氧半浮动栅极晶体管。各字线电连接至P型金氧半选择晶体管的选择栅极。各位线电连接至各非易失性存储单元中的P型金氧半浮动栅极晶体管的掺杂区。各源极线电连接至P型金氧半选择晶体管的掺杂区。

Description

具有辅助栅极的非易失性存储单元结构及其存储器数组
技术领域
本发明涉及非易失性存储器(NVM)元件领域，特别是一种具有辅助栅极的单层多晶硅非易失性存储单元结构及其非易失性存储器数组。
背景技术
非易失性存储器(NVM)元件，例如广泛使用在电子装置中贮存数据的电子擦除式可程序化只读存储器(EEPROM)和闪存(flash memory)，具有可电子擦除数据和再程序化特性，而且在关闭电源的情况下，数据仍可留存。非易失性存储器元件大致上分成多次程序化存储器(MTP)和单次程序化存储器(OTP)。多次程序化存储器(MTP)可多次读取和程序化，例如电子擦除式可程序化只读存储器和闪存被设计具有相关的电子电路，可支持不同的操作，例如程序化，擦除和读取。单次程序化存储器(OTP)具有程序化和读取功能的电子电路，但并不具备擦除功能的电子电路。
单层多晶硅非易失性存储器结构因为可减少额外工艺步骤而被提出来。单层多晶硅非易失性存储器用单层多晶硅形成贮存电荷的浮动栅极，可和一般互补式金氧半导体场效晶体管(CMOS)工艺兼容，因此可应用在嵌入式存储器、混和模式电路的嵌入式非易失性存储器，以及微控制器(例如系统单芯片，SOC)等领域。
目前已知可用热电子注入(又称为通道热电子CHE)技术来程序化存储器。程序化和验证运算时的漏电流问题，随着核心元件尺寸缩小而恶化。並且，随着闪存元件微缩及存储单元的通道长度缩小，相邻元件引起的程序化干扰也会增加。当程序化时，干扰会发生在共享同一字线的相邻存储单元之间。另外，随着存储单元单位的尺寸和隧穿氧化层持续微缩，保存资料的遗失和浮动栅极的电荷漏泄问题逐渐严重。因此，业界对于改善非易失性存储器的数据保存能力或耐久度有强烈的需求。
发明内容
本发明的目的是提供一具有辅助栅极的改良单层多晶硅非易失性存储单元结构及其非易失性存储器数组，可达到更好的耐久度、较大开/关容许范围、减少程序化电流(可减少约20％)、降低程序化电压，以及减少程序化干扰。
根据本发明一实施例，本发明提出一种非易失性存储器数组，包含多个非易失性存储单元，其中各非易失性存储单元包含一半导体衬底，其中具有第一N型阱区；一第一氧化物定义区及一第二氧化物定义区，设置在所述半导体衬底内；一P型金氧半选择晶体管，设置在第一氧化物定义区上，其中P型金氧半选择晶体管包含一选择栅极、一第一P+源极掺杂区，位于第一N型阱区，以及一第二P+源极掺杂区与第一P+源极掺杂区分隔开；一P型金氧半浮动栅极晶体管，与P型金氧半选择晶体管串联，并且设置在第一氧化物定义区上，其中P型金氧半浮动栅极晶体管包含一浮动栅极，覆盖第一氧化物定义区、第二P+源极掺杂区，以及一第三P+源极掺杂区与第二P+源极掺杂区分隔开，其中P型金氧半浮动栅极晶体管是非易失性存储单元的电荷贮存元件；以及一辅助栅极，自浮动栅极凸出至第二氧化物定义区的一边，使得辅助栅极与第二氧化物定义区电容耦合，其中辅助栅极与浮动栅极由单层多晶硅一体构成。
所述非易失性存储器数组另包含多条字线，沿着第一方向延伸，其中各字线电连接至各非易失性存储单元中的P型金氧半选择晶体管的选择栅极。
所述非易失性存储器数组另包含多条位线，沿着第二方向延伸，其中各位线电连接至各非易失性存储单元中的P型金氧半浮动栅极晶体管的第三P+源极掺杂区。
所述非易失性存储器数组另包含多条源极线，其中源极线电连接至各非易失性存储单元中的P型金氧半选择晶体管的第一P+源极掺杂区。
为让本发明的上述目的、特征及优点能更明显易懂，下文特举优选实施方式，并配合附图，作详细说明如下。然而如下的优选实施方式与附图仅供参考与说明用，并非用来对本发明加以限制。
附图说明
附图包括对本发明的实施例提供进一步的理解，及被并入且构成说明书中的一部份。附图说明一些本发明的实施例，并与说明书一起用于解释其原理。
图1是本发明一实施例俯视图，是一单层多晶硅非易失性存储单元元件；
图2是沿图1切线I-I’截取的示意性剖面图；
图3是沿图1切线II-II’截取的示意性剖面图；
图4是沿图1切线III-III’截取的示意性剖面图；
图5和图6分别说明图1所示存储单元的等效电路，并例示程序化(PGM)、读取(READ)及擦除(ERS)时的操作条件；
图7说明由图1所示非易失性存储单元所组成的存储器数组局部布局；
图8说明由图1所示非易失性存储单元所组成的存储器数组局部布局，其中例示了源极线、位线、辅助栅极线和擦除线；
图9是根据本发明的一实施例所绘示包含如图8所示的存储器数组的等效电路图；
图10说明根据本发明的另一实施例所绘示的数组结构；
图11是根据本发明的另一实施例所绘示的数组结构，其中第二氧化物定义区位于N型阱区外；
图12是根据本发明的另一实施例所绘示的数组结构，其中FG、AG和EG沿着第二方向对准；
图13是根据本发明的另一实施例所绘示的数组结构，其中FG、AG和EG沿着第二方向对准，且其中第二氧化物定义区位于N型阱区外；以及
图14是根据本发明的另一实施例所绘示的数组结构，其中四个非易失性存储单元共享一个AG耦合区域(第二氧化物定义区)。
须注意的是所有附图均是示意图，以说明和制图方便为目的，相对尺寸及比例都经过调整。相同的符号在不同的实施例中代表相对应或类似的特征。
其中，附图标记说明如下：
1 非易失性存储单元
210 第一氧化物定义(OD)区
220 第二氧化物定义(OD)区
230 第三氧化物定义(OD)区
100 半导体衬底
200 隔离区
110 N型阱(NW)区
120 P型阱(PW)区
10 选择晶体管
20 浮动栅极晶体管
12 P+源极掺杂区
SL 源极线
14 P+掺杂区
32 选择栅极(SG)通道区
2 选择栅极(SG)
WL 字线
2a 栅极介电层
4 浮动栅极(FG)
16 P+汲极掺杂区
BL 位线
4a 栅极介电层
34 浮动栅极通道区
6 辅助栅极(AG)
18 N+掺杂区
6a 水平区段
6b 垂直区段
8 擦除栅极(EG)
19 N+掺杂区
EL 擦除线
1a 非易失性存储单元
1b 非易失性存储单元
80 中心线
3 存储器数组
180 N型阱区拾取接点
190 接触点
C1 非易失性存储单元
C2 非易失性存储单元
C3 非易失性存储单元
C4 非易失性存储单元
90 水平中心线
具体实施方式
借由接下来的叙述及所提供的众多特定细节，可充分了解本发明。然而对于本领域中的技术人员，在没有这些特定细节下依然可实行本发明。並且，一些本领域中公知的系统配置和工艺步骤并未在此详述，因为这些应是本领域中的技术人员所熟知的。在不悖离本发明的范围内，可做结构、逻辑和电性上的修改并应用在其他实施例上。
同样地，实施例的附图是示意图，并未照实际比例绘制，为了清楚呈现而放大一些尺寸。在此公开和描述的多个实施例中若具有共通或类似的某些特征时，为了方便图示及描述，类似的特征通常会以相同的标号表示。
用语“氧化物定义(oxide define,OD)区”在本技术领域中普遍认为是一衬底上硅质主表面的某一区域，通常是局部硅氧化(LOCOS)或浅沟道绝缘(STI)区域以外的区域。用语“氧化物定义(OD)区”也普遍可被认为是形成及操作有源电路元件例如晶体管的“有源区域”。
图1至图4是根据本发明一实施例所绘示的单层多晶硅非易失性存储单元示意图。图1是根据本发明一实施例所绘示的单层多晶硅非易失性存储单元的布局平面图。图2是沿着图1切线I-I’方向截取的示意性剖面图。图3是沿着图1切线II-II’方向截取的示意性剖面图。图4是沿着图1切线III-III’方向截取的示意性剖面图。所例示的非易失性存储单元结构可作为多次程序化存储器(MTP)单元。应了解的是本发明也可应用于其他存储器元件。
如图1所示，非易失性存储单元1包含三个被分隔开但彼此紧密排列的氧化物定义(OD)区，包含有一第一氧化物定义(OD)区210、一第二氧化物定义(OD)区220和一第三氧化物定义(OD)区230，由形成在一半导体衬底100(例如P型掺杂硅衬底P-Sub)主表面的隔离区200分隔开。根据此实施例，隔离区200可为浅沟道绝缘(STI)区，但不仅限于此。应了解图1的布局仅是示意图。
根据本发明实施例，第一氧化物定义(OD)区210及第二氧化物定义(OD)区220位于N型阱(NW)区110内，第三氧化物定义(OD)区230位于P型阱(PW)区120内。
由图1和图2可知，非易失性存储单元1包含一选择晶体管10和一与选择晶体管10串联的浮动栅极晶体管20，直接形成在第一氧化物定义(OD)区210上。根据本发明实施例，选择晶体管10是P型金氧半导体(P型金氧半)晶体管，包含一P+源极掺杂区12(与一源极线SL耦合)位于N型阱(NW)区110中；一与P+源极掺杂区12分隔开的共享P+掺杂区14；一选择栅极(SG)通道区32，位在P+源极掺杂区12和共享P+掺杂区14之间并接近半导体衬底100主要表面；一选择栅极(SG)2覆盖在选择栅极通道区32上，并与字线(WL)耦合；一栅极介电层2a，位于选择栅极(SG)2和选择栅极通道区32之间。间隙壁(图未示)可以形成在选择栅极2的相对侧壁上。
一浮动栅极晶体管20直接位于第一氧化物定义(OD)区210上。浮动栅极晶体管20借由共享P+掺杂区14与选择晶体管10链接。浮动栅极晶体管20与选择晶体管10分享共享P+掺杂区14，因而形成两串联的晶体管，在此实施例中，是两串联的P型金氧半晶体管。
浮动栅极晶体管20包含一浮动栅极(FG)4，覆盖在第一氧化物定义(OD)区210上。根据本发明实施例，浮动栅极4由单层多晶硅构成，例如N+掺杂多晶硅或P+掺杂多晶硅，且浮动栅极晶体管20是非易失性存储单元1的电荷贮存元件。选择栅极(SG)2和浮动栅极(FG)4均是直线型，沿着一第1方向(参考x轴方向)延伸。
浮动栅极晶体管20另包含共享P+掺杂区14，位于浮动栅极4的一边，一P+汲极掺杂区16位于另外一边，且与位线(BL)耦合；一浮动栅极通道区34介于共享P+掺杂区14和P+汲极掺杂区16之间；以及一栅极介电层4a位于浮动栅极4与浮动栅极通道区34之间。根据本发明实施例，栅极介电层4a的厚度与栅极介电层2a的厚度一致，且选择晶体管10与浮动栅极晶体管20共享N型阱区110。
由图1和图3可知，根据本发明实施例，非易失性存储单元1另包含一辅助栅极(AG)6，自浮动栅极4一末端延伸凸出至第二氧化物定义(OD)区220的一边，且与第二氧化物定义(OD)区220及N型阱区110电容耦合。由上方俯视，辅助栅极(AG)6部分重叠第二氧化物定义(OD)区220，且部分重叠面对第一氧化物定义(OD)区210的边缘。
在第二氧化物定义(OD)区220未被辅助栅极(AG)6覆盖的区域形成一N+掺杂区18，N+掺杂区18作为N型阱区拾取接点并位于第二氧化物定义(OD)区220，经由N+掺杂区18提供N型阱区110一N型阱区电压(VNW)。根据本发明实施例，辅助栅极(AG)6与N型阱区110之间不需要额外的掺杂区或离子井区。可借由N型阱区电压(VNW)控制一耦合至辅助栅极(AG)6的感应电压。上述感应电压是由于辅助栅极(AG)6与偏压下的N型阱区110之间的耦合效应所产生的，将在程序化操作时产生更多的载子注入至浮动栅极，使得写入效率可以提升。辅助栅极(AG)6可由N+掺杂多晶硅或P+掺杂多晶硅构成。
根据本发明实施例，辅助栅极(AG)6包含一水平区段6a，自浮动栅极(FG)4沿第1方向(参考x轴方向)连续延伸出，并直接与浮动栅极(FG)4相连。辅助栅极(AG)6另包含一垂直区段6b，沿第2方向(参考y轴方向)延伸出，并直接与水平区段6a相连。
根据本发明实施例，辅助栅极(AG)6与浮动栅极(FG)4是一体形成，并在同一工艺步骤中定义完成。辅助栅极(AG)6可借由N型阱区110自动偏压，如此可以增加耦合率和程序化效率，也可减少程序化干扰和降低程序化电流/电压。另外，非易失性存储单元1可抑制IOFF和IOFF电流上升问题，因而达到较大的耐久性和开/关容忍度。辅助栅极(AG)6提供浮动栅极晶体管20额外能力来补偿耦合比，因而可较有效的控制通道。
由图1和图4可知，根据本发明实施例，非易失性存储单元1另包含一擦除栅极(EG)8，自垂直区段6b沿着第二方向(参考y轴方向)连续延伸出去，且横越N型阱区110和P型阱区120的接合处。根据本发明实施例，擦除栅极(EG)8一末端重叠P型阱区120内的第三氧层定义(OD)区230，借由这样的结构，擦除栅极(EG)8可与第三氧层定义(OD)区230及P型阱区120电容耦合。一N+掺杂区19位于第三氧层定义(OD)区230未被擦除栅极(EG)8覆盖的区域上。
图5和图6分别说明图1中的存储单元单位的等效电路并例示程序化(PGM)、读取(READ)及擦除(ERS)时的操作条件。根据图5和图6所示，在程序化(PGM)操作时，选择栅极(SG)2与一字线电压VWL＝VDD连接；擦除线(EL)与一擦除线电压VEL＝VDD连接；源极线(SL)与一源极线电压VSL＝VPP连接；位线(BL)接地(VBL＝0V)；N型阱(NW)区110与一N型阱区电压VNW＝VPP连接；P型阱区(PW)120与一P型阱区电压VPW＝0V连接。根据本发明实施例，VPP与VEE可在2V至15V之间，VDD可在2V至10V之间。在上述操作条件下，非易失性存储单元1可借由通道热电子注入(CHEI)机制被程序化。
在擦除(ERS)操作时，选择栅极(SG)2与一字线电压VWL＝0V连接；擦除线(EL)与一擦除线电压VEL＝VEE连接；源极线(SL)与一源极线电压VSL＝0V连接；位线(BL)接地(VBL＝0V)；N型阱(NW)区110与一N型阱区电压VNW＝0V连接；P型阱区(PW)120与一P型阱区电压VPW＝0V连接。根据本发明实施例，VPP与VEE可在2V至15V之间，VDD可在2V至10V之间。在上述操作条件下，非易失性存储单元1可借由Fowler Nordheim(FN)机制被擦除。
在读取(READ)操作时，选择栅极(SG)2与一字线电压VWL＝0V连接；擦除线(EL)与一擦除线电压VEL＝0V连接；源极线(SL)与一源极线电压VSL＝VDD连接；位线(BL)接地(VBL＝0V)；N型阱(NW)区110与一N型阱区电压VNW＝VDD连接；P型阱区(PW)120与一P型阱区电压VPW＝0V连接。根据本发明实施例，VPP与VEE可为2V至15V之间，VDD可为2V至10V之间。
图7说明由图1所示非易失性存储单元1所组成的存储器数组局部布局。如图7所示，存储器数组包含至少一非易失性存储单元1a及一非易失性存储单元1b。非易失性存储单元1a即是图1所示结构，而非易失性存储单元1b则是其对于中心线80的镜像对称。
图8说明由图7所示非易失性存储单元1a及1b所组成的存储器数组3局部布局，其中例示了源极线(SL)、位线(BL)、N型阱(辅助栅极)线和擦除线(EL)。图9是根据本发明一实施例所绘示包含如图8所示的存储器数组3的等效电路图。在图8中，存储器数组3包括八个非易失性存储单元。在图9的等效电路图中仅例示四个非易失性存储单元。
如图8及图9所示，在同一行的非易失性存储单元的选择栅极包括但不限于非易失性存储单元1a和1b，电连接至同一字线(WL)。应理解的是，字线可以与非易失性存储单元的选择栅极一体构成。字线和选择栅极可以形成在同一层中，例如多晶硅层。字线可以沿着第一方向(参考x轴方向)延伸。
存储器数组3包含多条位线(BL)。同一栏的非易失性存储单元的P+汲极掺杂区16电连接至同一位线(BL)。位线可以沿着第二方向(参考y轴方向)延伸。应理解的是，位线可以形成在金属内连架构中。
在存储器数组3中提供多条N型阱(NW)线，其是用于将N型阱电压与非易失性存储单元的辅助栅极(AG)电容耦合。图示中仅例示一条N型阱(NW)线(或辅助栅极线)。N型阱(NW)线可沿着第二方向(参考y轴方向)延伸且位于两个位线之间。应理解的是，N型阱(NW)线可以形成在金属内连架构中，且经由第二氧化物定义(OD)区220上的N型阱区拾取接点180将N型阱(NW)线电连接至相应的N+掺杂区18，以向N型阱区110提供N型阱区电压VNW。
存储器数组3包含多条源极线(SL)。存储器数组3中非易失性存储单元的P+源极掺杂区电连接至相应的源极线(SL)。如图7所示，源极线(SL)沿第一方向(参考x轴方向)延伸。应理解的是，图7中的源极线(SL)、位线(BL)、N型阱(辅助栅极)线和擦除线(EL)仅是示意图。源极线(SL)和位线(BL)可以布置在金属内连架构的不同层中。
在存储器数组3中提供多条擦除线(EL)，其用于将擦除线电压(VEL)与非易失性存储单元的辅助栅极(AG)电容耦合。为了简化，图示中仅例示一条擦除线。应理解的是，存储器数组3可包含多个擦除线。擦除线(EL)可沿着第一方向(参考x轴方向)延伸。应理解的是，擦除线(EL)可以形成在金属内连架构中(例如M1或M2)。擦除线(EL)是经由第三氧化物定义(OD)区230上的接触点190电连接至相应的N+掺杂区19，以提供P型阱(PW)区120一擦除线电压VEL。
图10是根据本发明另一实施例所绘示的数组结构。图10例示四个非易失性存储单元C1、C2、C3及C4，各非易失性存储单元C1、C2、C3及C4具有类似图1至图7所示的非易失性存储单元结构。
例如，非易失性存储单元C1可包含三个被分隔开但彼此紧密排列的氧化物定义(OD)区，包含有一第一氧化物定义(OD)区210、一第二氧化物定义(OD)区220和一第三氧化物定义(OD)区230，由嵌入在一半导体衬底100(例如P型掺杂硅衬底P-Sub)主表面的隔离区200分隔开。第二氧化物定义(OD)区域220也可以被称为辅助栅极(AG)耦合区域。
根据本发明的实施例，第一氧化物定义(OD)区210及第二氧化物定义(OD)区220位于N型阱(NW)区110内，第三氧化物定义(OD)区230位于P型阱区(PW)120内。图10例示两个第一氧化物定义(OD)区210、两个第二氧化物定义(OD)区220和两个第三氧化物定义(OD)区域230，其中两个第一氧化物定义(OD)区210都具有沿着第二方向(参考y轴方向)延伸的细长矩形形状；两个第二氧化物定义(OD)区220介于两个平行的第一氧化物定义(OD)区210之间；两个第三氧化物定义(OD)区域230具有沿着第一方向(参考x轴方向)延伸的细长矩形形状。
非易失性存储单元C1包含一选择晶体管10和一与选择晶体管10串联的浮动栅极晶体管20，直接形成在第一氧化物定义(OD)区210上。根据本发明实施例，选择晶体管10是P型金氧半导体(P型金氧半)晶体管，包含一P+源极掺杂区12(与一源极线SL耦合)位于N型阱(NW)区110中；一与P+源极掺杂区12分隔开的共享P+掺杂区14；一选择栅极(SG)通道区，位在P+源极掺杂区12和共享P+掺杂区14之间并接近半导体衬底100主要表面；一选择栅极(SG)2覆盖在选择栅极通道区上，并与字线(WL)耦合；以及一栅极介电层，位于选择栅极(SG)2和选择栅极通道区之间。
一浮动栅极晶体管20直接位于第一氧化物定义(OD)区210上。浮动栅极晶体管20借由共享P+掺杂区14与选择晶体管10串接。浮动栅极晶体管20与选择晶体管10分享共享P+掺杂区14，因而形成两串联P型金氧半晶体管。
浮动栅极晶体管20包含一浮动栅极(FG)4，覆盖在第一氧化物定义(OD)区210上。根据本发明实施例，浮动栅极4由单层多晶硅构成，例如N+掺杂多晶硅或P+掺杂多晶硅，且浮动栅极晶体管20是非易失性存储单元的电荷贮存元件。选择栅极(SG)2和浮动栅极(FG)4均是直线型，沿着一第1方向(参考x轴方向)延伸。
浮动栅极晶体管20另包含共享P+掺杂区14位于浮动栅极4的一边，一P+汲极掺杂区16位于另外一边，且与位线(BL)耦合；一浮动栅极通道区介于共享P+掺杂区14和P+汲极掺杂区16之间；以及一栅极介电层位于浮动栅极4与浮动栅极通道区之间。
非易失性存储单元C1另包含一辅助栅极(AG)6，自浮动栅极4一末端延伸凸出至第二氧化物定义(OD)区220的一边，且与第二氧化物定义(OD)区220及N型阱区110电容耦合。由上方俯视，辅助栅极(AG)6部分重叠第二氧化物定义(OD)区220。
在第二氧化物定义(OD)区220未被辅助栅极(AG)6覆盖的区域形成一N+掺杂区18。可借由N型阱区电压(VNW)控制一耦合至辅助栅极(AG)6的感应电压。上述感应电压是由于辅助栅极(AG)6与偏压下的N型阱区110之间的耦合效应所产生的，将在程序化操作时产生更多的载子注入至浮动栅极，使得写入效率可以提升。辅助栅极(AG)6可由N+掺杂多晶硅或P+掺杂多晶硅构成。
非易失性存储单元C1另包含一擦除栅极(EG)8，自浮动栅极4的一边缘沿着第二方向(参考y轴方向)连续延伸出去，且横越N型阱区110和P型阱区120的接合处。根据本发明实施例，擦除栅极(EG)8一末端重叠P型阱区120内的第三氧层定义(OD)区230，借由这样的结构，擦除栅极(EG)8可与第三氧层定义(OD)区230及P型阱区120电容耦合。一N+掺杂区19位于第三氧层定义(OD)区230未被擦除栅极(EG)8覆盖的区域上。
非易失性存储单元C1是非易失性存储单元C2对于中心线80(虚线)的镜像对称结构，而非易失性存储单元C3则是非易失性存储单元C4对于中心线80(虚线)的镜像对称结构。因此，非易失性存储单元C1的AG及非易失性存储单元C2的AG与同一个第二氧化物定义(OD)区220电容耦合，而非易失性存储单元C3的AG及非易失性存储单元C4的AG与同一个第二氧化物定义(OD)区220电容耦合。
非易失性存储单元C1是非易失性存储单元C3对于水平中心线90(虚线)的镜像对称结构，而非易失性存储单元C2则是非易失性存储单元C4对于水平中心线90(虚线)的镜像对称结构。因此，非易失性存储单元C1与非易失性存储单元C3分享一P+源极掺杂区12(与一源极线SL耦合)，而非易失性存储单元C2与非易失性存储单元C4分享一P+源极掺杂区12(与一源极线SL耦合)。
图11是根据本发明的另一实施例所绘示的数组结构，其中例示四个非易失性存储单元C1、C2、C3及C4，各非易失性存储单元C1、C2、C3及C4具有类似图10所示的非易失性存储单元的结构，差异在于，图11的第二氧化物定义(OD)区220位于N型阱区110外及第三氧化物定义(OD)区230位于N型阱区130内。第二氧化物定义(OD)区220位于N型阱区110和N型阱区之间的P型阱区120内。
例如，非易失性存储单元C1包含一选择晶体管10和一与选择晶体管10串联的浮动栅极晶体管20，直接形成在第一氧化物定义(OD)区210上。根据本发明实施例，选择晶体管10是P型金氧半导体(P型金氧半)晶体管，包含一P+源极掺杂区12(与一源极线SL耦合)位于N型阱(NW)区110中；一与P+源极掺杂区12分隔开的共享P+掺杂区14；一选择栅极(SG)通道区，位在P+源极掺杂区12和共享P+掺杂区14之间并接近半导体衬底主要表面；一选择栅极(SG)2覆盖在选择栅极通道区上，并与字线(WL)耦合；以及一栅极介电层，位于选择栅极(SG)2和选择栅极通道区之间。
一浮动栅极晶体管20直接位于第一氧化物定义(OD)区210上。浮动栅极晶体管20借由共享P+掺杂区14与选择晶体管10链接。浮动栅极晶体管20与选择晶体管10分享共享P+掺杂区14，因而形成两串联P型金氧半晶体管。
浮动栅极晶体管20包含一浮动栅极(FG)4，覆盖在第一氧化物定义(OD)区210上。根据本发明实施例，浮动栅极4由单层多晶硅构成，例如N+掺杂多晶硅或P+掺杂多晶硅，且浮动栅极晶体管20是非易失性存储单元的电荷贮存元件。选择栅极(SG)2和浮动栅极(FG)4均是直线型，沿着一第1方向(参考x轴方向)延伸。
浮动栅极晶体管20另包含共享P+掺杂区14位于浮动栅极4的一边，一P+汲极掺杂区16位于另外一边，且与位线(BL)耦合；一浮动栅极通道区介于共享P+掺杂区14和P+汲极掺杂区16之间；以及一栅极介电层位于浮动栅极4与浮动栅极通道区之间。一辅助栅极(AG)6，自浮动栅极4凸出延伸至第二氧化物定义(OD)区220的一边，且与第二氧化物定义(OD)区220及P型阱区120电容耦合。由上方俯视，辅助栅极(AG)6部分重叠第二氧化物定义(OD)区220。在第二氧化物定义(OD)区220未被辅助栅极(AG)6覆盖的区域形成一N+掺杂区18。
非易失性存储单元C1另包含一擦除栅极(EG)8，自浮动栅极4的一边缘沿着第二方向(参考y轴方向)连续延伸出去，且横越N型阱区130和P型阱区120的接合处。根据本发明实施例，擦除栅极(EG)8一末端重叠N型阱区130内的第三氧层定义(OD)区230，借由这样的结构，擦除栅极(EG)8可与第三氧层定义(OD)区230电容耦合。一N+掺杂区19位于第三氧层定义(OD)区230未被擦除栅极(EG)8覆盖的区域上。
非易失性存储单元C1是非易失性存储单元C2对于中心线80(虚线)的镜像对称结构，而非易失性存储单元C3则是非易失性存储单元C4对于中心线80(虚线)的镜像对称结构。因此，非易失性存储单元C1的AG及非易失性存储单元C2的AG与同一个第二氧化物定义(OD)区220电容耦合，而非易失性存储单元C3的AG及非易失性存储单元C4的AG与同一个第二氧化物定义(OD)区220电容耦合。
非易失性存储单元C1是非易失性存储单元C3对于水平中心线90(虚线)的镜像对称结构，而非易失性存储单元C2则是非易失性存储单元C4对于水平中心线90(虚线)的镜像对称结构。因此，非易失性存储单元C1与非易失性存储单元C3分享一P+源极掺杂区12(与一源极线SL耦合)，而非易失性存储单元C2与非易失性存储单元C4分享一P+源极掺杂区12(与一源极线SL耦合)。
图12是根据本发明的另一实施例所绘示的数组结构，其中例示四个非易失性存储单元C1、C2、C3及C4，且FG、AG和EG是沿着第二方向对准。图12例示中两个第一氧化物定义(OD)区210、两个第二氧化物定义(OD)区220和两个第三氧化物定义(OD)区域230，其中两个第一氧化物定义(OD)区210都具有沿着第一方向(参考x轴方向)延伸的细长矩形形状；两个第三氧化物定义(OD)区域230具有细长矩形形状；两个第二氧化物定义(OD)区220介于第一氧化物定义(OD)区210与第三氧化物定义(OD)区域230之间。
例如，非易失性存储单元C1包含一选择晶体管10和一与选择晶体管10串联的浮动栅极晶体管20，直接形成在第一氧化物定义(OD)区210上。根据本发明实施例，选择晶体管10是P型金氧半导体(P型金氧半)晶体管，包含一P+源极掺杂区12(与一源极线SL耦合)位于N型阱(NW)区110中；一与P+源极掺杂区12分隔开的共享P+掺杂区14；一选择栅极(SG)通道区，位在P+源极掺杂区12和共享P+掺杂区14之间并接近半导体衬底主要表面；一选择栅极(SG)2覆盖在选择栅极通道区上，并与字线(WL)耦合；以及一栅极介电层，位于选择栅极(SG)2和选择栅极通道区之间。
一浮动栅极晶体管20直接位于第一氧化物定义(OD)区210上。浮动栅极晶体管20借由共享P+掺杂区14与选择晶体管10链接。浮动栅极晶体管20与选择晶体管10分享共享P+掺杂区14，因而形成两串联P型金氧半晶体管。
浮动栅极晶体管20包含一浮动栅极(FG)4，覆盖在第一氧化物定义(OD)区210上。根据本发明实施例，浮动栅极4由单层多晶硅构成，例如N+掺杂多晶硅或P+掺杂多晶硅，且浮动栅极晶体管20是非易失性存储单元的电荷贮存元件。选择栅极(SG)2和浮动栅极(FG)4均是直线型，沿着一第1方向(参考x轴方向)延伸。
浮动栅极晶体管20另包含共享P+掺杂区14位于浮动栅极4的一边，一P+汲极掺杂区16位于另外一边，且与位线(BL)耦合；一浮动栅极通道区介于共享P+掺杂区14和P+汲极掺杂区16之间；以及一栅极介电层位于浮动栅极4与浮动栅极通道区之间。一辅助栅极(AG)6，自浮动栅极4凸出延伸重叠第二氧化物定义(OD)区220，且与第二氧化物定义(OD)区220电容耦合。在第二氧化物定义(OD)区220未被辅助栅极(AG)6覆盖的区域形成一N+掺杂区18。
非易失性存储单元C1另包含一擦除栅极(EG)8，自浮动栅极4的一边缘沿着第二方向(参考y轴方向)连续延伸出去，且横越N型阱区110和P型阱区120的接合处。根据本发明实施例，擦除栅极(EG)8一末端重叠N型阱区130内的第三氧层定义(OD)区230，借由这样的结构，擦除栅极(EG)8可与第三氧层定义(OD)区230电容耦合。一N+掺杂区19位于第三氧层定义(OD)区230未被擦除栅极(EG)8覆盖的区域上。
图13是根据本发明的另一实施例所绘示的数组结构，其中例示四个非易失性存储单元C1、C2、C3及C4，各非易失性存储单元C1、C2、C3及C4具有类似图12所示的非易失性存储单元的结构，差异在于，图13的第二氧化物定义(OD)区220位于N型阱区110外及第三氧化物定义(OD)区230位于N型阱区130内。第二氧化物定义(OD)区220位于N型阱区110和N型阱区之间的P型阱区120内。
图14是根据本发明的另一实施例所绘示的数组结构，其中例示四个非易失性存储单元C1、C2、C3及C4，各非易失性存储单元C1、C2、C3及C4具有类似图12所示的非易失性存储单元的结构，差异在于，图14中的四个非易失性存储单元C1、C2、C3及C4共享一个AG耦合区域(第二氧化物定义区)。第二氧化物定义(OD)区220介于两个平行的第一氧化物定义(OD)区210之间，以提供更紧密的数组结构。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (14)

1.一种非易失性存储器数组，其特征在于，包含：
多个非易失性存储单元，其中各非易失性存储单元包含：
一半导体衬底，其中具有一第一N型阱区；
一第一氧化物定义区及一第二氧化物定义区，设置在所述半导体衬底内；
一P型金氧半选择晶体管，设置在所述第一氧化物定义区上，其中所述P型金氧半选择晶体管包含一选择栅极、一第一P+源极掺杂区，位于所述第一N型阱区，以及一第二P+源极掺杂区与所述第一P+源极掺杂区分隔开；
一P型金氧半浮动栅极晶体管，与所述P型金氧半选择晶体管串联，并且设置在所述第一氧化物定义区上，其中所述P型金氧半浮动栅极晶体管包含一浮动栅极，覆盖所述第一氧化物定义区、所述第二P+源极掺杂区，以及一第三P+源极掺杂区与所述第二P+源极掺杂区分隔开，其中所述P型金氧半浮动栅极晶体管是所述非易失性存储单元的电荷贮存元件；以及
一辅助栅极，自所述浮动栅极凸出延伸至所述第二氧化物定义区的一边缘，使得所述辅助栅极与所述第二氧化物定义区电容耦合，其中所述辅助栅极与所述浮动栅极由单层多晶硅一体构成；
多条字线，沿着一第一方向延伸，其中各所述字线电连接至各所述多个非易失性存储单元中的所述P型金氧半选择晶体管的所述选择栅极；
多条位线，沿着一第二方向延伸，其中各所述位线电连接至各所述多个非易失性存储单元中的所述P型金氧半浮动栅极晶体管的所述第三P+源极掺杂区；以及
多条源极线，其中所述源极线电连接至各所述多个非易失性存储单元中的所述P型金氧半选择晶体管的所述第一P+源极掺杂区。
2.根据权利要求1所述的非易失性存储器数组，其特征在于，所述第一氧化物定义区及所述第二氧化物定义区设置在所述第一N型阱区内。
3.根据权利要求1所述的非易失性存储器数组，其特征在于，借由所述N型阱区的一偏压来控制一耦合至所述辅助栅极的一感应电压。
4.根据权利要求1所述的非易失性存储器数组，其特征在于，所述第一方向垂直于所述第二方向。
5.根据权利要求1所述的非易失性存储器数组，其特征在于，在所述半导体衬底内另包含一P型阱区及一第三氧化物定义区。
6.根据权利要求5所述的非易失性存储器数组，其特征在于，另包含一擦除栅极，从所述浮动栅极连续延伸并且横越所述第一N型阱区和所述P型阱区的接合处。
7.根据权利要求6所述的非易失性存储器数组，其特征在于，所述擦除栅极的一末端重叠所述第三氧化物定义区，使得所述擦除栅极与所述第三氧化物定义区电容耦合。
8.根据权利要求5所述的非易失性存储器数组，其特征在于，所述第一氧化物定义区设置在所述第一N型阱区内，而所述第二氧化物定义区设置在所述P型阱区内。
9.根据权利要求8所述的非易失性存储器数组，其特征在于，另包含一第二N型阱区，其中所述第三氧化物定义区设置在所述第二N型阱区内。
10.根据权利要求5所述的非易失性存储器数组，其特征在于，所述第一氧化物定义区及所述第二氧化物定义区设置在所述第一N型阱区内，以及所述第三氧化物定义区设置在所述P型阱区内。
11.根据权利要求5所述的非易失性存储器数组，其特征在于，另包含多条擦除线，用以将一擦除线电压电容耦合至各所述多个非易失性存储单元中的所述辅助栅极。
12.根据权利要求11所述的非易失性存储器数组，其特征在于，所述擦除线沿着所述第一方向延伸。
13.根据权利要求11所述的非易失性存储器数组，其特征在于，各所述擦除线电连接至所述第三氧化物定义区中的一掺杂区。
14.根据权利要求11所述的非易失性存储器数组，其特征在于，所述擦除线、所述位线及所述源极线形成于一金属内连架构中。
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