CN109979943B - 半导体元件及其制造方法 - Google Patents
半导体元件及其制造方法 Download PDFInfo
- Publication number
- CN109979943B CN109979943B CN201711460739.0A CN201711460739A CN109979943B CN 109979943 B CN109979943 B CN 109979943B CN 201711460739 A CN201711460739 A CN 201711460739A CN 109979943 B CN109979943 B CN 109979943B
- Authority
- CN
- China
- Prior art keywords
- substrate
- region
- pad oxide
- layer
- oxide layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 96
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 238000000034 method Methods 0.000 title claims description 78
- 230000015654 memory Effects 0.000 claims abstract description 76
- 239000000758 substrate Substances 0.000 claims abstract description 72
- 238000002955 isolation Methods 0.000 claims abstract description 64
- 238000003860 storage Methods 0.000 claims abstract description 36
- 239000004020 conductor Substances 0.000 claims abstract description 18
- 230000008569 process Effects 0.000 claims description 51
- 238000005530 etching Methods 0.000 claims description 15
- 239000002019 doping agent Substances 0.000 claims description 11
- 238000005468 ion implantation Methods 0.000 claims description 8
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 6
- 229910052785 arsenic Inorganic materials 0.000 claims description 6
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 6
- 229910052698 phosphorus Inorganic materials 0.000 claims description 6
- 239000011574 phosphorus Substances 0.000 claims description 6
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 3
- 229910052799 carbon Inorganic materials 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 126
- 150000002500 ions Chemical class 0.000 description 11
- 150000004767 nitrides Chemical class 0.000 description 11
- 229910021332 silicide Inorganic materials 0.000 description 10
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 229910052814 silicon oxide Inorganic materials 0.000 description 7
- 125000006850 spacer group Chemical group 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 230000008901 benefit Effects 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 229910021344 molybdenum silicide Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 description 1
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 description 1
- LDDQLRUQCUTJBB-UHFFFAOYSA-N ammonium fluoride Chemical compound [NH4+].[F-] LDDQLRUQCUTJBB-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- PEUPIGGLJVUNEU-UHFFFAOYSA-N nickel silicon Chemical compound [Si].[Ni] PEUPIGGLJVUNEU-UHFFFAOYSA-N 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- UAJUXJSXCLUTNU-UHFFFAOYSA-N pranlukast Chemical compound C=1C=C(OCCCCC=2C=CC=CC=2)C=CC=1C(=O)NC(C=1)=CC=C(C(C=2)=O)C=1OC=2C=1N=NNN=1 UAJUXJSXCLUTNU-UHFFFAOYSA-N 0.000 description 1
- 229960004583 pranlukast Drugs 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
- H01L21/2652—Through-implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
本发明公开一种半导体元件及其制造方法。所述半导体元件包括基底、多个隔离结构、电荷存储层以及导体层。所述基底具有存储器区与逻辑区。所述存储器区的所述基底具有多个半导体鳍。所述隔离结构配置在所述基底中,以隔离所述半导体鳍。所述半导体鳍突出于所述隔离结构。所述电荷存储层覆盖所述半导体鳍。所述导体层横越所述半导体鳍与所述隔离结构,使得所述电荷存储层配置在所述导体层与所述半导体鳍之间。
Description
技术领域
本发明涉及一种集成电路及其制造方法,且特别是涉及一种半导体元件及其制造方法。
背景技术
存储器是一种用于存储电脑或电子产品中的资料或数据的半导体元件,其概分为挥发性存储器(volatile memory)与非挥发性存储器(non-volatile memory)。非挥发性存储器因具有存入的数据在断电后也不会消失的优点,而被广泛地使用。
一般而言,具有硅-氧化物-氮化物-氧化物-半导体(silicon-oxide-nitride-oxide-semiconductor,SONOS)结构的非挥发性存储器具有工艺简单且容易结合至集成电路的周边电路区或逻辑电路区中的优点。然而,随着半导体元件的尺寸微缩,以立体式的存储器结构来取代平面式的存储器结构已然成为一种趋势。因此,如何提供一种立体式的SONOS存储器结构,使其具有高效能、工艺简单以及制造便宜等优点已然成为重要的一门课题。
发明内容
本发明提供一种半导体元件,其结合类似鳍状晶体管(FinFET-like)与SONOS存储器结构,以形成立体式的SONOS存储器结构,进而提升半导体元件的效能。
本发明提供一种半导体元件的制造方法,其工艺简单且成本低廉,进而提升半导体元件的商业竞争力。
本发明提供一种半导体元件,包括基底、多个隔离结构、电荷存储层以及导体层。所述基底具有存储器区与逻辑区。所述存储器区的所述基底具有多个半导体鳍。所述隔离结构配置在所述基底中,以隔离所述半导体鳍。所述半导体鳍突出于所述隔离结构。所述电荷存储层覆盖所述半导体鳍。所述导体层横越所述半导体鳍与所述隔离结构,使得所述电荷存储层配置在所述导体层与所述半导体鳍之间。
在本发明的一实施例中,所述隔离结构的顶面低于所述半导体鳍的顶面,且相距高度差。
在本发明的一实施例中,所述高度差介于20纳米至30纳米之间。
在本发明的一实施例中,所述存储器区的所述基底的顶面与所述逻辑区的所述基底的顶面为共平面。
在本发明的一实施例中,所述电荷存储层包括氧化物-氮化物-氧化物的堆叠层。
在本发明的一实施例中,所述半导体元件还包括选择栅极结构配置在逻辑区的所述基底上,并横越所述基底与所述隔离结构。
在本发明的一实施例中,所述导体层为控制栅极。
在本发明的一实施例中,所述半导体元件还包括掺杂区位于所述选择栅极结构与所述控制栅极之间的所述基底中,其中所述选择栅极结构与所述控制栅极共用所述掺杂区。
在本发明的一实施例中,所述半导体鳍的宽度介于5纳米至20纳米之间。
本发明提供一种半导体元件的制造方法,其步骤如下。提供基底,其包括存储器区与逻辑区。在所述存储器区与所述逻辑区的所述基底中形成多个隔离结构。在所述存储器区与所述逻辑区的所述基底上形成垫氧化物层。移除所述存储器区中的所述垫氧化物层,以凹陷所述隔离结构,使得所述存储器区中的所述基底的多个部分突出于所述隔离结构,以形成多个半导体鳍。形成电荷存储层以覆盖所述半导体鳍。形成导体层以横越所述半导体鳍与所述隔离结构,使得所述电荷存储层配置在所述导体层与所述半导体鳍之间。
在本发明的一实施例中,所述移除所述存储器区中的所述垫氧化物层的步骤如下。形成掩模图案以覆盖所述逻辑区中的所述垫氧化物层。进行缓冲氧化物蚀刻工艺(BOE)5秒至300秒,以完全移除所述存储器区中的所述垫氧化物层并移除所述隔离结构的一部分。
在本发明的一实施例中,所述缓冲氧化物蚀刻工艺对所述隔离结构与所述基底的蚀刻选择比介于100至5之间。
在本发明的一实施例中,所述移除所述存储器区中的所述垫氧化物层的步骤如下。形成掩模图案以覆盖所述逻辑区中的所述垫氧化物层。对所述存储器区中的所述垫氧化物层进行离子注入处理。进行缓冲氧化物蚀刻工艺5秒至300秒,以完全移除所述存储器区中的所述垫氧化物层并移除所述隔离结构的一部分。
在本发明的一实施例中,所述离子注入处理包括将掺质注入到所述存储器区中的所述垫氧化物层中,所述掺质包括碳、磷、砷或其组合。
在本发明的一实施例中,移除所述存储器区中的所述垫氧化物层以凹陷所述隔离结构之后,所述隔离结构的顶面低于所述半导体鳍的顶面,且相距高度差。
在本发明的一实施例中,所述高度差介于20纳米至30纳米之间。
在本发明的一实施例中,所述半导体元件的制造方法还包括在逻辑区的所述基底上形成选择栅极结构,其横越所述基底与所述隔离结构。
在本发明的一实施例中,所述导体层为控制栅极。
在本发明的一实施例中,在形成所述选择栅极结构之后,所述半导体元件的制造方法还包括在所述选择栅极结构与所述控制栅极之间的所述基底中形成掺杂区,其中所述选择栅极结构与所述控制栅极共用所述掺杂区。
在本发明的一实施例中,所述半导体鳍的宽度介于5纳米至20纳米之间。
基于上述,本发明在移除存储器区中的垫氧化物层的步骤中,更进一步地移除隔离结构的一部分,以形成多个半导体鳍。接着,依序形成电荷存储层与控制栅极以覆盖所述半导体鳍,由此形成立体式的SONOS存储器结构,进而提升半导体元件的效能。另外,本发明的半导体元件的工艺步骤简单且成本低廉,其可提升半导体元件的商业竞争力。
为让本发明的上述特征和优点能更明显易懂,下文特举实施例,并配合所附附图作详细说明如下。
附图说明
图1为本发明一实施例所绘示的半导体元件的平面示意图;
图2A、图3A、图4A、图5A、图6A、图7A及图8A为沿着图1的A-A’线所绘示的半导体元件的制造流程的剖面示意图;
图2B、图3B、图4B、图5B、图6B、图7B及图8B为沿着图1的B-B’线所绘示的半导体元件的制造流程的剖面示意图;
图9为本发明第一实施例所绘示的半导体元件的制造流程图;
图10为本发明第二实施例所绘示的半导体元件的制造流程图。
具体实施方式
参照本实施例的附图以更全面地阐述本发明。然而,本发明也可以各种不同的形式体现,而不应限于本文中所述的实施例。附图中的层与区域的厚度会为了清楚起见而放大。相同或相似的标号表示相同或相似的元件,以下段落将不再一一赘述。
图1为依照本发明一实施例所绘示的半导体元件的平面示意图。在本实施例中,所述半导体元件可以是具有SONOS存储器结构的半导体元件,但本发明不以此为限。
请参照图1,本发明实施例提供一种半导体元件包括基底100、多个隔离结构101、第一栅极堆叠10以及第二栅极堆叠20。具体来说,基底100包括存储器区MR与逻辑区LR。虽然图1所绘示的存储器区MR位于逻辑区LR旁,但本发明不以此为限。在其他实施例中,逻辑区LR也可围绕存储器区MR。也就是说,存储器区MR与逻辑区LR的配置可依设计需求来进行调整。
隔离结构101配置在基底100中。详细地说,隔离结构101沿着第一方向D1延伸并横越存储器区MR与逻辑区LR,以将基底100分为多个条状结构。如图1所示,所述条状结构与隔离结构101沿着第二方向D2交替排列。在一实施例中,第一方向D1与第二方向D2互相垂直。
具体来说,如图1所示,存储器区MR中的所述条状结构可以是半导体鳍105。换言之,存储器区MR的基底100具有多个半导体鳍105。位于基底100中的隔离结构101隔离半导体鳍105。第一栅极堆叠10配置在存储器区MR的基底100上,其沿着第二方向D2延伸,以横越并覆盖隔离结构101与半导体鳍105。第二栅极堆叠20配置在逻辑区LR的基底100上,其沿着第二方向D2延伸,以横越并覆盖隔离结构101与基底100。在一实施例中,第一栅极堆叠10可以是一种存储单元元件,其用以当作控制栅极结构;而第二栅极堆叠20可以是一种金属氧化物半导体元件,其用以当作选择栅极结构。
图2A、图3A、图4A、图5A、图6A、图7A及图8A为沿着图1的A-A’线所绘示的半导体元件的制造流程的剖面示意图。图2B、图3B、图4B、图5B、图6B、图7B及图8B为沿着图1的B-B’线所绘示的半导体元件的制造流程的剖面示意图。图9为依照本发明第一实施例所绘示的半导体元件的制造流程图。
请参照图2A、图2B以及图9,本发明第一实施例提供一种半导体元件的制造方法S100,其步骤如下。首先,进行步骤S102,提供基底100,其包括相邻的存储器区MR与逻辑区LR。在一实施例中,基底100包括半导体基底,例如是硅基底。
接着,如图2B所示,在基底100中形成多个隔离结构101。隔离结构101嵌入基底100中,使得基底100形成为一梳状结构。所述梳状结构包括下部100a与多个梳部100b。梳部100b位于下部100a上。梳部100b夹置在隔离结构101之间。在一实施例中,隔离结构101可例如是浅沟槽隔离(Shallow Trench Isolation,STI)结构,其材料包括绝缘材料,所述绝缘材料可以是氧化硅、氮化硅或其组合。
之后,进行步骤S104,在基底100上依序形成垫氧化物层102与氮化物层104。垫氧化物层102全面性地(blanketly)覆盖存储器区MR与逻辑区LR的基底100与隔离结构101上。氮化物层104覆盖垫氧化物层102上,使得垫氧化物层102位于氮化物层104与基底100之间以及氮化物层104与隔离结构101之间。在一实施例中,垫氧化物层102可以是氧化硅,其形成方法包括热氧化法、化学气相沉积法(CVD)等。在一实施例中,氮化物层104可以是氮化硅,其形成方法包括CVD。
然后,进行步骤S106,如图2A、图2B、图3A以及图3B所示,在逻辑区LR中的氮化物层104上形成掩模图案106。之后,以掩模图案106为掩模,进行图案化工艺,以移除存储器区MR中的氮化物层104。在此情况下,如图3A所示,图案化的氮化物层104a与其上的掩模图案106覆盖逻辑区LR中的垫氧化物层102的顶面,且暴露出存储器区MR中的垫氧化物层102的顶面。在一实施例中,掩模图案106可以是光致抗蚀剂,其通过旋转涂布法以及光刻法来形成。
之后,对存储器区MR的基底100进行离子掺杂工艺108。在一实施例中,离子掺杂工艺108包括至少二道离子掺杂工艺,其依序包括用以形成第一阱区103的第一离子掺杂工艺以及用以调整临界电压(threshold voltage,Vt)的第二离子掺杂工艺。在一实施例中,所述第一离子掺杂工艺所注入的掺质可例如是硼(B),所述第二离子掺杂工艺所注入的掺质可例如是铟(In),上述两者的掺杂浓度可依据不同元件的需求来调整。
在移除掩模图案106之后,进行步骤S108,如图3A、图3B、图4A以及图4B所示,移除存储器区MR中的垫氧化物层102,以凹陷隔离结构101,使得存储器区MR中的基底100的多个部分突出于隔离结构101,以形成多个半导体鳍105。具体来说,以图案化的氮化物层104a为掩模,进行蚀刻工艺,以完全移除存储器区MR中的垫氧化物层102,并移除隔离结构101的一部分。在替代实施例中,掩模图案106也可在所述蚀刻工艺中一并移除。
在一实施例中,所述蚀刻工艺包括湿式蚀刻工艺,例如是缓冲氧化物蚀刻(BOE)工艺。所述BOE工艺包括使用HF、NH4F以及水混合而成的蚀刻液来进行蚀刻,上述三者的比例可依实际需求来调整。在本实施例中,所述BOE工艺的工艺时间介于5秒至300秒。所述BOE工艺对隔离结构101与基底100的蚀刻选择比介于100至5之间。也就是说,在完全移除存储器区MR中的垫氧化物层102之后,所述BOE工艺会蚀刻隔离结构101,而不会蚀刻基底100或是微量蚀刻基底100,以形成类似鳍状(Fin-like)结构。在此情况下,如图4B所示,隔离结构101的顶面101T低于半导体鳍105(或基底100)的顶面105T,且相距高度差H。在一实施例中,所述高度差H介于20纳米至30纳米之间。在一实施例中,半导体鳍105的宽度W介于5纳米至20纳米之间。
在移除图案化的氮化物层104a之后,进行步骤S110,如图5A与图5B所示,在基底100上全面性地形成电荷存储层110。值得注意的是,如图5B所示,电荷存储层110覆盖半导体鳍105的顶面105T与上侧壁105S。也就是说,电荷存储层110覆盖外露于(或突出于)隔离结构101的半导体鳍105的表面。在一实施例中,电荷存储层110包括氧化物-氮化物-氧化物(ONO)的堆叠层。具体来说,电荷存储层110包括氧化硅层112、氮化硅层114以及氧化硅层116,其中氮化硅层114配置在两个氧化硅层112、116之间。但本发明不以此为限,在其他实施例中,电荷存储层110也可以是多晶硅(亦即浮置栅极)或ONON的堆叠层等。
请参照图5A、图5B、图6A以及图6B,在存储器区MR中的电荷存储层110上形成掩模图案118。掩模图案118覆盖存储器区MR中的电荷存储层110,且暴露出逻辑区LR中的电荷存储层110。以掩模图案118为掩模,完全移除逻辑区LR中的电荷存储层110,以暴露出逻辑区LR中的垫氧化物层102a的顶面。在一实施例中,掩模图案118可以是光致抗蚀剂,其通过旋转涂布法以及光刻法来形成。
在移除掩模图案118之后,进行步骤S112,如图6A、图6B、图7A以及图7B所示,形成导体层120a、120b以横越半导体鳍105与隔离结构101。具体来说,可先在基底100上形成导体材料(未绘示)。在一实施例中,所述导体材料可以是掺杂多晶硅、未掺杂多晶硅或其组合,其形成方法包括CVD。接着,图案化所述导体材料,以于存储器区MR中的基底100上形成导体层120a,且于逻辑区LR中的基底100上形成导体层120b。如图7A与图7B所示,导体层120a配置在电荷存储层110a上,使得电荷存储层110a配置在导体层120a与半导体鳍105之间。如图1所示,导体层120a为条状结构,其沿着第二方向D2延伸,且横越隔离结构101与半导体鳍105。在一实施例中,导体层120a用以当作控制栅极。
另一方面,在形成导体层120b之前,还包括移除逻辑区LR中的垫氧化物层102、在基底100中形成第二阱区107以及于基底100上形成栅介电层122。在一实施例中,第二阱区107可以是P型导电型,其所注入的掺质可例如是硼(B)。在一实施例中,栅介电层122可以是氧化硅,其形成方法包括热氧化法或CVD。接着,在栅介电层122上形成导体层120b。如图1所示,导体层120b也为条状结构,其沿着第二方向D2延伸,且横越隔离结构101与基底100(或第二阱区107)。在一实施例中,导体层120b用以当作选择栅极。
请参照图7A、图7B、图8A以及图8B,在形成导体层120a、120b之后,图案化栅介电层122与电荷存储层110a,以分别形成第一栅极堆叠10与第二栅极堆叠20。具体来说,以导体层120a为掩模,移除部分电荷存储层110a,以暴露出基底100(或第一阱区103)的顶面。另一方面,以导体层120b为掩模,移除部分栅介电层122,以暴露出基底100(或第二阱区107)的顶面。由图8A可知,存储器区MR的基底100的顶面100T与逻辑区LR的基底100的顶面100T’为共平面。
第一栅极堆叠10包括电荷存储层110b以及导体层120a。电荷存储层110a共形地(conformally)覆盖半导体鳍105的表面。如图8B所示,电荷存储层110b覆盖半导体鳍105的顶面105T与上侧壁105S,使得电荷存储层110b的顶面110T为凹凸不平的表面。具体来说,位于隔离结构101上的电荷存储层110b的顶面100T1低于位于半导体鳍105上的电荷存储层110b的顶面100T2。
值得注意的是,由于电荷存储层110b的顶面110T为凹凸不平的表面,因此本实施例的电荷存储层110b与导体层120a之间的接触面积增加,进而提升半导体元件的栅极控制能力。如此一来,本实施例的半导体元件在抹除状态(erase state)下的导通电流(Ion)可有效地提升,而不会造成漏电流(Ioff)的增加。换言之,本实施例的半导体元件的整体效能可有效地提升。
另一方面,第二栅极堆叠20包括栅介电层122a以及位于栅介电层122a上的导体层120b。如图1所示,第二栅极堆叠20可以是条状结构,其沿着第二方向D2延伸,以横越并覆盖隔离结构101与基底100(或第二阱区107)。
在形成第一栅极堆叠10与第二栅极堆叠20之后,本实施例的半导体元件的制造方法还包括形成间隙壁124、126。具体来说,间隙壁124覆盖在第一栅极堆叠10的侧壁上;而间隙壁126覆盖在第二栅极堆叠20的侧壁上。在一实施例中,间隙壁124、126可包括单层结构、双层结构或多层结构。间隙壁124、126的材料包括绝缘材料,其可例如是氧化硅、氮化硅、氮氧化硅或其组合。间隙壁124、126的形成方法为本领域技术人员所熟知,于此便不再详述。
在形成间隙壁124、126之后,本实施例的半导体元件的制造方法还包括在基底100中形成掺杂区128、130、132。具体来说,掺杂区128配置在第一栅极堆叠10与第二栅极堆叠20之间的基底100中。在一实施例中,掺杂区128可以是N型导电型,其所注入的掺质可例如是可例如是磷(P)或是砷(As)。如图8A所示,掺杂区128可以是第一栅极堆叠10(或控制栅极结构)的源极区;同时也是第二栅极堆叠20(或选择栅极结构)的漏极区。也就是说,第一栅极堆叠10与第二栅极堆叠20共用掺杂区128,以将第一栅极堆叠10与第二栅极堆叠20电性串联在一起。在替代实施例中,掺杂区128也包括轻掺杂漏极区(lightly doped drain,LDD)。
在一实施例中,掺杂区130配置在第一栅极堆叠10的另一侧(即远离掺杂区128的一侧)的基底100中。掺杂区130可以是N型导电型,其所注入的掺质可例如是可例如是磷(P)或是砷(As)。如图8A所示,掺杂区130可以是第一栅极堆叠10(或控制栅极结构)的漏极区。在替代实施例中,掺杂区130也包括轻掺杂漏极区。
在一实施例中,掺杂区132配置在第二栅极堆叠20的另一侧(即远离掺杂区128的一侧)的基底100中。掺杂区132可以是N型导电型,其所注入的掺质可例如是可例如是磷(P)或是砷(As)。如图8A所示,掺杂区132可以是第二栅极堆叠20(或选择栅极结构)的源极区。在替代实施例中,掺杂区132也包括轻掺杂漏极区。
在形成掺杂区128、130、132之后,本实施例的半导体元件的制造方法更包括形成硅化金属层138、140、142、144、146。具体来说,硅化金属层138形成在掺杂区128上。硅化金属层140形成在掺杂区130上。硅化金属层142形成在掺杂区132上。硅化金属层144形成在导体层120a(即控制栅极)上。硅化金属层146形成在导体层120b(即选择栅极)上。在一实施例中,硅化金属层138、140、142、144、146的材料例如是硅化镍(NiSi)、硅化钴(CoSi)、硅化钛(TiSi)、硅化钨(WSi)、硅化钼(MoSi)、硅化铂(PtSi)、硅化钯(PdSi)或其组合。硅化金属层138、140、142、144、146的形成方法为本领域技术人员所熟知,于此便不再详述。
图10为依照本发明第二实施例所绘示的半导体元件的制造流程图。
请参照图9与图10,基本上,本发明第二实施例的半导体元件的制造方法S200与本发明第一实施例的半导体元件的制造方法S100相似。也就是说,步骤S202、S204、S206与步骤S102、S104、S106相同,于此便不再赘述。上述两者不同之处在于:在进行步骤S206之后,第二实施例的半导体元件的制造方法S200还包括进行步骤S207,亦即对存储器区MR中的垫氧化物层102进行离子注入处理,如图3A与图3B所示。具体来说,在对存储器区MR的基底100进行离子掺杂工艺108(其包括用以形成第一阱区103的第一离子掺杂工艺与用以调整临界电压的第二离子掺杂工艺)之后,对存储器区MR中的垫氧化物层102进行离子注入处理。值得注意的是,所述离子注入处理可用以改变存储器区MR中的垫氧化物层102的结构组成,使得经注入后的垫氧化物层102更容易被后续进行的缓冲氧化物蚀刻(BOE)工艺移除,由此缩短BOE工艺的工艺时间。也就是说,步骤S208的BOE工艺时间可小于步骤S108的BOE工艺时间。在一实施例中,所述离子注入处理所注入的掺质包括碳、磷、砷或其组合。
接着,进行步骤S208,如图4A与图4B所示,以图案化的氮化物层104a为掩模,进行蚀刻工艺,以完全移除存储器区MR中的垫氧化物层102,并移除隔离结构101的一部分。在一实施例中,所述蚀刻工艺包括湿式蚀刻工艺,例如是缓冲氧化物蚀刻(BOE)工艺。在本实施例中,所述BOE工艺的工艺时间介于5秒至300秒。所述BOE工艺对隔离结构101与基底100的蚀刻选择比介于100至5之间。也就是说,在完全移除存储器区MR中的垫氧化物层102之后,所述BOE工艺会蚀刻隔离结构101,而不会蚀刻基底100或是微量蚀刻基底100,以形成类似鳍状(Fin-like)结构。
之后,进行步骤S210、S212,亦即形成电荷存储层110与形成导体层120a、120b。由于步骤S210、S212与步骤S110、S112相同,于此便不再赘述。
综上所述,本发明在移除存储器区中的垫氧化物层的步骤中,更进一步地移除隔离结构的一部分,以形成多个半导体鳍。接着,依序形成电荷存储层与控制栅极以覆盖所述半导体鳍,由此形成立体式的SONOS存储器结构,进而提升半导体元件的效能。另外,本发明的半导体元件的工艺步骤简单且成本低廉,其可提升半导体元件的商业竞争力。
虽然结合以上实施例公开了本发明,然而其并非用以限定本发明,任何所属技术领域中具有通常知识者,在不脱离本发明的精神和范围内,可作些许的更动与润饰,故本发明的保护范围应当以附上的权利要求所界定的为准。
Claims (8)
1.一种半导体元件的制造方法,其特征在于,包括:
提供基底,其包括存储器区与逻辑区;
在所述存储器区与所述逻辑区的所述基底中形成多个隔离结构;
在所述逻辑区的所述基底上形成选择栅极结构,其横越所述基底与所述隔离结构;
在所述存储器区与所述逻辑区的所述基底上形成垫氧化物层;
移除所述存储器区中的所述垫氧化物层,以凹陷所述隔离结构,使得所述存储器区中的所述基底的多个部分突出于所述隔离结构,以形成多个半导体鳍;
形成电荷存储层以覆盖所述半导体鳍;
形成导体层以横越所述半导体鳍与所述隔离结构,使得所述电荷存储层配置在所述导体层与所述半导体鳍之间,其中所述导体层为控制栅极;以及
在所述选择栅极结构与所述控制栅极之间的所述基底中形成掺杂区,其中所述选择栅极结构与所述控制栅极共用所述掺杂区,
其中位于所述存储器区的所述隔离结构的顶面低于位于所述逻辑区的所述隔离结构的顶面,且相距第一高度差,其中所述第一高度差介于20纳米至30纳米之间,
其中位于所述逻辑区的所述基底的顶面与位于所述逻辑区的所述隔离结构的所述顶面为共平面。
2.如权利要求1所述的半导体元件的制造方法,其中所述移除所述存储器区中的所述垫氧化物层包括:
形成掩模图案以覆盖所述逻辑区中的所述垫氧化物层;
进行缓冲氧化物蚀刻工艺5秒至300秒,以完全移除所述存储器区中的所述垫氧化物层并移除所述隔离结构的一部分。
3.如权利要求2所述的半导体元件的制造方法,其中所述缓冲氧化物蚀刻工艺对所述隔离结构与所述基底的蚀刻选择比介于100至5之间。
4.如权利要求1所述的半导体元件的制造方法,其中所述移除所述存储器区中的所述垫氧化物层包括:
形成掩模图案以覆盖所述逻辑区中的所述垫氧化物层;
对所述存储器区中的所述垫氧化物层进行离子注入处理;以及
进行缓冲氧化物蚀刻工艺5秒至300秒,以完全移除所述存储器区中的所述垫氧化物层并移除所述隔离结构的一部分。
5.如权利要求4所述的半导体元件的制造方法,其中所述离子注入处理包括将掺质注入到所述存储器区的所述垫氧化物层中,所述掺质包括碳、磷、砷或其组合。
6.如权利要求1所述的半导体元件的制造方法,其中移除所述存储器区中的所述垫氧化物层以凹陷所述隔离结构之后,所述位于所述存储器区的隔离结构的所述顶面低于所述半导体鳍的顶面,且相距第二高度差。
7.如权利要求6所述的半导体元件的制造方法,其中所述第二高度差介于20纳米至30纳米之间。
8.如权利要求1所述的半导体元件的制造方法,其中所述半导体鳍的宽度介于5纳米至20纳米之间。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201711460739.0A CN109979943B (zh) | 2017-12-28 | 2017-12-28 | 半导体元件及其制造方法 |
US15/878,278 US10312250B1 (en) | 2017-12-28 | 2018-01-23 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201711460739.0A CN109979943B (zh) | 2017-12-28 | 2017-12-28 | 半导体元件及其制造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN109979943A CN109979943A (zh) | 2019-07-05 |
CN109979943B true CN109979943B (zh) | 2022-06-21 |
Family
ID=66673356
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201711460739.0A Active CN109979943B (zh) | 2017-12-28 | 2017-12-28 | 半导体元件及其制造方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US10312250B1 (zh) |
CN (1) | CN109979943B (zh) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113314540A (zh) * | 2020-01-03 | 2021-08-27 | 长江存储科技有限责任公司 | 三维存储器的制备方法及三维存储器 |
US11751398B2 (en) | 2020-09-15 | 2023-09-05 | Ememory Technology Inc. | Memory structure and operation method thereof |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007201021A (ja) * | 2006-01-24 | 2007-08-09 | Toshiba Corp | 半導体装置 |
JP2014049717A (ja) * | 2012-09-04 | 2014-03-17 | Toshiba Corp | 半導体装置の製造方法および半導体装置 |
CN104124210A (zh) * | 2013-04-28 | 2014-10-29 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构的形成方法 |
CN104934474A (zh) * | 2014-03-19 | 2015-09-23 | 台湾积体电路制造股份有限公司 | 组合FinFET及其形成方法 |
CN106653762A (zh) * | 2015-10-30 | 2017-05-10 | 联华电子股份有限公司 | 非挥发性存储器及其制造方法 |
US9659948B2 (en) * | 2015-09-17 | 2017-05-23 | United Microelectronics Corp. | Semiconductor device and method of fabricating semiconductor device |
CN107123649A (zh) * | 2016-02-24 | 2017-09-01 | 瑞萨电子株式会社 | 用于制造半导体器件的方法 |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100642632B1 (ko) * | 2004-04-27 | 2006-11-10 | 삼성전자주식회사 | 반도체소자의 제조방법들 및 그에 의해 제조된 반도체소자들 |
KR100612419B1 (ko) * | 2004-10-19 | 2006-08-16 | 삼성전자주식회사 | 핀 트랜지스터 및 평판 트랜지스터를 갖는 반도체 소자 및그 형성 방법 |
CN100438038C (zh) * | 2004-11-02 | 2008-11-26 | 力晶半导体股份有限公司 | 非易失性存储器及其制造方法与操作方法 |
KR100645065B1 (ko) * | 2005-06-23 | 2006-11-10 | 삼성전자주식회사 | 핀 전계 효과 트랜지스터와 이를 구비하는 비휘발성 메모리장치 및 그 형성 방법 |
KR100764745B1 (ko) * | 2006-08-31 | 2007-10-08 | 삼성전자주식회사 | 반원통형 활성영역을 갖는 반도체 장치 및 그 제조 방법 |
US7592675B2 (en) * | 2006-10-02 | 2009-09-22 | Taiwan Semiconductor Manufacutring Company, Ltd. | Partial FinFET memory cell |
US8598646B2 (en) * | 2011-01-13 | 2013-12-03 | Spansion Llc | Non-volatile FINFET memory array and manufacturing method thereof |
CN102956562B (zh) * | 2011-08-22 | 2015-04-29 | 中芯国际集成电路制造(上海)有限公司 | 存储器件的形成方法 |
US9293466B2 (en) * | 2013-06-19 | 2016-03-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Embedded SRAM and methods of forming the same |
US9508396B2 (en) * | 2014-04-02 | 2016-11-29 | Ememory Technology Inc. | Array structure of single-ploy nonvolatile memory |
US9478536B2 (en) * | 2014-12-09 | 2016-10-25 | Samsung Electronics Co., Ltd. | Semiconductor device including fin capacitors |
KR102449901B1 (ko) * | 2015-06-23 | 2022-09-30 | 삼성전자주식회사 | 집적회로 소자 및 그 제조 방법 |
CN105185746B (zh) * | 2015-08-20 | 2018-06-22 | 上海华力微电子有限公司 | Cmos器件工艺中锗硅外延层的制备方法 |
JP6557095B2 (ja) * | 2015-08-26 | 2019-08-07 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP6578172B2 (ja) * | 2015-09-18 | 2019-09-18 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US9842850B2 (en) * | 2015-12-30 | 2017-12-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | High-K-last manufacturing process for embedded memory with silicon-oxide-nitride-oxide-silicon (SONOS) memory cells |
US9754955B2 (en) * | 2015-12-30 | 2017-09-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | High-K-last manufacturing process for embedded memory with metal-oxide-nitride-oxide-silicon (MONOS) memory cells |
JP6591291B2 (ja) * | 2016-01-07 | 2019-10-16 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JP6591311B2 (ja) * | 2016-02-24 | 2019-10-16 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
TWI627665B (zh) * | 2016-04-06 | 2018-06-21 | 瑞昱半導體股份有限公司 | 鰭式場效電晶體及其製造方法 |
JP6688698B2 (ja) * | 2016-07-08 | 2020-04-28 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
-
2017
- 2017-12-28 CN CN201711460739.0A patent/CN109979943B/zh active Active
-
2018
- 2018-01-23 US US15/878,278 patent/US10312250B1/en active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007201021A (ja) * | 2006-01-24 | 2007-08-09 | Toshiba Corp | 半導体装置 |
JP2014049717A (ja) * | 2012-09-04 | 2014-03-17 | Toshiba Corp | 半導体装置の製造方法および半導体装置 |
CN104124210A (zh) * | 2013-04-28 | 2014-10-29 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构的形成方法 |
CN104934474A (zh) * | 2014-03-19 | 2015-09-23 | 台湾积体电路制造股份有限公司 | 组合FinFET及其形成方法 |
US9659948B2 (en) * | 2015-09-17 | 2017-05-23 | United Microelectronics Corp. | Semiconductor device and method of fabricating semiconductor device |
CN106653762A (zh) * | 2015-10-30 | 2017-05-10 | 联华电子股份有限公司 | 非挥发性存储器及其制造方法 |
CN107123649A (zh) * | 2016-02-24 | 2017-09-01 | 瑞萨电子株式会社 | 用于制造半导体器件的方法 |
Also Published As
Publication number | Publication date |
---|---|
CN109979943A (zh) | 2019-07-05 |
US10312250B1 (en) | 2019-06-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9443991B2 (en) | Semiconductor device and method of manufacturing the same | |
US9196733B2 (en) | Fin FET and method of fabricating same | |
US9305930B2 (en) | Finfet crosspoint flash memory | |
US7767533B2 (en) | Method and device for providing a contact structure | |
KR100549008B1 (ko) | 등방성식각 기술을 사용하여 핀 전계효과 트랜지스터를제조하는 방법 | |
US8507349B2 (en) | Semiconductor device employing fin-type gate and method for manufacturing the same | |
US11594453B2 (en) | Method of forming a device with split gate non-volatile memory cells, HV devices having planar channel regions and FINFET logic devices | |
US7629215B2 (en) | Semiconductor device and method of manufacturing the same | |
CN109979943B (zh) | 半导体元件及其制造方法 | |
US20230378284A1 (en) | Semiconductor device with non-volatile memory cell and manufacturing method thereof | |
US10971508B2 (en) | Integrated circuit and method of manufacturing the same | |
JP5555211B2 (ja) | 半導体装置及びその製造方法 | |
US20200357801A1 (en) | Memory structure and manufacturing method thereof | |
KR100642383B1 (ko) | 개선된 소거효율을 갖는 플래시 메모리소자 및 그 제조방법 | |
CN111653524A (zh) | 一种鳍式场效应晶体管的制造方法 | |
TW202018917A (zh) | 非揮發性記憶體及其製造方法 | |
CN113838932B (zh) | 半导体结构及其形成方法 | |
CN110752153A (zh) | 半导体结构及其形成方法 | |
US20080014703A1 (en) | Method of fabricating semiconductor integrated circuit device and semiconductor integrated circuit device manufactured using the same | |
US20220157972A1 (en) | Fin-based laterally-diffused metal-oxide semiconductor field effect transistor | |
US6933561B2 (en) | Semiconductor device and method of manufacturing the same | |
KR100698068B1 (ko) | 핀 구조 전계 트랜지스터 및 이의 제조방법 | |
US20070246763A1 (en) | Trench step channel cell transistor and manufacture method thereof | |
TWI565006B (zh) | 記憶元件的製造方法 | |
JP5469893B2 (ja) | 半導体装置及びその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |