CN106206591B - 具有辅助栅极的非易失性存储器单元结构 - Google Patents

具有辅助栅极的非易失性存储器单元结构 Download PDF

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CN106206591B
CN106206591B CN201510255970.0A CN201510255970A CN106206591B CN 106206591 B CN106206591 B CN 106206591B CN 201510255970 A CN201510255970 A CN 201510255970A CN 106206591 B CN106206591 B CN 106206591B
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volatile memory
memory cell
cell structure
auxiliary grid
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CN106206591A (zh
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曹沐潆
陈纬仁
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eMemory Technology Inc
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Abstract

本发明公开了一种具有辅助栅极的非易失性存储器单元结构，包括一半导体衬底，其上设有一N型井区和一P型井区；一第一氧化层定义区和一第二氧化层定义区设于所述N型井区内；一PMOS选择晶体管设于所述第一氧化层定义区上；一PMOS浮动栅极晶体管与所述PMOS选择晶体管串联，其中PMOS浮动栅极晶体管另包含一覆盖于第一氧化层定义区上的浮动栅极；一辅助栅极，自浮动栅极一末端凸出至第二氧化层定义区的一边，使辅助栅极与第二氧化层定义区及N型井区电容耦合。选择晶体管、浮动栅极晶体管以及辅助栅极均同样位于N型井区中。

Description

具有辅助栅极的非易失性存储器单元结构
技术领域
本发明涉及非易失性存储器组件领域，特别涉及一种具有辅助栅极的单层多晶硅非易失性存储器单元结构。
背景技术
非易失性存储器(NVM)组件，例如广泛使用在电子装置中存储数据的电可擦可编程只读存储器(EEPROM)和闪存(flash memory)，具有电可擦除数据和再编程特性，而且在关闭电源的情况下，数据仍可留存。非易失性存储器组件大致上分成多次编程存储器(MTP)和单次编程存储器(OTP)。多次编程存储器(MTP)可多次读出和编程，例如电可擦可编程只读存储器和闪存被设计具有相关的电子电路，可支持不同的操作，例如编程，擦除和读出。单次编程存储器(OTP)具有编程和读出功能的电子电路，但并不具备擦除功能的电子电路。
单层多晶硅非易失性存储器结构因为可减少额外工艺步骤而被提出来。单层多晶硅非易失性存储器用单层多晶硅形成存储电荷的浮动栅极，可和一般互补金属氧化物半导体(CMOS)场效晶体管工艺兼容，因此可应用在嵌入式存储器、混和模式电路的嵌入式非易失性存储器，以及微控制器(例如系统整合芯片，SOC)等领域。
目前已知可用热电子注入(又称为沟道热电子或CHE编程)技术来编程存储器。编程和验证运算时的漏电流，随着核心组件尺寸缩小而恶化。再者，随着闪存组件微缩及存储单元的沟道长度缩小，相邻组件引起的编程干扰也会增加。当编程时，干扰会发生在共享同一字线的相邻存储单元之间。另外，随着所述存储单元单位的尺寸和穿隧氧化层持续微缩，保存资料的遗失和浮动栅极的电荷漏泄问题逐渐严重。因此，业界对于改善非易失性存储器的数据保存能力或耐久度有强烈的需求。
发明内容
本发明的目的为提供一具有辅助栅极的改良单层多晶硅非易失性存储器单元结构，可达到较佳耐久度、较大开/关容许范围、减少编程电流(可减少约百分之20)、降低编程电压，和减少编程干扰。
根据本发明一实施例，具有辅助栅极的非易失性存储器单元结构包括一半导体衬底，其中设有一N型井区；一第一氧化物定义区及一第二氧化物定义区，设于所述N型井区之内；一PMOS选择晶体管设于所述第一氧化物定义区上；一PMOS浮动栅极晶体管设于所述第一氧化物定义区上并与所述PMOS选择晶体管串联，其中所述PMOS浮动栅极晶体管包括一覆盖在所述第一氧化物定义区上的一浮动栅极；以及一辅助栅极，自所述浮动栅极一末端延伸至所述第二氧化物定义区的一边缘，使所述辅助栅极与所述N型井区电容耦合，并且通过N型井区的一偏压来控制耦合至所述辅助栅极的感应电压。
毋庸置疑的，所述领域的技术人士读完接下来本发明优选实施例的详细描述与附图后，均可了解本发明的目的
附图说明
图1是本发明一实施例提供的一种具有单层多晶硅的非易失性存储器单元组件的俯视图。
图2是沿图1切线I-I’截取的横断面示意图。
图3是沿图1切线II-II’截取的横断面示意图。
图4是沿图1切线III-III’截取的横断面示意图。
图5是图1所示具有单层多晶硅的非易失性存储器单元组件1的等效电路。
图6例示图5所示等效电路的编程(PGM)、读出(REG)及擦除(ERS)时的操作条件。
图7说明由图1所示具有单层多晶硅的非易失性存储器单元组件1所组成的存储器数组局布局。
其中，附图标记说明如下：
1 非易失性存储器单元组件
100 半导体衬底
110 N型井区
120 P型井区
200 隔离区
210 第一氧化物定义(OD)区
220 第二氧化物定义(OD)区
230 第三氧化物定义(OD)区
10 选择晶体管
20 浮动栅极晶体管
12 P+源极掺杂区
14 共享P+掺杂区
32 选择栅极通道区
2 选择栅极
2a (选择)栅极介电层
4 浮动栅极
16 漏极掺杂区
34 浮动栅极通道区
4a (浮动)栅极介电层
6 辅助栅极
6a 水平区段
6b 垂直区段
8 擦除栅极
18 N+掺杂区
19 N+掺杂区
PW P型井区
NW N型井区
SL 源极线
BL 位线
EL 擦除线
SG 选择栅极
WL 字线
FG 浮动栅极
AG 辅助栅极
EG 擦除栅极
须注意的是所有附图均为示意图，以说明和制图方便为目的，相对尺寸及比例都经过调整。相同的符号在不同的实施例中代表相对应或类似的特征。
具体实施方式
通过接下来的叙述及所提供的众多特定细节，可充分了解本发明。然而对于此领域中的技术人员，在没有这些特定细节下依然可实行本发明。此外，一些此领域中公知的系统配置和工艺步骤并未在此详述，因为这些应是此领域中的技术人员所熟知的。在不悖离本发明的范围内，可做结构、逻辑和电性上的修改并应用在其他实施例上。
同样地，实施例的附图为示意图，并未照实际比例绘制，为了清楚呈现而放大一些尺寸。在此公开和描述的多个实施例中若具有共通或类似的某些特征时，为了方便图示及描述，类似的特征通常会以相同的标号表示。
专有名词“氧化物定义(oxide define,OD)区”在所述技术领域中普遍认为是一衬底上硅质主表面的某一区域，通常为硅的局部氧化(LOCOS)或浅沟道隔离(STI)区域以外的区域。专有名词“氧化物定义(OD)区”也普遍可被认为是形成及操作有源电路组件例如晶体管的”有源区”。
图1至图4是根据本发明一实施例的一具有单层多晶硅的非易失性存储器单元组件的示意图。图1是根据本发明一实施例的一具有单层多晶硅的非易失性存储器单元组件的布局俯视图。图2是沿着图1切线I-I’方向截取的横断面示意图。图3是沿着图1切线II-II’方向截取的横断面示意图。图4是沿着图1切线III-III’方向截取的横断面示意图。所例示的非易失性存储器单元结构可作为多次编程存储器(MTP)单元。应了解的是本发明也可应用于其他存储器组件。
如图1所示，非易失性存储器单元组件1包含三个被区隔开但彼此紧密排列的氧化物定义(OD)区，包括一第一氧化物定义(OD)区210，一第二氧化物定义(OD)区220，和一第三氧化物定义(OD)区230，由嵌入在一半导体衬底100(例如P型掺杂硅衬底P-Sub)主表面的隔离区200区隔开。根据此实施例，隔离区200可为浅沟道隔离(STI)区，但不仅限于此。应了解图1的布局仅为示意图。
根据本发明实施例，第一氧化物定义(OD)区210及第二氧化物定义(OD)区220位于N型井区(NW)110内，第三氧化物定义(OD)区230位于P型井区(PW)120内。
由图1和图2可知，非易失性存储器单元1包含一选择晶体管10和一与之串联的浮动栅极晶体管20，直接形成在第一氧化物定义(OD)区210上。根据本发明实施例，选择晶体管10为P型金氧半导体(PMOS)晶体管，包含一P+源极掺杂区12(与一源极线SL耦合)位于N型井区(NW)110中；一与P+源极掺杂区12分隔开的共享P+掺杂区14；一选择栅极(SG)通道区32，位于P+源极掺杂区12和共享P+掺杂区14之间并接近半导体衬底100主要表面；一选择栅极(SG)2覆盖在选择栅极通道32区上，并与字线(WL)耦合；一栅极介电层2a，位于选择栅极(SG)2和选择栅极通道区32之间。
一浮动栅极晶体管20位于第一氧化物定义(OD)区210上。浮动栅极晶体管20借由共享P+掺杂区14与选择晶体管10连结。浮动栅极晶体管20与选择晶体管10分享共享P+掺杂区14，因而形成两串连的晶体管，在此实施例中，为两串连的PMOS晶体管。
浮动栅极晶体管20包含一浮动栅极(FG)4，覆盖在第一氧化物定义(OD)区210上。根据本发明实施例，浮动栅极4由单层多晶硅构成，例如N+掺杂多晶硅，或P+掺杂多晶硅，且浮动栅极晶体管20为非易失性存储器单元1的存储组件。选择栅极(SG)2和浮动栅极(FG)4均为直线型，沿着一第1方向(参考x轴方向)延伸。
浮动栅极晶体管20另包含共享P+掺杂区14位于浮动栅极4的一边，一P+掺杂漏极区16位于另外一边，且与擦除线(BL)耦合；一浮动栅极通道区34介于共享P+掺杂区14和P+掺杂漏极区16之间；一栅极介电层4a位于浮动栅极4与浮动栅极通道区34之间。根据本发明实施例，栅极介电层4a的厚度与栅极介电层2a的厚度一致，且选择晶体管10与浮动栅极晶体管20共享N型井区110。
由图1和图3可知，根据本发明实施例，非易失性存储器单元1另包含一辅助栅极(AG)6，自浮动栅极4一末端延伸凸出至第二氧化物定义(OD)区220的一边，且与第二氧化物定义(OD)区220及N型井区110具电容式耦合。由上方俯视，辅助栅极(AG)6部分重叠第二氧化物定义(OD)区220，且部分重叠面对第一氧化物定义(OD)区210的边缘。
在第二氧化物定义(OD)区220未被辅助栅极(AG)6覆盖的区域形成有一N+掺杂区18，N+掺杂区18作为N型井区拾取接点并位于第二氧化物定义(OD)区，提供N型井区110一N型井区电压(VNW)。根据本发明实施例，辅助栅极(AG)6与N型井区110之间不需要额外的掺杂区或离子井区。可借由N型井区电压(VNW)控制一耦合至辅助栅极(AG)6的感测电压。上述感测电压是由于辅助栅极(AG)6与偏压下的N型井区110之间的偶和效应所产生的，将在编程操作时产生更多的载子穿隧至浮动栅极，使得写入效率可以提升。辅助栅极(AG)6可由N+掺杂多晶硅或P+掺杂多晶硅构成。
根据本发明实施例，辅助栅极(AG)6包含一水平区段6a，自浮动栅极(FG)4沿第1方向(参考x轴方向)连续延伸出，并直接与浮动栅极(FG)4相连。辅助栅极(AG)6另包含一垂直区段6b，沿第2方向(参考y轴方向)延伸出，并直接与水平区段6a相连。
根据本发明实施例，辅助栅极(AG)6与浮动栅极(FG)4是由相同的工艺形成。辅助栅极(AG)6可借由N型井区110自动偏压，如此可以增加耦合率和编程效率，也可减少编程干扰和降低编程电流/电压。另外，非易失性存储器单元1可抑制IOFF和IOFF电流上升问题，因而达到较大的耐久性和开/关容忍度。辅助栅极(AG)6提供浮动栅极晶体管20额外能力来补偿耦合比，因而可较有效的控制通道。
由图1和图4可知，根据本发明实施例，非易失性存储器单元1另包含一擦除栅极(EG)8，自垂直区段6b沿着第二方向(参考y轴方向)连续延伸出去，且横越N型井区110和P型井区120的接合处。根据本发明实施例，擦除栅极(EG)8一末端重叠P型井区120内的第三氧层定义(OD)区230，借由这样的结构，擦除栅极(EG)8可与第三氧层定义(OD)区230及P型井区120电容耦合。一N+掺杂区19位于三氧层定义(OD)区230未被擦除栅极(EG)8覆盖的区域上。
图5和图6分别说明图1中的存储单元单位的等效电路并例示编程(PGM)、读出(REG)及擦除(ERS)时的操作条件。根据图5和图6所示，在编程(PGM)操作时，选择栅极(SG)与一字线电压VWL＝VDD连接；擦除线(EL)与一擦除线电压VEL＝VDD连接；源极线(SL)与一源极线电压VSL＝VPP连接；位线(BL)接地(VBL＝0V)；N型井区(NW)110与一N型井区电压VNW＝VPP连接；P型井区(PW)120与一P型井区电压VPW＝0V连接。根据本发明实施例，VPP与VEE可在2V至15V之间，VDD可在2V至10V之间。在上述操作条件下，非易失性存储器单元1可借由沟道热电子注入(CHEI)机制被编程。
在擦除(ERS)操作时，选择栅极(SG)与一字线电压VWL＝0V连接；擦除线(EL)与一擦除线电压VEL＝VEE连接；源极线(SL)与一源极线电压VSL＝0V连接；位线(BL)接地(VBL＝0V)；N型井区(NW)110与一N型井区电压VNW＝0V连接；P型井区(PW)120与一P型井区电压VPW＝0V连接。根据本发明实施例，VPP与VEE可在2V至15V之间，VDD可在2V至10V之间。在上述操作条件下，非易失性存储器单元1可借由Fowler Nordheim(FN)机制被擦除。
在读出(READ)操作时，选择栅极(SG)与一字线电压VWL＝0V连接；擦除线(EL)与一擦除线电压VEL＝0V连接；源极线(SL)与一源极线电压VSL＝VDD连接；位线(BL)接地(VBL＝0V)；N型井区(NW)110与一N型井区电压VNW＝VDD连接；P型井区(PW)120与一P型井区电压VPW＝0V连接。根据本发明实施例，VPP与VEE可为2V至15V之间，VDD可为2V至10V之间。
图7说明由图1所示非易失性存储器单元1所组成的存储器数组局部布局。如图7所示，存储器数组包含至少一非易失性存储器单元1a及一非易失性存储器单元1b。非易失性存储器单元1a即为图1所示结构，而非易失性存储器单元1b则为其对于中心线80的镜像对称。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (13)

1.一种具有辅助栅极的非易失性存储器单元结构，其特征在于，包括
一半导体衬底，其中设有一N型井区；
一第一氧化物定义区及一第二氧化物定义区，设于所述N型井区之内；
一PMOS选择晶体管设于所述第一氧化物定义区上；
一PMOS浮动栅极晶体管设于所述第一氧化物定义区上并与所述PMOS选择晶体管串联，其中所述PMOS浮动栅极晶体管包括一覆盖在所述第一氧化物定义区上的一浮动栅极；
一辅助栅极，自所述浮动栅极一末端延伸至所述第二氧化物定义区的一边缘并覆盖部分所述第二氧化物定义区，使所述辅助栅极与所述N型井区电容耦合；以及
一N+掺杂区，位于所述第二氧化物定义区未被所述辅助栅极覆盖的区域，其中是通过所述N+掺杂区对所述N型井区提供一偏压来控制耦合至所述辅助栅极的感应电压。
2.根据权利要求1所述的具有辅助栅极的非易失性存储器单元结构，其特征在于，所述选择晶体管与所述浮动栅极晶体管共享所述N型井区。
3.根据权利要求1所述的具有辅助栅极的非易失性存储器单元结构，其特征在于，所述选择晶体管包括一P+源极掺杂区，位于所述N型井区内；一共享P+掺杂区，与所述P+源极掺杂区分隔开；一选择栅极通道区，位于所述P+源极掺杂区与所述共享P+掺杂区之间且靠近所述半导体衬底的主表面；一选择栅极，覆盖在所述选择栅极通道区上方；以及一栅极介电层，位于所述选择栅极与所述选择栅极通道区间。
4.根据权利要求3所述的具有辅助栅极的非易失性存储器单元结构，其特征在于，所述P+源极掺杂区与一源极线耦合。
5.根据权利要求3所述的具有辅助栅极的非易失性存储器单元结构，其特征在于，所述共享P+掺杂区位于所述浮动栅极一侧；所述浮动栅极晶体管另包含一位于所述浮动栅极另外一侧的P+漏极掺杂区；一于所述共享P+掺杂区与所述P+漏极掺杂区之间的浮动栅极通道区；一位于所述浮动栅极与所述浮动栅极通道区间的栅极介电层。
6.根据权利要求5所述的具有辅助栅极的非易失性存储器单元结构，其特征在于，所述P+漏极掺杂区与一位线耦合。
7.根据权利要求1所述的具有辅助栅极的非易失性存储器单元结构，其特征在于，所述浮动栅极作为一电荷存储组件。
8.根据权利要求1所述的具有辅助栅极的非易失性存储器单元结构，其特征在于，所述辅助栅极与所述浮动栅极由单层多晶硅一体成型构成。
9.根据权利要求1所述的具有辅助栅极的非易失性存储器单元结构，其特征在于，所述辅助栅极包含N+掺杂多晶硅或P+掺杂多晶硅。
10.根据权利要求1所述的具有辅助栅极的非易失性存储器单元结构，其特征在于，所述辅助栅极包含一自所述浮动栅极沿一第一方向延伸出且与所述浮动栅极相连的水平区段，以及与一自所述水平区段沿一第二方向延伸出且与所述水平区段相连的垂直区段。
11.根据权利要求1所述的具有辅助栅极的非易失性存储器单元结构，其特征在于，另包含一位于所述半导体衬底的P型井区，以及一设于所述P型井区的第三氧化物定义区。
12.根据权利要求11所述的具有辅助栅极的非易失性存储器单元结构，其特征在于，另包含一擦除栅极，自所述浮动栅极延伸出，且横跨所述N型井区与所述P型井区。
13.根据权利要求12所述的具有辅助栅极的非易失性存储器单元结构，其特征在于，所述擦除栅极一末端覆盖在所述第三氧化物定义区上，使所述擦除栅极与所述第三氧化物定义区与所述P型井区电容耦合。
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