WO2023206152A1 - 一种反熔丝存储器及电子设备 - Google Patents

一种反熔丝存储器及电子设备 Download PDF

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Publication number
WO2023206152A1
WO2023206152A1 PCT/CN2022/089605 CN2022089605W WO2023206152A1 WO 2023206152 A1 WO2023206152 A1 WO 2023206152A1 CN 2022089605 W CN2022089605 W CN 2022089605W WO 2023206152 A1 WO2023206152 A1 WO 2023206152A1
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Prior art keywords
voltage
line
memory
gate
tube
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PCT/CN2022/089605
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English (en)
French (fr)
Inventor
潘越
刘畅
徐由
布明恩
刘燕翔
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华为技术有限公司
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Priority to PCT/CN2022/089605 priority Critical patent/WO2023206152A1/zh
Priority to CN202280083745.1A priority patent/CN118382895A/zh
Publication of WO2023206152A1 publication Critical patent/WO2023206152A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards

Definitions

  • the present application relates to the field of electronic technology, and in particular to an antifuse memory and electronic equipment.
  • One-time programmable (OTP) memory is a non-volatile memory that supports one-time programming. It is widely used in the field of embedded chips and is used to store the identification and key of the chip, the code value and redundancy of the chip characteristics. Fixed information such as fixed address code value. OTP memory based on anti-fuse structure has the characteristics of high integration density, good miniaturization and high security, and is a major type of OTP memory.
  • the memory unit of an OTP memory based on an anti-fuse structure usually includes an anti-fuse tube located on a substrate, and the anti-fuse tube has a gate (G), Source (source, S), drain (drain, D), gate oxide layer, and lightly doped drain (LDD) corresponding to S and D.
  • STI shallow trench isolation (shallow trench isolation) .
  • the main working principle of the memory unit is to store information based on whether the gate oxide layer of the antifuse tube is broken down. Before data is written, the gate oxide layer of the antifuse tube exhibits insulating properties, so there is a huge resistance between G and S (or D) of the antifuse tube, and the state is "1" at this time.
  • the breakdown position of the gate oxide layer of the above antifuse tube is uncertain, as shown in (b) in Figure 2. If the breakdown position is located in the middle of the gate oxide layer, instead of (a in Figure 2) ), a high-resistance breakdown path (i.e. G-substrate-S (or D)) is formed between G and S (or D), and the read current is relatively small at this time , thus the read current gap between the two states "0" and "1" is reduced, which will greatly reduce the read success rate.
  • G-substrate-S or D
  • This application provides an anti-fuse memory and electronic equipment for improving the reading success rate of the anti-fuse memory.
  • an anti-fuse memory includes a plurality of bit lines, a plurality of word lines, a plurality of write lines and a plurality of memory cells.
  • the memory unit includes: an active area, and a The selection tube and the anti-fuse tube on the active area; wherein, the selection tube can be used to gate the anti-fuse tube, and the anti-fuse tube can be used to store data; the active area can refer to a single memory unit.
  • the source electrode (also called the second source electrode) of the fuse tube and the first electrode of the drain electrode (also called the second drain electrode) are coupled, and the source electrode of the anti-fuse tube and the third electrode of the drain electrode are coupled.
  • the diode is suspended;
  • the antifuse tube also has a lightly doped drain region located between the source and the drain and in contact with the source and the drain, and the lightly doped drain region is covered by the active region; wherein, the antifuse
  • the portion of the gate of the fuse tube that overlaps the active region in a direction perpendicular to the active region has its orthographic projection on the active region located at the orthogonal position of the lightly doped drain region on the active region. The inside of the projection, that is, the location where the gate oxide layer corresponding to the gate of the antifuse tube may be broken down, is in contact with the lightly doped drain region.
  • the part of the gate of the antifuse tube that overlaps with the active area in the direction perpendicular to the active area has its orthographic projection on the active area located at the point where the lightly doped drain area is on the active area. Interior of orthographic projection.
  • the gate oxide layer of the antifuse tube is broken down, and the breakdown position is located either at the end side of the gate oxide layer or in the middle of the gate oxide layer.
  • the breakdown position can connect the gate of the antifuse tube and the lightly doped drain region, thus forming a conductive path of gate - lightly doped drain region - source (or drain).
  • the resistance of this conductive path is relatively small. Small, it can ensure a large read current when subsequent data is read, and a large gap with the read current when the memory unit is not written, thereby improving the read success rate of the anti-fuse memory.
  • the second gate electrode includes a first portion that overlaps the active area in a direction perpendicular to the active area and has a first width along the first direction.
  • a width is less than or equal to 2 times the extended width of the lightly doped drain region along a first direction, and the first direction is the arrangement direction of the second source electrode and the second drain electrode.
  • the corresponding lightly doped drain region when the first width W1 is less than or equal to 2 times the extended width d1 of the lightly doped drain region along the first direction (that is, W1 ⁇ 2 ⁇ d1), the corresponding lightly doped drain region
  • the doped ions extend from the two edges of the second gate electrode through diffusion in the first direction to just below the second gate electrode, it can be ensured that the orthographic projection of the first part on the active area is located in the lightly doped drain area in the active area. Interior of the orthographic projection on the area.
  • the penetration position can connect the first part of the second gate and the lightly doped drain region. to form a conductive path.
  • the second gate further includes a third gate that at least partially overlaps the active region in a direction perpendicular to the active region and has a second width along the first direction.
  • a third gate that at least partially overlaps the active region in a direction perpendicular to the active region and has a second width along the first direction.
  • Two parts and a third part the first part is located between the second part and the third part, and the first width is smaller than the second width; wherein, the part of the second part and the third part that overlaps with the active area is along the second
  • the length of the direction is equal to the extension width of the lightly doped drain region along the second direction, and the second direction is a direction perpendicular to the first direction.
  • the above lightly doped drain region when the length of the portion of the second part and the third part that overlaps with the active region along the second direction is equal to the extended width d2 of the lightly doped drain region along the second direction, the above lightly doped drain region When the lightly doped ions corresponding to the drain region extend from the edge of the second gate electrode to just below the second gate electrode through diffusion in the second direction, it can ensure that the orthographic projection of the second part and the third part on the active area is located The interior of the orthographic projection of the lightly doped drain region onto the active region.
  • the penetration position can communicate with the second part of the second gate electrode.
  • the lightly doped drain region, or the third part of the second gate electrode and the lightly doped drain region are connected to form a conductive path.
  • the second gate further includes a fourth part and a fifth part having a third width along the first direction, and the fourth part is located on a side of the second part away from the first part, The fifth part is located on a side of the third part away from the first part, and the third width is greater than the second width.
  • the second gate when the second gate has multiple widths along the first direction, and the portions corresponding to the multiple widths are distributed in a stepped manner according to the relationship between the widths, the second gate can be made to have multiple widths along the first direction. Gradually transition from a larger width to a smaller width, thereby improving the reliability of the antifuse tube while reducing the preparation complexity.
  • one side of the second gate in the second direction is a straight line. That is, one side of the plurality of parts with different widths included in the second gate is linearly distributed (or flush) in the second direction, and the other side may be stepped.
  • one side of the second gate in the second direction is a straight line. That is, one side of the plurality of parts with different widths included in the second gate is linearly distributed (or flush) in the second direction, and the other side may be stepped.
  • the selection tube further includes a first gate oxide layer
  • the anti-fuse tube further includes a second gate oxide layer
  • the thickness of the first gate oxide layer is greater than that of the second gate oxide layer. thickness of.
  • the memory further includes a plurality of protection lines
  • the memory unit further includes: a protection tube located on the active area; the protection tube is coupled in series between the selection tube and the inverter. Between the fuse tubes, the protection tube has a third grid, and the third grid is coupled with the protection line.
  • the antifuse memory includes a memory cell array having the plurality of memory cells, and the memory cells located in the same row in the memory cell array share one bit line and are located in the same column.
  • the memory cells share one write line and one word line.
  • the memory cells located in the same row of the memory cell array share one bit line, and the memory cells located in the same column share one write line and one word line, which can improve the performance of the antifuse memory. Integration level, thereby reducing the area of the antifuse memory.
  • the voltage of the selected write line corresponding to the target memory unit is a preset voltage, a voltage of the selected word line
  • the voltage of the selected bit line is one-half of the preset voltage, and the voltage of the selected bit line is zero; the voltage of the non-selected bit line corresponding to the non-target memory cell sharing the selected write line and the selected word line is one-half of the preset voltage.
  • Preset voltage; the voltages of the non-selected write lines and non-selected word lines corresponding to the non-target memory cells that share the selected bit line are both zero; the voltages of the selected bit line, the selected write line, and the selected word line are not shared.
  • the voltages of the unselected write lines and unselected word lines corresponding to the non-target memory cells are both zero, and the voltage of the unselected bit lines is one-half of the preset voltage.
  • the voltage of the selected write line and the voltage of the selected word line corresponding to the target memory unit are both read.
  • voltage and the voltage of the selected bit line are zero;
  • the unselected bit lines corresponding to the non-target memory cells sharing the selected write line and the selected word line are in a floating state;
  • the unselected bit lines corresponding to the non-target memory cells sharing the selected bit line are The voltages of the write line and the unselected word line are both zero; the voltages of the unselected write line and the unselected word line corresponding to the non-target memory cells that do not share the selected bit line, the selected write line, and the selected word line are all zero, and the unselected bit lines are floating.
  • the memory cells located in the same row in the memory cell array also share one protection line.
  • the memory cells located in the same row in the memory cell array also share the protection line, which can improve the integration level of the anti-fuse memory and thereby reduce the area of the anti-fuse memory.
  • the voltage of the selected write line corresponding to the target memory unit is the first preset voltage, the selected word line
  • the voltage of is the write voltage, and the voltage of the selected bit line is zero;
  • the voltage of the non-selected bit line corresponding to the non-target memory cell sharing the selected write line and the selected word line is the write voltage;
  • the voltage of the non-target memory cell sharing the selected bit line is the write voltage;
  • the voltages of the unselected write lines and unselected word lines corresponding to the target memory cell are both zero;
  • the voltage of the non-selected word line and the unselected word line are both zero, the voltage of the unselected bit line is the write voltage;
  • the voltage of the protection line corresponding to the memory cell array is the second preset voltage.
  • the voltage of the selected write line corresponding to the target memory unit is the read voltage
  • the voltages of the bit lines are all the third preset voltage
  • the non-selected bit lines corresponding to the non-target memory cells sharing the selected write line and the selected word line are in a floating state
  • the corresponding non-target memory cells sharing the selected bit line are in a floating state.
  • the voltages of the unselected write lines and unselected word lines are both zero; the unselected write lines and unselected word lines corresponding to the non-target memory cells that do not share the selected bit line, the selected write line, and the selected word line
  • the voltages are all zero, and the unselected bit lines are in a floating state; the voltage of the protection line corresponding to the memory cell array is the third preset voltage.
  • a storage device in a second aspect, includes: a controller and a memory.
  • the controller is used to control reading and writing of the memory.
  • the memory is provided by the first aspect or any possible implementation of the first aspect. Antifuse memory provided.
  • a third aspect provides an electronic device.
  • the electronic device includes a circuit board and a storage device connected to the circuit board.
  • the storage device is the storage device provided in the second aspect.
  • any of the storage devices and electronic devices provided above include the same or corresponding features of the anti-fuse memory provided above. Therefore, the beneficial effects it can achieve can be referred to the above provided The corresponding beneficial effects in the antifuse memory will not be described again here.
  • Figure 1 is a schematic structural diagram of a storage unit in an OTP memory
  • Figure 2 is a schematic diagram after the storage unit in an OTP memory is broken down
  • Figure 3 is a schematic structural diagram of an electronic device provided by an embodiment of the present application.
  • Figure 4 is a schematic structural diagram of an antifuse memory provided by an embodiment of the present application.
  • Figure 5 is a top view and equivalent circuit diagram of a memory unit provided by an embodiment of the present application.
  • Figure 6 is a cross-sectional view of a memory unit provided by an embodiment of the present application.
  • Figure 7 is a top view of another storage unit provided by the embodiment of the present application.
  • Figure 8 is a top view and equivalent circuit diagram of another memory unit provided by an embodiment of the present application.
  • Figure 9 is a cross-sectional view of another memory unit provided by an embodiment of the present application.
  • Figure 10 is a top view and equivalent circuit diagram of another memory unit provided by the embodiment of the present application.
  • Figure 11 is a schematic diagram of two memory units sharing a BL provided by an embodiment of the present application.
  • Figure 12 is a schematic structural diagram of an antifuse memory provided by an embodiment of the present application.
  • Figure 13 is a top view and equivalent circuit diagram of another memory unit provided by the embodiment of the present application.
  • Figure 14 is a schematic diagram of another two memory units sharing a BL provided by an embodiment of the present application.
  • Figure 15 is a schematic structural diagram of another antifuse memory provided by an embodiment of the present application.
  • circuits or other components may be described or referred to as “for” performing one or more tasks.
  • “for” is used to imply structure by indicating that the circuit/component includes structure (eg, circuitry) that performs one or more tasks during operation. Thus, a designated circuit/component may be said to perform the task even when the circuit/component is currently inoperable (e.g., not turned on).
  • Circuits/components used with the wording "for” include hardware, such as circuitry that performs operations, etc.
  • At least one of a, b or c can mean: a, b, c, a and b, a and c, b and c, a, b and c; where a, b and c can It can be single or multiple.
  • the selection tube, antifuse tube and protection tube in the embodiment of the present application may be metal oxide semiconductor (metal oxide semiconductor, MOS) tubes, and the type of the MOS tube may include N-type metal oxide semiconductor (N-type metal oxide semiconductor (NMOS) tube and P-type metal oxide semiconductor (P-type metal oxide semiconductor (PMOS) tube).
  • MOS metal oxide semiconductor
  • NMOS N-type metal oxide semiconductor
  • PMOS P-type metal oxide semiconductor
  • the technical solution of this application can be applied to various electronic devices with antifuse memory.
  • the electronic device may include but is not limited to: mobile phones, tablets, computers, laptops, camcorders, cameras, wearable devices, vehicle-mounted devices (for example, cars, bicycles, electric vehicles, airplanes, ships, trains, high-speed rails, etc.), virtual Reality (virtual reality, VR) equipment, augmented reality (AR) equipment or intelligent robots, etc.
  • vehicle-mounted devices for example, cars, bicycles, electric vehicles, airplanes, ships, trains, high-speed rails, etc.
  • VR virtual reality
  • AR augmented reality
  • FIG. 3 is a schematic structural diagram of an electronic device provided by an embodiment of the present application.
  • the electronic device takes a mobile phone as an example.
  • the electronic device may include: a memory 101, a processor 102, a sensor component 103, a multimedia component 104, and an audio component. 105 and power component 106, etc.
  • the memory 101 can be used to store data, software programs and modules; it mainly includes a stored program area and a stored data area.
  • the stored program area can store an operating system and at least one application required for a function, such as a sound playback function, an image playback function, etc. ;
  • the storage data area can store data created according to the use of the electronic device, such as audio data, image data, phone books, etc.
  • the electronic device may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other volatile solid-state storage device.
  • the memory 101 may include one or more memory devices, and the one or more memory devices may include antifuse memory, double data rate (DDR) memory (DDR for short), etc.; wherein , the antifuse memory can be used to store fixed information in the electronic device, and the DDR can be used to store unfixed information in the electronic device that needs to be modified or updated multiple times.
  • DDR double data rate
  • the processor 102 is the control center of the electronic device, using various interfaces and lines to connect various parts of the entire device, by running or executing software programs and/or modules stored in the memory 101, and calling data stored in the memory 101 , perform various functions of the electronic device and process data, thereby overall monitoring the electronic device.
  • the processor 102 may include one or more processing units.
  • the processor 102 may include a central processing unit (CPU) and a graphics processor (GPU).
  • the CPU mainly processes the operating system. , user interfaces and applications, etc.
  • GPU is a processor specially designed for processing images.
  • the processor 102 may further include other hardware circuits or accelerators, such as field programmable gate arrays or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof, which are not specifically limited in the embodiments of this application.
  • Sensor assembly 103 includes one or more sensors for providing various aspects of status assessment for the electronic device.
  • the sensor component 103 may include a light sensor for detecting the distance between an external object and the electronic device, or may be used in imaging applications, that is, become an integral part of a camera or camera.
  • the sensor component 103 can also include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor or a temperature sensor.
  • the sensor component 103 can detect the acceleration/deceleration, orientation, open/closed state, and relative positioning of the components of the electronic device. , or temperature changes of the electronic device, etc.
  • the multimedia component 104 provides a screen for an output interface between the electronic device and the user.
  • the screen may be a touch panel, and when the screen is a touch panel, the screen may be implemented as a touch screen to receive input signals from the user.
  • the touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensor may not only sense the boundary of a touch or slide action, but also detect the duration and pressure associated with the touch or slide action.
  • the multimedia component 104 also includes at least one camera.
  • the multimedia component 104 includes a front camera and/or a rear camera. When the electronic device is in an operating mode, such as a shooting mode or a video mode, the front camera and/or the rear camera can receive external multimedia data.
  • Each front-facing camera and rear-facing camera can be a fixed optical lens system or have a focal length and optical zoom capabilities.
  • the audio component 105 may provide an audio interface between the user and the electronic device.
  • the audio component 105 may include an audio circuit, a speaker, and a microphone.
  • the audio circuit can transmit the electrical signal converted from the received audio data to the speaker, which converts it into a sound signal for output; on the other hand, the microphone converts the collected sound signal into an electrical signal, which is received by the audio circuit and converted into audio. data, and then output the audio data to be sent to, for example, another electronic device, or output the audio data to the processor 102 for further processing.
  • Power supply component 106 is used to provide power to various components of the electronic device.
  • Power supply component 106 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the electronic device.
  • the electronic device may also include a wireless fidelity (WiFi) module, a Bluetooth module, other input and output modules, etc., which will not be described again in the embodiment of the present application.
  • WiFi wireless fidelity
  • Bluetooth Bluetooth
  • other input and output modules etc.
  • the structure of the electronic device shown in Figure 3 does not constitute a limitation of the electronic device.
  • the electronic device may include more or fewer components than shown in the figure, or combine certain components. Or a different component arrangement.
  • FIG. 4 is a schematic structural diagram of an antifuse memory provided by an embodiment of the present application.
  • the antifuse memory includes a plurality of memory cells, and the memory unit includes: an active area 1, and a selector tube M1 and an antifuse tube M2 located on the active area and coupled in series.
  • the antifuse tube M2 has a second gate electrode G2, a second source electrode S2, a second drain electrode D2, is located between the second source electrode S2 and the second drain electrode D2, and is connected to the second source electrode S2 and the second drain electrode D2. Drain D2 contacts lightly doped drain region LDD2.
  • FIG. 4 takes a memory cell as an example and shows a cross-sectional view of the memory cell cut along a direction perpendicular to the active area 1 .
  • the active area 1 may refer to the planar area on the substrate used to set or deploy a single memory unit (ie, the selection tube M1 and the anti-fuse tube M2), and may also be called the selection tube M1 and the anti-fuse tube of a single memory unit.
  • Each memory unit can correspond to an active area 1 on the substrate, and the active areas 1 corresponding to different memory units can be isolated by shallow trench isolation (STI).
  • STI shallow trench isolation
  • the lightly doped drain region LDD2 may refer to a low doped drain region provided on the substrate close to the second source electrode S2 and the second drain electrode D2. Since there are a large number of carriers near the second drain D2, the hot carrier effect is easily generated.
  • the lightly doped drain region LDD2 is provided to withstand part of the voltage between the second source S2 and the second drain D2. To protect the second drain electrode D2, the low-doped region is called a low-doped drain region.
  • the lightly doped drain region LDD2 occupies the original communication position and can also be used to replace the channel function.
  • the doping concentration of the lightly doped drain region LDD2 may range from 1e 19 cubic centimeters (cm -3 ) to 1 ⁇ e 22 cm -3 .
  • the antifuse tube M2 may also have a gate oxide layer 23 located between the second gate G2 and the lightly doped drain region LDD2.
  • the antifuse tube M2 may also include a first spacer and a second spacer.
  • the first spacer is located on the side of the second gate G2 and the gate oxide layer 23 close to the second source S2.
  • the spacer can be used to isolate the second gate G2 and the second source S2.
  • the second spacer is located on the side of the second gate G2 and the gate oxide layer 23 close to the second drain D2.
  • the second spacer can be used to isolate the second gate G2 and the second source S2.
  • the selection transistor M1 may have a first gate G1, a first source S1 and a first drain D1.
  • the selection transistor M1 can be coupled to the second source S2 of the anti-fuse transistor M2 through the first source S1, or coupled to the second drain D2, or can also be coupled to the second source S2 of the anti-fuse transistor M2 through the first drain D1 and the anti-fuse transistor M2.
  • the second source S2 is coupled or coupled with the second drain D2 to realize series coupling of the selection transistor M1 and the antifuse transistor M2.
  • the coupling of the first drain D1 of the selection transistor M1 and the second source S2 of the antifuse transistor M2 is taken as an example for illustration.
  • the selection transistor M1 may also have lightly doped drain regions LDD11 and LDD12 located between the first source electrode S1 and the first drain electrode D1.
  • the lightly doped drain region LDD11 is in contact with the first source electrode S1, and the lightly doped drain region LDD11 is in contact with the first source electrode S1.
  • the drain region LDD12 is in contact with the first drain electrode D1, but LDD11 and LDD12 are not in contact.
  • the lightly doped drain region LDD12 can be used to protect the first drain electrode D1.
  • a light electrode is usually formed near the two electrodes (ie, the source electrode and the drain electrode) during the manufacturing process.
  • the drain region is doped so that when either one of the two electrodes is used as the drain, corresponding drain protection can be performed through the corresponding lightly doped drain region.
  • the selection transistor M1 may also have a gate oxide layer 13 located between the first gate G1 and the lightly doped drain regions LDD11 and LDD12.
  • the selection tube M1 may also include a third spacer and a fourth spacer.
  • the third spacer is located on the side of the first gate G1 and the gate oxide layer 13 close to the first source S2.
  • the fourth spacer can be used to isolate the first gate G1 and the first source S1.
  • the fourth spacer is located on the side of the first gate G1 and the gate oxide layer 13 close to the first drain D1.
  • the fourth spacer can be used to isolate the first gate. pole G1 and the first drain D1.
  • the selection tube M1 can be used to strobe the anti-fuse tube M2 when writing and reading data, and the anti-fuse tube M2 can be used to store corresponding data, specifically through the anti-fuse Whether the gate oxide layer 23 of the tube M2 is broken down to store information.
  • the gate oxide layer 23 of the anti-fuse tube M2 exhibits insulating properties, so that there is a gap between the second gate electrode G2 of the anti-fuse tube M2 and the second source electrode S2 (or the second drain electrode D2). There is a very large resistance value, and the state is "1" at this time.
  • a preset voltage is applied to the first gate G1 of the selection tube M1 to gate the anti-fuse tube M2, and a high voltage is applied to the second gate G2 of the anti-fuse tube M2.
  • the high voltage breaks down the gate oxide layer 23 of the antifuse tube M2 to form a conductive path between the second gate electrode G2 and the second source electrode S2 (or the second drain electrode D2). At this time, the state is “0” ".
  • the part of the second gate G2 of the anti-fuse tube M2 that overlaps the active area 1 in the direction perpendicular to the active area 1 is in the active area.
  • the orthographic projection on region 1 is located inside the orthographic projection of lightly doped drain region LDD2 on active region 1 .
  • the gate oxide layer 23 of the antifuse tube M2 is broken down, and the breakdown position is located either on the end side of the gate oxide layer 23 or on the gate oxide layer 23 In the middle of Two drains D2), the resistance of this conductive path is small, which can ensure a large read current when subsequently reading data, and a large gap with the read current when the memory unit is not written, thereby improving The read success rate of this antifuse memory.
  • the second gate G2 of the antifuse tube M2 may have one or more widths along the first direction, and the first direction may be the arrangement direction of the second source S2 and the second drain D2.
  • the second gate G2 has multiple widths along the first direction, portions corresponding to the multiple widths may be distributed in a stepped manner according to the size relationship of the widths. The following describes the case where the second gate G2 has one or more widths along the first direction through several possible embodiments.
  • the second gate G2 includes a first portion P1 having a first width W1 along the first direction, and the first portion P1 is perpendicular to The source area 1 overlaps the active area 1 in the direction.
  • the first width W1 is less than or equal to 2 times the extended width d1 of the lightly doped drain region LDD2 along the first direction (that is, W1 ⁇ 2 ⁇ d1).
  • the above-mentioned first direction is the arrangement direction of the second source electrode S2 and the second drain electrode D2.
  • the antifuse tube M2 can be equivalent to a capacitor, so the selection tube M1 and the antifuse Specifically, the series coupling of the tube M2 can be as follows: the first drain D1 of the selection tube M1 is coupled to one end of the capacitor (ie, the second source S2), and the other end of the capacitor is the second gate G2.
  • FIG. 6 is a cross-sectional view of the memory cell cut along the straight line AA' in FIG. 5 .
  • the above-mentioned extension width d1 may also be called a diffusion width, which specifically may refer to the fact that during the formation of the lightly doped drain region LDD2, the corresponding lightly doped ions extend from the edge of the second gate G2 along the first direction through diffusion. to the width directly below the second gate G2.
  • the above lightly doped ions are transferred from the second
  • the two edges of the gate G2 extend through diffusion along the first direction to directly below the second gate G2
  • the orthographic projection of the first part P1 on the active area 1 is located in the lightly doped drain region LDD2 in the active area The interior of the orthographic projection on 1.
  • the drain region LDD2 is doped to form a conductive path.
  • the second gate G2 further includes: at least partially intersecting the active region 1 in a direction perpendicular to the active region 1 .
  • the second portion P2 and the third portion P3 are stacked and have a second width W2 along the first direction, the first portion P1 is located between the second portion P2 and the third portion P3, and the first width W1 is smaller than the second width W2.
  • the length of the portion of the second part P2 and the third part P3 overlapping the active region 1 along the second direction is equal to the extended width d2 of the lightly doped drain region LDD2 along the second direction, and the second direction is the same as the first extension width d2 of the lightly doped drain region LDD2.
  • Orientation Vertical direction is equal to the extended width d2 of the lightly doped drain region LDD2 along the second direction.
  • the above-mentioned extension width d2 may also be called a diffusion width, which may specifically refer to the fact that in the process of forming the lightly doped drain region LDD2, the corresponding lightly doped ions extend from the edge of the second gate G2 along the second direction through diffusion. to the width directly below the second gate G2.
  • (b) in Figure 6 is a cross-sectional view of the memory cell cut along the straight line BB' shown in (a) in Figure 5, with the second part P2 and the third part P3 perpendicular to the active area. The description will be given by taking an example of partially overlapping the active area 1 in the direction of 1.
  • the length of the portion of the second part P2 and the third part P3 overlapping the active region 1 along the second direction is equal to the extended width d2 of the lightly doped drain region LDD2 along the second direction
  • the above-mentioned lightly doped ions extend from the edge of the second gate G2 through diffusion in the second direction to just below the second gate G2, it can ensure that the second part P2 and the third part P3 are aligned in the active region 1.
  • the projection is located inside the orthographic projection of the lightly doped drain region LDD2 on the active region 1 .
  • the penetration position can communicate with the second gate G2
  • the second part P2 and the lightly doped drain region LDD2, or the third part P3 of the second gate G2 and the lightly doped drain region LDD2 are connected to form a conductive path.
  • the second gate G2 further includes: a fourth portion P4 and a fifth portion P5 having a third width W3 along the first direction.
  • the fourth part P4 is located on the side of the second part P2 away from the first part P1
  • the fifth part P5 is located on the side of the third part P3 away from the first part P1
  • the third width W3 is greater than the second width W2.
  • the fourth portion P4 and the fifth portion P5 do not overlap the active area 1 in a direction perpendicular to the active area 1 .
  • Figure 7 is a top view of the memory unit.
  • the second gate G2 may also have other widths along the first direction, such as between the second width and the second width as shown in FIG.
  • a width between the width W2 and the third width W3 the above-mentioned FIG. 7 is only exemplary and does not limit the embodiment of the present application.
  • the second gate G2 when the second gate G2 has multiple widths along the first direction, and the portions corresponding to the multiple widths are distributed in a stepped manner according to the size relationship of the widths, the second gate G2 can be made to have multiple widths along the first direction.
  • One direction gradually transitions from a larger width to a smaller width, thereby reducing the preparation complexity and improving the reliability of the antifuse tube M2.
  • one side of the second gate G2 in the second direction may be a straight line. That is, the second gate G2 includes multiple portions with different widths, one side in the second direction is distributed in a straight line (or is called flush), and the other side may be stepped.
  • the first portion P1 has the first width W1
  • the second portion P2 and the third portion P3 have the second width W2
  • the third portion P3 has the third width W3.
  • the fourth part P4 and the fifth part P5 are distributed in a straight line on one side in the second direction (that is, the side on the left as shown in the figure).
  • the impact of optical proximity correction (OPC) and process fluctuations on the second gate G2 can be reduced during the preparation process, making the preparation
  • the resulting width of the second gate G2 has smaller fluctuations.
  • the thickness of the gate oxide layer 13 in the selector tube M1 may be greater than the gate oxide layer 23 in the antifuse tube M2. thickness of.
  • the thickness of the gate oxide layer 13 in the selection tube M1 may range from 3 nanometers (nm) to 10 nm, and the thickness of the gate oxide layer 23 in the antifuse tube M2 may range from 0.5 nm to 3 nm.
  • the thickness of the gate oxide layer 13 in the selector tube M1 is 7 nm, and the thickness of the gate oxide layer 23 in the antifuse tube M2 is 2 nm.
  • the memory unit may also include a protection tube M3, and the protection tube M3 may be coupled in series between the selection tube M1 and the anti-fuse tube M2.
  • the protection tube M3 has a third gate G3, a third source S3, and a third drain D3.
  • the protection tube M3 can be connected to the selection tube through one of the third source S3 and the third drain D3.
  • M1 is coupled to the anti-fuse tube M2 through the other electrode of the third source electrode S3 and the third drain electrode D3.
  • (a) in Figure 8 is a top view of the memory unit, and (b) in Figure 8 is an equivalent circuit diagram of the memory unit.
  • the antifuse tube M2 can be equivalent to a capacitor.
  • FIG. 8 takes the protection transistor M3 to be coupled to the selection transistor M1 through the third source S3 and to be coupled to the antifuse transistor M2 through the third drain D3 as an example.
  • the protection transistor M3 may also have lightly doped drain regions LDD31 and LDD32 located between the third source S3 and the third drain D3.
  • the lightly doped drain region LDD31 is connected to the third source
  • the contact of electrode S3 can be used to protect the third source electrode S3, the contact between the lightly doped drain region LDD32 and the third drain electrode D3 can be used to protect the third drain electrode D3, and LDD31 and LDD32 are not in contact.
  • the antifuse tube M2 having multiple widths is used as an example for illustration.
  • (a) and (b) in Figure 9 are respectively the memory unit along the straight line AA' and the straight line AA' shown in (a) in Figure 8. Cross-sectional view cut by straight line BB'.
  • the protection transistor M3 may also have a gate oxide layer 33 located between the third gate G3 and the lightly doped drain regions LDD31 and LDD32 .
  • the protection tube M3 may also include a fifth spacer and a sixth spacer.
  • the fifth spacer is located on the side of the third gate G3 and the gate oxide layer 13 close to the third source S3.
  • the sixth spacer can be used to isolate the third gate G3 and the third source S3.
  • the sixth spacer is located on the side of the third gate G3 and the gate oxide layer 33 close to the third drain D3.
  • the sixth spacer can be used to isolate the third gate. pole G3 and the third drain D3.
  • the memory unit may include one or more protection tubes M3 coupled in series; when the memory unit includes a selection tube M1, an antifuse tube M2 and a protection tube M3, both the selection tube M1 and the protection tube M3 It can be a MOSFET tube with a thin gate oxide layer.
  • the thickness of the gate oxide layer in both the selection transistor M1 and the protection transistor M3 can range from 0.5nm to 3nm.
  • the structure of the antifuse tube M2 shown in the above-mentioned FIGS. 4-9 is only exemplary, and the above-mentioned FIGS. 4-9 do not limit the embodiments of the present application.
  • the part of the second gate G2 in the antifuse tube M2 that overlaps the active area 1 in the direction perpendicular to the active area 1 has its orthographic projection on the active area 1 located at the lightly doped drain It suffices that the area LDD2 is inside the orthographic projection on the active area 1 .
  • the antifuse memory may also include: multiple bit lines (BL), multiple word lines (WL), and multiple write lines (program line, PL).
  • BL bit lines
  • WL word lines
  • PL write lines
  • the memory cell when the memory cell includes a selection transistor M1 and an antifuse transistor M2, and does not include a protection transistor M3, the first gate G1 of the selection transistor M1 is coupled to a word line WL, and the selection transistor M1
  • One of the first source electrode S1 and the first drain electrode D1 of M1 is coupled to a bit line BL, and the other electrode of the first source electrode S1 and the first drain electrode D1 is coupled to the second source of the antifuse tube M2
  • the electrode S2 and one of the second drain electrodes D2 are coupled, the other electrode of the second source electrode S2 and the second drain electrode D2 is floating (that is, not connected to other devices or signal lines), and the second electrode of the antifuse tube M2 Gate G2 is coupled to a write line PL.
  • the first gate G1 of the selection tube M1 is coupled to a word line WL, and the first source S1 of the selection tube M1 is coupled to a bit line.
  • the line BL is coupled, the first drain D1 is coupled with the second source S2 of the anti-fuse tube M2, the second drain D2 of the anti-fuse tube M2 is floating, and the second gate G2 of the anti-fuse tube M2 is connected to a write Incoming line PL coupling.
  • (a) in Figure 10 is a top view of the memory unit, and (b) in Figure 10 is an equivalent circuit diagram of the memory unit.
  • the antifuse tube M2 can be equivalent to a capacitor.
  • the plurality of memory cells of the antifuse memory include a first memory unit and a second memory unit, and the first memory unit and the second memory unit may share a bit line BL.
  • the first memory unit is coupled to the word line WL1, the bit line BL1 and the write line PL1 respectively
  • the second memory unit is coupled to the word line WL2, the bit line BL1 and the write line PL2 respectively, that is, the first memory unit The cell and the second memory cell share bit line BL1.
  • Figure 11 is a top view of the first storage unit and the second storage unit.
  • the multiple memory cells included in the antifuse memory can be distributed in an array, that is, the antifuse memory includes multiple rows and multiple columns of memory cells.
  • the multiple rows and multiple columns of memory cells can also be called a memory cell array.
  • the above-mentioned multiple rows and multiple columns may refer to a logical relationship. Specifically, it may refer to a logical "set” or "matrix". In the actual physical arrangement, multiple rows and multiple columns may or may not appear. Multiple columns. In practical applications, as long as the connection relationship between multiple storage units satisfies the connection relationship between storage units in the same row and the same column as described below, they can be considered to belong to the same row or the same column.
  • the antifuse memory includes a memory cell array, a plurality of bit lines BL, a plurality of word lines WL and a plurality of write lines PL
  • the memory cells located in the same row in the memory cell array share one bit line BL.
  • memory cells located in the same column share a write line PL and a word line WL.
  • the memory cell array includes memory cells in m rows and n columns, the plurality of bit lines BL includes BL1 to BLm, the plurality of word lines WL includes WL1 to WLn, and the plurality of bit lines BL includes WL1 to WLn.
  • the write lines PL include PL1 to PLn.
  • the n memory cells located in the i-th row in the memory cell array share the bit line BLi.
  • the value of i ranges from 1 to m.
  • the m memory cells located in the j-th column in the memory cell array share the bit line BLi.
  • the memory cells share the write line PLj and the word line WLj.
  • the value of j ranges from 1 to n, and m and n are integers greater than 1.
  • the voltage of the selected write line SPL corresponding to the target memory cell is the preset voltage VPP, and the voltage of the selected word line SWL is One-half of the preset voltage (i.e. 1/2 ⁇ VPP), the voltage of the selected bit line SBL is zero (i.e. 0V); the corresponding non-target memory cells sharing the selected write line SPL and the selected word line SWL
  • the voltage of the unselected bit line UBL is half the preset voltage (i.e. 1/2 ⁇ VPP); the unselected write line UPL and the unselected word line UWL corresponding to the non-target memory cells sharing the selected bit line SBL
  • the voltages are all zero (i.e.
  • the non-selected write lines UPL and unselected word lines UWL corresponding to the non-target memory cells that do not share the selected bit line SBL, the selected write line SPL and the selected word line SWL The voltages are all zero (that is, 0V), and the voltage of the unselected bit line UBL is one-half of the preset voltage (that is, 1/2 ⁇ VPP).
  • the voltage of the selected write line SPL and the voltage of the selected word line SWL corresponding to the target memory cell are both the read voltage VR and the selected bit.
  • the voltage of line SBL is zero (that is, 0V);
  • the unselected bit line UBL corresponding to the non-target memory cell sharing the selected write line SPL and the selected word line SWL is in a floating state (floating), that is, there is no current on the UBL ( no current) flows through;
  • the voltages of the unselected write lines UPL and unselected word lines UWL corresponding to the non-target memory cells sharing the selected bit line SBL are both zero (i.e.
  • the selected bit line SBL, the The voltages of the unselected write line UPL and the unselected word line UWL corresponding to the non-target memory cells of the selected write line SPL and the selected word line SWL are both zero (that is, 0V), and the unselected bit line UBL is in a floating state (floating state). ).
  • the anti-fuse memory may also include: multiple protection lines YL.
  • the memory cell includes a selection tube M1, an antifuse tube M2 and a protection tube M3, the first gate G1 of the selection tube M1 is coupled to a word line WL, and the first gate G1 of the selection tube M1 is coupled to a word line WL.
  • One of the source electrode S1 and the first drain electrode D1 is coupled to a bit line BL, and the other electrode of the first source electrode S1 and the first drain electrode D1 is coupled to the third source electrode S3 and the third source electrode S3 of the protection tube M3.
  • One pole of the drain D3 is coupled, the third gate G3 of the protection tube M2 is coupled with a protection line YL, and the other pole of the third source S3 and the third drain D3 is coupled with the second pole of the anti-fuse tube M2.
  • One of the source electrode S2 and the second drain electrode D2 is coupled, the other electrode of the second source electrode S2 and the second drain electrode D2 is suspended, and the second gate electrode G2 of the antifuse tube M2 is connected to a write line PL. coupling.
  • the first gate G1 of the selection tube M1 is coupled to a word line WL, and the first source S1 of the selection tube M1 is coupled to a bit line.
  • Line BL is coupled
  • the first drain D1 is coupled with the third source S3 of the protection tube M3
  • the third gate of the protection tube M3 is coupled with a protection line PL
  • the third drain D3 of the protection tube M3 is coupled with the antifuse tube
  • the second source S2 of M2 is coupled, the second drain D2 of the anti-fuse tube M2 is suspended, and the second gate G2 of the anti-fuse tube M2 is coupled to a write line PL.
  • (a) in Figure 13 is a top view of the memory unit
  • (b) in Figure 13 is an equivalent circuit diagram of the memory unit.
  • the antifuse tube M2 can be equivalent to a capacitor.
  • the plurality of memory cells of the antifuse memory include a first memory unit and a second memory unit, and the first memory unit and the second memory unit may share a bit line BL.
  • the first memory unit is coupled to the word line WL1, the bit line BL1, the protection line YL1 and the write line PL1 respectively
  • the second memory unit is coupled to the word line WL2, the bit line BL1, the protection line YL2 and the write line respectively.
  • Line PL2 is coupled, that is, the first memory cell and the second memory cell share bit line BL1.
  • Figure 14 is a top view of the first storage unit and the second storage unit.
  • the antifuse memory includes a memory cell array, a plurality of bit lines BL, a plurality of word lines WL, a plurality of write lines PL and a plurality of protection lines YL
  • the memory cell array located in the same row The memory cells share a bit line BL, and the memory cells located in the same column share a write line PL, a word line WL and a protection line YL.
  • the memory cell array includes memory cells in m rows and n columns, the plurality of bit lines BL includes BL1 to BLm, the plurality of word lines WL includes WL1 to WLn, and the plurality of bit lines BL includes WL1 to WLn.
  • the write lines PL include PL1 to PLn, the protection lines YL include YL1 to YLn, the n memory cells located in the i-th row of the memory cell array share the bit line BLi, and the value of i ranges from 1 to m,
  • the m memory cells located in the jth column of the memory cell array share the write line PLj, the word line WLj and the protection line YLj.
  • the value of j ranges from 1 to n, and m and n are integers greater than 1.
  • the voltage of the selected write line SPL corresponding to the target memory unit is the first preset voltage VPP and the voltage of the selected word line SWL.
  • the voltage is the write voltage VWR, and the voltage of the selected bit line SBL is zero (that is, 0V); the voltage of the unselected bit line UBL corresponding to the non-target memory cell sharing the selected write line SPL and the selected word line SWL is the write voltage VWR ;
  • the voltages of the non-selected write line UPL and the unselected word line UBL corresponding to the non-target memory cells sharing the selected bit line SBL are both zero (that is, 0V); the selected bit line SBL and the selected write line SPL are not shared.
  • the voltages of the unselected write line UPL and the unselected word line UWL corresponding to the non-target memory cells of the selected word line SWL are both zero (that is, 0V), the voltage of the unselected bit line UBL is the write voltage VWR, and the protection line YL1
  • the voltages to YLn are all the second preset voltage VDD2.
  • the voltage of the selected write line SPL corresponding to the target memory cell is the read voltage VR, the voltage of the selected word line SWL and the selected bit line
  • the voltages of SBL are all the third preset voltage VDD;
  • the unselected bit line UBL corresponding to the non-target memory cells sharing the selected write line SPL and the selected word line SWL is in a floating state (floating), that is, there is no current on the UBL (no current) flows through;
  • the voltages of the non-selected write lines UPL and non-selected word lines UWL corresponding to the non-target memory cells sharing the selected bit line SBL are both zero (i.e.
  • the selected bit lines SBL The voltages of the unselected write line UPL and the unselected word line UWL corresponding to the non-target memory cells of the selected write line SPL and the selected word line SWL are both zero (that is, 0V), and the unselected bit line UBL is in a floating state ( floating), the voltages of the protection lines YL1 to YLn are all the third preset voltage VDD.
  • the target memory cell can be controlled. Reading and writing; wherein, after the write operation is performed on the target memory unit, the gate oxide layer 23 of the anti-fuse tube M2 in the target memory unit is broken down, and no matter whether the breakdown position is located at the end side of the gate oxide layer 23 or at In the middle of the gate oxide layer 23, this breakdown position can connect the second gate electrode G2 and the lightly doped drain region LDD2, thereby forming a conductive path of the second gate electrode G2-the lightly doped drain region LDD2-the second source electrode.
  • signal lines for example, bit line BL, write line PL, word line WL, protection line YL
  • the resistance of this conductive path is small, so that when reading the data in the target memory cell, a larger read current can be obtained, which is the same as when the target memory cell is not written. There is a large gap between the read currents, thereby improving the read success rate of the antifuse memory.
  • embodiments of the present application also provide a storage device, which includes a controller and an antifuse memory coupled to the controller.
  • the antifuse memory can be any of the antifuses provided above. memory.
  • the controller can be used to control the read and write operations of the antifuse memory.
  • the storage device may further include a processor coupled to the controller, and the processor may write data into the anti-fuse memory through the controller, or read data stored in the anti-fuse memory.
  • An embodiment of the present application also provides an electronic device.
  • the electronic device includes a circuit board and a storage device connected to the circuit board.
  • the storage device includes an anti-fuse memory.
  • the anti-fuse memory can be any of the above provided An antifuse memory.
  • the circuit board can be a printed circuit board (PCB).
  • the circuit board can also be a flexible printed circuit board (FPC). This embodiment does not limit the circuit board.
  • the electronic device can be different types of user equipment or terminal equipment such as computers, mobile phones, tablets, wearable devices, and vehicle-mounted equipment; the electronic device can also be network equipment such as base stations.
  • the electronic device further includes a packaging substrate, the packaging substrate is fixed on the printed circuit board PCB through solder balls, and the antifuse memory is fixed on the packaging substrate through solder balls.
  • anti-fuse memories in storage devices and electronic equipment, please refer to the above description of anti-fuse memories, and the embodiments of the present application will not be repeated here.

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Abstract

一种反熔丝(anti-fuse)存储器，用于提高反熔丝存储器的读取成功率。该反熔丝存储器包括存储单元，位线、字线和写入线。存储单元包括：有源区，以及位于该有源区且串联耦合的选择管和反熔丝管。选择管的栅极和字线耦合，且源极或漏极与位线耦合。反熔丝管的栅极与写入线耦合，且源极或漏极中的一极与选择管耦合，另一极悬空。反熔丝管还具有设置在源极和漏极之间的轻掺杂漏区(LDD)，该轻掺杂漏区被有源区覆盖。在编程操作后，反熔丝管的栅氧化层被击穿，且击穿位置无论位于栅氧化层的端侧还是中间均能够连通反熔丝管的栅极和轻掺杂漏区，从而形成阻值较小的导电通路：栅极-轻掺杂漏区-源极(或漏极)，以保证读取数据时能够提供较大的读电流。

Description

一种反熔丝存储器及电子设备 技术领域
本申请涉及电子技术领域，尤其涉及一种反熔丝存储器及电子设备。
背景技术
一次可编程(one time programmable，OTP)存储器是一种支持一次编程的非易失性存储器，广泛应用于嵌入式芯片领域，用于存储芯片的标识和密钥、芯片特性的码值和冗余修复的地址码值等固定信息。基于反熔丝(anti-fuse)结构的OTP存储器具有集成密度高、微缩性好和安全性高等特性，是一种主要的OTP存储器类型。
目前，如图1所示，基于反熔丝(anti-fuse)结构的OTP存储器的存储单元通常包括位于衬底上的反熔丝管，该反熔丝管具有栅极(gate，G)、源极(source，S)、漏极(drain，D)、栅氧化层、以及与S和D对应的轻掺杂漏区(light doped drain，LDD)，STI表示浅槽隔离(shallow trench isolation)。其中，该存储单元的主要工作原理是通过反熔丝管的栅氧化层是否被击穿来存储信息。在未写入数据之前，反熔丝管的栅氧化层呈现出绝缘特性，从而反熔丝管的G和S(或D)之间存在极大的阻值，此时为状态“1”。在写入数据时，通过在G上施加一个短时的高电压，该高电压用于击穿栅氧化层，以在G与S(或D)之间形成导电通路，此时为状态“0”，击穿后如图2中的(a)所示。在读取数据时，通过在G与S(或D)之间施加一个较小的读电压，通过检测流过反熔丝管的电流大小即可区分出所存储的数据为“1”或“0”。
但是，上述反熔丝管的栅氧化层的击穿位置是不确定的，如图2中的(b)所示，如果击穿位置位于栅氧化层的中间，而不是图2中的(a)所示的栅氧化层的端侧，则G与S(或D)之间形成高阻值击穿通路(即G-衬底-S(或D))，此时读取电流相对较小，从而“0”和“1”这两种状态之间的读取电流差距减小，这样会大大降低读取成功率。
发明内容
本申请提供一种反熔丝存储器及电子设备，用于提高反熔丝存储器的读取成功率。
为达到上述目的，本申请的实施例采用如下技术方案。
第一方面，提供一种反熔丝存储器，该反熔丝存储器包括多个位线、多个字线、多个写入线和多个存储单元，该存储单元包括：有源区，以及位于该有源区上的选择管和反熔丝管；其中，该选择管可用于选通该反熔丝管，该反熔丝管可用于存储数据；该有源区可以是指单个存储单元的选择管和反熔丝管在衬底上所占用的平面区域；选择管和反熔丝管串联耦合，具体为该选择管的栅极与字线耦合，该选择管的源极和漏极中的第一极与位线耦合；该反熔丝管的栅极(也可称为第二栅极)与写入线耦合，该选择管的源极和漏极中的第二极与该反熔丝管的源极(也可称为第二源极)和漏极(也可称为第二漏极)中的第一极耦合，该反熔丝管的源极和漏极中的第二极悬空；该反熔丝管还具有位于源极与漏极之间且与源极和漏极接触的轻掺杂漏区，该轻掺杂漏区被有源区覆盖；其中，该反熔丝管的栅极在垂直于该有源区的方向上与该有源区交叠的部分，在该有源区上的正投影位于该轻掺杂漏区在该有源区上的正投影的内部，即该反熔丝管的栅极对应的栅氧化层可能被击 穿的位置均与轻掺杂漏区接触。
上述技术方案中，反熔丝管的栅极在垂直于有源区的方向上与有源区交叠的部分，在有源区上的正投影位于轻掺杂漏区在有源区上的正投影的内部。这样，对该存储单元进行编程(或写入)操作后，反熔丝管的栅氧化层被击穿，且击穿位置无论位于栅氧化层的端侧，还是位于栅氧化层的中间，该击穿位置均可连通反熔丝管的栅极与轻掺杂漏区，从而形成的导电通路为栅极-轻掺杂漏区-源极(或漏极)，该导电通路的阻值较小，能够保证后续读取数据时具有较大的读电流，以及与该存储单元未写入时的读电流具有较大的差距，进而提高了该反熔丝存储器的读取成功率。
在第一方面的一种可能的实现方式中，第二栅极包括在垂直于该有源区的方向上与该有源区交叠，且沿第一方向具有第一宽度的第一部分，第一宽度小于或等于2倍的该轻掺杂漏区沿第一方向的扩展宽度，第一方向为第二源极和第二漏极的排列方向。上述可能的实现方式中，当第一宽度W1小于或等于2倍的轻掺杂漏区沿第一方向的扩展宽度d1(即W1≤2×d1)时，上述轻掺杂漏区对应的轻掺杂离子从第二栅极的两个边缘沿第一方向通过扩散延伸至第二栅极的正下方时，能够保证第一部分在有源区上的正投影位于轻掺杂漏区在有源区上的正投影的内部。这样，在反熔丝管中的栅氧化层被击穿后，能够保证在击穿位置位于栅氧化层的中间时，该穿位置可连通第二栅极的第一部分与轻掺杂漏区，以形成导电通路。
在第一方面的一种可能的实现方式中，第二栅极还包括在垂直于该有源区的方向上与该有源区至少部分交叠、且沿第一方向具有第二宽度的第二部分和第三部分，第一部分位于第二部分和第三部分之间，第一宽度小于第二宽度；其中，第二部分和第三部分中与该有源区交叠的部分沿第二方向的长度等于该轻掺杂漏区沿第二方向的扩展宽度，第二方向为与第一方向垂直的方向。上述可能的实现方式中，当第二部分和第三部分中与有源区交叠的部分沿第二方向的长度等于轻掺杂漏区沿第二方向的扩展宽度d2时，上述轻掺杂漏区对应的轻掺杂离子从第二栅极的边缘沿第二方向通过扩散延伸至第二栅极的正下方时，能够保证第二部分和第三部分在有源区上的正投影位于轻掺杂漏区在有源区上的正投影的内部。这样，在反熔丝管中的栅氧化层被击穿后，能够保证在击穿位置位于栅氧化层的端侧或者靠近端侧时，该穿位置可连通第二栅极的第二部分与轻掺杂漏区，或者连通第二栅极的第三部分与轻掺杂漏区，以形成导电通路。
在第一方面的一种可能的实现方式中，第二栅极还包括沿第一方向具有第三宽度的第四部分和第五部分，第四部分位于第二部分远离第一部分的一侧，第五部分位于第三部分远离第一部分的一侧，第三宽度大于第二宽度。上述可能的实现方式中，当第二栅极沿第一方向具有多个宽度，且该多个宽度对应的部分按照宽度的大小关系呈阶梯状分布时，可以使得第二栅极沿第一方向从一个较大的宽度逐渐过渡到一个较小的宽度，从而在降低制备复杂度的同时，提高反熔丝管的可靠性。
在第一方面的一种可能的实现方式中，第二栅极在第二方向上的一条边为直线。也即是，第二栅极包括的具有不同宽度的多个部分在第二方向上的一条侧边呈直线分布(或者称为齐平)，另一条侧边可以为阶梯状。上述可能的实现方式中，通过设置第二栅极在第二方向上的一条边为直线，可以在制备过程中减小OPC和工艺波动对第二栅极的影响，使得制备得到的第二栅极的宽度波动更小。
在第一方面的一种可能的实现方式中，该选择管还包括第一栅氧化层，该反熔丝管还包括第二栅氧化层，第一栅氧化层的厚度大于第二栅氧化层的厚度。上述可能的实现方式中，通过设置选择管中的栅氧化层的厚度大于反熔丝管中栅氧化层的厚度，可以对反熔丝管进行电压保护作用，从而提高反熔丝存储器中存储单元的使用寿命。
在第一方面的一种可能的实现方式中，该存储器还包括多个保护线，该存储单元还包括：位于该有源区上的保护管；该保护管串联耦合在该选择管和该反熔丝管之间，该保护管具有第三栅极，第三栅极与该保护线耦合。上述可能的实现方式中，通过设置保护管，该保护管串联耦合在该选择管和该反熔丝管之间，可以对反熔丝管进行电压保护作用，从而提高反熔丝存储器中存储单元的使用寿命。
在第一方面的一种可能的实现方式中，该反熔丝存储器包括具有该多个存储单元的存储单元阵列，该存储单元阵列中位于同一行的存储单元共用一个该位线，位于同一列的存储单元共用一个该写入线和一个该字线。上述可能的实现方式中，该存储单元阵列中位于同一行的存储单元共用一个该位线，位于同一列的存储单元共用一个该写入线和一个该字线，可以提高该反熔丝存储器的集成度，从而降低该反熔丝存储器的面积。
在第一方面的一种可能的实现方式中，当向该存储单元阵列中的目标存储单元写数据时，该目标存储单元对应的选中写入线的电压为预设电压、选中字线的电压为二分之一的该预设电压、选中位线的电压为零；共用该选中写入线和该选中字线的非目标存储单元对应的非选中位线的电压为二分之一的该预设电压；共用该选中位线的非目标存储单元对应的非选中写入线和非选中字线的电压均为零；未共用该选中位线、该选中写入线和该选中字线的非目标存储单元对应的非选中写入线和非选中字线的电压均为零、非选中位线的电压为二分之一的该预设电压。上述可能的实现方式中，通过在不同的位线、字线和写入线上施加相应的电压，即可实现对该存储单元的写操作。
在第一方面的一种可能的实现方式中，当从该存储单元阵列中的目标存储单元读取数据时，该目标存储单元对应的选中写入线的电压和选中字线的电压均为读电压、选中位线的电压为零；共用该选中写入线和该选中字线的非目标存储单元对应的非选中位线为悬空状态；共用该选中位线的非目标存储单元对应的非选中写入线和非选中字线的电压均为零；未共用该选中位线、该选中写入线和该选中字线的非目标存储单元对应的非选中写入线和非选中字线的电压均为零、非选中位线为悬空状态。上述可能的实现方式中，通过在不同的位线、字线和写入线上施加相应的电压，即可实现对该存储单元的读操作。
在第一方面的一种可能的实现方式中，当该反熔丝存储器还包括多个保护线时，该存储单元阵列中位于同一行的存储单元还共用一个该保护线。上述可能的实现方式中，该存储单元阵列中位于同一行的存储单元还共用一个该保护线，可以提高该反熔丝存储器的集成度，从而降低该反熔丝存储器的面积。
在第一方面的一种可能的实现方式中，当向该存储单元阵列中的目标存储单元写数据时，该目标存储单元对应的选中写入线的电压为第一预设电压、选中字线的电压为写电压、选中位线的电压为零；共用该选中写入线和该选中字线的非目标存储单元对应的非选中位线的电压为该写电压；共用该选中位线的非目标存储单元对应的非选中写入线和非选中字线的电压均为零；未共用该选中位线、该选中写入线和该选中字线的非目标存储单元对应的非选中写入线和非选中字线的电压均为零、非选中位线的电压为该写电压；该存储 单元阵列对应的保护线的电压为第二预设电压。上述可能的实现方式中，通过在不同的位线、字线、写入线和保护线上施加相应的电压，即可实现对该存储单元的写操作。
在第一方面的一种可能的实现方式中，当从该存储单元阵列中的目标存储单元读取数据时，该目标存储单元对应的选中写入线的电压为读电压、选中字线和选中位线的电压均为第三预设电压；共用该选中写入线和该选中字线的非目标存储单元对应的非选中位线为悬空状态；共用该选中位线的非目标存储单元对应的非选中写入线和非选中字线的电压均为零；未共用该选中位线、该选中写入线和该选中字线的非目标存储单元对应的非选中写入线和非选中字线的电压均为零、非选中位线为悬空状态；该存储单元阵列对应的保护线的电压为第三预设电压。上述可能的实现方式中，通过在不同的位线、字线、写入线和保护线上施加相应的电压，即可实现对该存储单元的读操作。
第二方面，提供一种存储装置，该存储装置包括：控制器和存储器，该控制器用于控制该存储器的读写，该存储器为第一方面或第一方面的任一种可能的实现方式所提供的反熔丝存储器。
第三方面，提供一种电子设备，该电子设备包括电路板、以及与该电路板连接的存储装置，该存储装置为第二方面所提供的存储装置。
可以理解地是，上述提供的任一种存储装置和电子设备包含了上文所提供的反熔丝存储器的相同或相对应的特征，因此，其所能达到的有益效果可参考上文所提供的对应的反熔丝存储器中的有益效果，此处不再赘述。
附图说明
图1为一种OTP存储器中的存储单元的结构示意图；
图2为一种OTP存储器中的存储单元被击穿后的示意图；
图3为本申请实施例提供的一种电子设备的结构示意图；
图4为本申请实施例提供的一种反熔丝存储器的结构示意图；
图5为本申请实施例提供的一种存储单元的俯视图和等效电路图；
图6为本申请实施例提供的一种存储单元的剖面图；
图7为本申请实施例提供的另一种存储单元的俯视图；
图8为本申请实施例提供的另一种存储单元的俯视图和等效电路图；
图9为本申请实施例提供的另一种存储单元的剖面图；
图10为本申请实施例提供的又一种存储单元的俯视图和等效电路图；
图11为本申请实施例提供的一种共用BL的两个存储单元的示意图；
图12为本申请实施例提供的一种反熔丝存储器的结构示意图；
图13为本申请实施例提供的另一种存储单元的俯视图和等效电路图；
图14为本申请实施例提供的另一种共用BL的两个存储单元的示意图；
图15为本申请实施例提供的另一种反熔丝存储器的结构示意图。
具体实施方式
下文将详细论述各实施例的制作和使用。但应了解，本申请提供的许多适用发明概念可实施在多种具体环境中。所论述的具体实施例仅仅说明用以实施和使用本说明和本技术的具体方式，而不限制本申请的范围。
除非另有定义，否则本文所用的所有科技术语都具有与本领域普通技术人员公知的含 义相同的含义。
各电路或其它组件可描述为或称为“用于”执行一项或多项任务。在这种情况下，“用于”用来通过指示电路/组件包括在操作期间执行一项或多项任务的结构(例如电路系统)来暗指结构。因此，即使当指定的电路/组件当前不可操作(例如未打开)时，该电路/组件也可以称为用于执行该任务。与“用于”措辞一起使用的电路/组件包括硬件，例如执行操作的电路等。
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述。在本申请中，“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b或c中的至少一项(个)，可以表示：a，b，c，a和b，a和c，b和c，a、b和c；其中a、b和c可以是单个，也可以是多个。
本申请的实施例采用了“第一”和“第二”等字样对名称或功能或作用类似的对象进行区分，本领域技术人员可以理解“第一”和“第二”等字样并不对数量和执行次序进行限定。“耦合”一词用于表示电性连接，包括通过导线或连接端直接相连或通过其他器件间接相连。因此“耦合”应被视为是一种广义上的电子通信连接。
另外，本申请实施例中的选择管、反熔丝管和保护管可以是金属氧化物半导体(metal oxide semiconductor，MOS)管，该MOS管的类型可以包括N型金属氧化物半导体(N-type metal oxide semiconductor，NMOS)管和P型金属氧化物半导体(P-type metal oxide semiconductor，PMOS)管。
需要说明的是，本申请中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其他实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
本申请的技术方案可以应用于具有反熔丝存储器的各种电子设备中。该电子设备可以包括但不限于：手机、平板电脑、计算机、笔记本电脑、摄像机、照相机、可穿戴设备、车载设备(例如，汽车、自行车、电动车、飞机、船舶、火车、高铁等)、虚拟现实(virtual reality，VR)设备、增强现实(augmented reality，AR)设备或者智能机器人等。为方便描述，本申请中将上面提到的设备统称为电子设备。
图3为本申请实施例提供的一种电子设备的结构示意图，该电子设备以手机为例进行说明，该电子设备可以包括：存储器101、处理器102、传感器组件103、多媒体组件104、音频组件105和电源组件106等。
下面结合图3对该电子设备的各个构成部件进行具体的介绍：
存储器101可用于存储数据、软件程序以及模块；主要包括存储程序区和存储数据区，其中，存储程序区可存储操作系统、至少一个功能所需的应用程序，比如声音播放功能、图像播放功能等；存储数据区可存储根据该电子设备的使用所创建的数据，比如音频数据、图像数据、电话本等。此外，该电子设备可以包括高速随机存取存储器，还可以包括非易 失性存储器，例如至少一个磁盘存储器件、闪存器件、或其他易失性固态存储器件。在本申请实施例中，存储器101可以包括一个或者多个存储器件，这一个或者多个存储器件可以包括反熔丝存储器、双倍速率(double data rate，DDR)存储器(简称DDR)等；其中，该反熔丝存储器可用于存储该电子设备中的固定信息，该DDR可用于存储该电子设备中需要多次修改或更新的不固定的信息。
处理器102是该电子设备的控制中心，利用各种接口和线路连接整个设备的各个部分，通过运行或执行存储在存储器101内的软件程序和/或模块，以及调用存储在存储器101内的数据，执行该电子设备的各种功能和处理数据，从而对该电子设备进行整体监控。可选地，处理器102可以包括一个或多个处理单元，比如，处理器102可以包括中央处理器(central processing unit，CPU)和图像处理器(graphic processing unit，GPU)，CPU主要处理操作系统、用户界面和应用程序等，GPU是专门设计的用于处理图像的一种处理器。此外，处理器102还可以进一步包括其他硬件电路或加速器，如现场可编程门阵列或者其他可编程逻辑器件、晶体管逻辑器件、硬件部件或者其任意组合等，本申请实施例对此不作具体限制。
传感器组件103包括一个或多个传感器，用于为该电子设备提供各个方面的状态评估。其中，传感器组件103可以包括光传感器，用于检测外部物体与该电子设备的距离，或者在成像应用中使用，即成为相机或摄像头的组成部分。此外，传感器组件103还可以包括加速度传感器，陀螺仪传感器，磁传感器，压力传感器或温度传感器，通过传感器组件103可以检测到该电子设备的加速/减速、方位、打开/关闭状态，组件的相对定位，或该电子设备的温度变化等。
多媒体组件104在该电子设备和用户之间的提供一个输出接口的屏幕，该屏幕可以为触摸面板，且当该屏幕为触摸面板时，屏幕可以被实现为触摸屏，以接收来自用户的输入信号。触摸面板包括一个或多个触摸传感器以感测触摸、滑动和触摸面板上的手势。所述触摸传感器可以不仅感测触摸或滑动动作的边界，而且还检测与所述触摸或滑动操作相关的持续时间和压力。此外，多媒体组件104还包括至少一个摄像头，比如，多媒体组件104包括一个前置摄像头和/或后置摄像头。当该电子设备处于操作模式，如拍摄模式或视频模式时，前置摄像头和/或后置摄像头可以接收外部的多媒体数据。每个前置摄像头和后置摄像头可以是一个固定的光学透镜系统或具有焦距和光学变焦能力。
音频组件105可提供用户与该电子设备之间的音频接口，比如，音频组件105可以包括音频电路、扬声器和麦克风。音频电路可将接收到的音频数据转换后的电信号，传输到扬声器，由扬声器转换为声音信号输出；另一方面，麦克风将收集的声音信号转换为电信号，由音频电路接收后转换为音频数据，再输出音频数据以发送给比如另一该电子设备，或者将音频数据输出至处理器102以便进一步处理。
电源组件106用于为该电子设备的各个组件提供电源，电源组件106可以包括电源管理系统，一个或多个电源，及其他与该电子设备生成、管理和分配电力相关联的组件。
尽管未示出，该电子设备还可以包括无线保真(wireless fidelity，WiFi)模块、蓝牙模块和其它输入输出模块等，本申请实施例在此不再赘述。本领域技术人员可以理解，图3中示出的该电子设备的结构并不构成对该电子设备的限定，该电子设备可以包括比图示更多或更少的部件，或者组合某些部件，或者不同的部件布置。
图4为本申请实施例提供的一种反熔丝存储器的结构示意图。该反熔丝存储器包括多个存储单元，该存储单元包括：有源区1、以及位于有源区上且串联耦合的选择管M1和反熔丝管M2。其中，反熔丝管M2具有第二栅极G2、第二源极S2、第二漏极D2、位于第二源极S2与第二漏极D2之间且与第二源极S2和第二漏极D2接触的轻掺杂漏区LDD2。图4中以一个存储单元为例，示出了该存储单元沿垂直于有源区1的方向进行切分后的剖面图。
其中，有源区1可以是指衬底上用于设置或部署单个存储单元(即选择管M1和反熔丝管M2)的平面区域，也可以称为单个存储单元的选择管M1和反熔丝管M2在衬底上所占用的平面区域。每个存储单元在衬底上均可以对应一个有源区1，不同存储单元对应的有源区1之间可以通过浅槽隔离(shallow trench isolation，STI)隔离开。
另外，轻掺杂漏区LDD2可以是指在衬底上靠近第二源极S2和第二漏极D2的位置设置的一个低掺杂的漏区。由于第二漏极D2附近存在大量载流子，容易产生热载流子效应，设置的该轻掺杂漏区LDD2可用于承受第二源极S2与第二漏极D2之间的部分电压，以保护第二漏极D2，从而低掺杂区域被称为低掺杂的漏区。该轻掺杂漏区LDD2占据了原有沟通的位置，还可用于替换沟道的功能。可选的，轻掺杂漏区LDD2的掺杂浓度的范围可以为1e 19立方厘米(cm -3)至1×e 22cm -3。
进一步的，反熔丝管M2还可以具有位于第二栅极G2与轻掺杂漏区LDD2之间的栅氧化层23。在实际应用中，反熔丝管M2还可以包括第一侧墙和第二侧墙，第一侧墙位于第二栅极G2和栅氧化层23靠近第二源极S2的一侧，第一侧墙可用于隔离第二栅极G2和第二源极S2，第二侧墙位于第二栅极G2和栅氧化层23靠近第二漏极D2的一侧，第二侧墙可用于隔离第二栅极G2和第二漏极D2。
可选的，选择管M1可以具有第一栅极G1、第一源极S1和第一漏极D1。其中，选择管M1可以通过第一源极S1与反熔丝管M2的第二源极S2耦合、或者与第二漏极D2耦合，也可以通过第一漏极D1与反熔丝管M2的第二源极S2耦合、或者与第二漏极D2耦合，以实现选择管M1和反熔丝管M2的串联耦合。图4中以选择管M1的第一漏极D1与反熔丝管M2的第二源极S2耦合为例进行说明。进一步的，选择管M1还可以具有位于第一源极S1与第一漏极D1之间的轻掺杂漏区LDD11和LDD12，轻掺杂漏区LDD11与第一源极S1接触，轻掺杂漏区LDD12与第一漏极D1接触，LDD11与LDD12不接触，轻掺杂漏区LDD12可用于保护第一漏极D1。
需要说明的是，由于第一源极S1和第一漏极D1的位置是可以互换的，从而在制造过程中通常会在两个电极(即源极和漏极)的附近分别形成一个轻掺杂漏区，以便于后续在将该两个电极中的任意一个电极作为漏极时，均可以通过对应的轻掺杂漏区进行相应的漏极保护。
此外，选择管M1还可以具有位于第一栅极G1、与轻掺杂漏区LDD11和LDD12之间的栅氧化层13。在实际应用中，选择管M1也可以包括第三侧墙和第四侧墙，第三侧墙位于第一栅极G1和栅氧化层13靠近第一源极S2的一侧，第三侧墙可用于隔离第一栅极G1和第一源极S1，第四侧墙位于第一栅极G1和栅氧化层13靠近第一漏极D1的一侧，第四侧墙可用于隔离第一栅极G1和第一漏极D1。
具体的，在该存储单元中，该选择管M1可用于在写入和读取数据时选通反熔丝管 M2，该反熔丝管M2可用于存储相应的数据，具体是通过反熔丝管M2的栅氧化层23是否被击穿来存储信息。在未写入数据之前，反熔丝管M2的栅氧化层23呈现出绝缘特性，从而反熔丝管M2的第二栅极G2与第二源极S2(或第二漏极D2)之间存在极大的阻值，此时为状态“1”。在写入数据时，通过在选择管M1的第一栅极G1施加一个预设电压以选通反熔丝管M2，并在反熔丝管M2的第二栅极G2上施加一个高电压，通过该高电压击穿反熔丝管M2的栅氧化层23，以在第二栅极G2与第二源极S2(或第二漏极D2)之间形成导电通路，此时为状态“0”。
在本申请实施例提供的反熔丝存储器的存储单元中，反熔丝管M2的第二栅极G2在垂直于有源区1的方向上与有源区1交叠的部分，在有源区1上的正投影位于轻掺杂漏区LDD2在有源区1上的正投影的内部。这样，对该存储单元进行编程(或写入)操作后，反熔丝管M2的栅氧化层23被击穿，且击穿位置无论位于栅氧化层23的端侧，还是位于栅氧化层23的中间，该击穿位置均可连通第二栅极G2与轻掺杂漏区LDD2，从而形成的导电通路为第二栅极G2-轻掺杂漏区LDD2-第二源极S2(或第二漏极D2)，该导电通路的阻值较小，能够保证后续读取数据时具有较大的读电流，以及与该存储单元未写入时的读电流具有较大的差距，进而提高了该反熔丝存储器的读取成功率。
进一步的，反熔丝管M2的第二栅极G2沿第一方向可以具有一个或者多个宽度，第一方向可以为第二源极S2和第二漏极D2的排列方向。可选的，当第二栅极G2沿第一方向具有多个宽度时，该多个宽度对应的部分可以按照宽度的大小关系呈阶梯状分布。下面通过几种可能的实施例对第二栅极G2沿第一方向具有一个或者多个宽度的情况进行介绍说明。
在一种可能的实施例中，如图5和图6中的(a)所示，第二栅极G2包括沿第一方向具有第一宽度W1的第一部分P1，第一部分P1在垂直于有源区1的方向上与有源区1交叠。第一宽度W1小于或等于2倍的轻掺杂漏区LDD2沿第一方向的扩展宽度d1(即W1≤2×d1)。上述第一方向为第二源极S2和第二漏极D2的排列方向。图5中的(a)为该存储单元的俯视图，图5中的(b)为该存储单元的等效电路图，反熔丝管M2可以等效为一个电容，从而选择管M1与反熔丝管M2串联耦合具体可以为：选择管M1的第一漏极D1与该电容的一端(即第二源极S2)耦合，该电容的另一端为第二栅极G2。图6中的(a)为该存储单元沿图5中的直线AA’进行切分后的剖面图。
其中，上述扩展宽度d1也可以称为扩散宽度，具体可以是指在形成轻掺杂漏区LDD2的过程中，对应的轻掺杂离子从第二栅极G2的边缘沿第一方向通过扩散延伸至第二栅极G2的正下方的宽度。
上述可能的实施例中，当第一宽度W1小于或等于2倍的轻掺杂漏区LDD2沿第一方向的扩展宽度d1(即W1≤2×d1)时，上述轻掺杂离子从第二栅极G2的两个边缘沿第一方向通过扩散延伸至第二栅极G2的正下方时，能够保证第一部分P1在有源区1上的正投影位于轻掺杂漏区LDD2在有源区1上的正投影的内部。这样，在反熔丝管M2中的栅氧化层23被击穿后，能够保证在击穿位置位于栅氧化层23的中间时，该穿位置可连通第二栅极G2的第一部分P1与轻掺杂漏区LDD2，以形成导电通路。
在另一种可能的实施例中，如图5和图6中的(b)所示，第二栅极G2还包括：在垂直于有源区1的方向上与有源区1至少部分交叠、且沿第一方向具有第二宽度W2的第二 部分P2和第三部分P3，第一部分P1位于第二部分P2和第三部分P3之间，第一宽度W1小于第二宽度W2。其中，第二部分P2和第三部分P3中与有源区1交叠的部分沿第二方向的长度等于轻掺杂漏区LDD2沿第二方向的扩展宽度d2，第二方向为与第一方向垂直的方向。
其中，上述扩展宽度d2也可以称为扩散宽度，具体可以是指在形成轻掺杂漏区LDD2的过程中，对应的轻掺杂离子从第二栅极G2的边缘沿第二方向通过扩散延伸至第二栅极G2的正下方的宽度。图6中的(b)为该存储单元沿图5中的(a)所示的直线BB’进行切分后的剖面图，且以第二部分P2和第三部分P3在垂直于有源区1的方向上与有源区1部分交叠为例进行说明。
上述可能的实施例中，当第二部分P2和第三部分P3中与有源区1交叠的部分沿第二方向的长度等于轻掺杂漏区LDD2沿第二方向的扩展宽度d2时，上述轻掺杂离子从第二栅极G2的边缘沿第二方向通过扩散延伸至第二栅极G2的正下方时，能够保证第二部分P2和第三部分P3在有源区1上的正投影位于轻掺杂漏区LDD2在有源区1上的正投影的内部。这样，在反熔丝管M2中的栅氧化层23被击穿后，能够保证在击穿位置位于栅氧化层23的端侧或者靠近端侧时，该穿位置可连通第二栅极G2的第二部分P2与轻掺杂漏区LDD2，或者连通第二栅极G2的第三部分P3与轻掺杂漏区LDD2，以形成导电通路。
在又一种可能的实施例中，结合图5和图6，如图7所示，第二栅极G2还包括：沿第一方向具有第三宽度W3的第四部分P4和第五部分P5，第四部分P4位于第二部分P2远离第一部分P1的一侧，第五部分P5位于第三部分P3远离第一部分P1的一侧，第三宽度W3大于第二宽度W2。第四部分P4和第五部分P5在垂直于有源区1的方向上与有源区1不交叠。图7为该存储单元的俯视图。
需要说明的是，第二栅极G2沿第一方向除了具有上述第一宽度W1、第二宽度W2和第三宽度W3之外，还可以具有其它宽度，比如图7所示的介于第二宽度W2与第三宽度W3之间的一个宽度，上述图7仅为示例性的，并不对本申请实施例构成限制。
上述可能的实施例中，当第二栅极G2沿第一方向具有多个宽度，且该多个宽度对应的部分按照宽度的大小关系呈阶梯状分布时，可以使得第二栅极G2沿第一方向从一个较大的宽度逐渐过渡到一个较小的宽度，从而在降低制备复杂度的同时，提高反熔丝管M2的可靠性。
可选的，当第二栅极G2沿第一方向具有两个宽度或者两个以上的宽度时，第二栅极G2在第二方向上的一条边可以为直线。也即是，第二栅极G2包括的具有不同宽度的多个部分在第二方向上的一条侧边呈直线分布(或者称为齐平)，另一条侧边可以为阶梯状。示例性的，如图7所示的第二栅极G2中，具有第一宽度W1的第一部分P1、具有第二宽度W2的第二部分P2和第三部分P3、以及具有第三宽度W3的第四部分P4和第五部分P5，在第二方向上的一条侧边(即图中示出的位于左边的侧边)呈直线分布。通过设置第二栅极G2在第二方向上的一条边为直线，可以在制备过程中减小光学邻近效应修正(optical proximity correction，OPC)和工艺波动对第二栅极G2的影响，使得制备得到的第二栅极G2的宽度波动更小。
进一步的，结合图4-图7，在该存储单元包括选择管M1和反熔丝管M2时，选择管M1中的栅氧化层13的厚度可以大于反熔丝管M2中的栅氧化层23的厚度。通过设置选 择管M1中的栅氧化层13的厚度大于反熔丝管M2中栅氧化层23的厚度，可以对反熔丝管M2进行电压保护作用。
在一种示例中，选择管M1中的栅氧化层13的厚度范围可以为3纳米(nm)至10nm，反熔丝管M2中的栅氧化层23的厚度范围可以为0.5nm至3nm。比如，选择管M1中的栅氧化层13的厚度为7nm，反熔丝管M2中的栅氧化层23的厚度为2nm。
进一步的，结合图4-图7，如图8所示，该存储单元还可以包括保护管M3，保护管M3可以串联耦合在选择管M1与反熔丝管M2之间。可选的，保护管M3具有第三栅极G3、第三源极S3、第三漏极D3，保护管M3可以分别通过第三源极S3和第三漏极D3中的一极与选择管M1耦合，通过第三源极S3和第三漏极D3中的另一极与反熔丝管M2耦合。图8中的(a)为该存储单元的俯视图，图8中的(b)为该存储单元的等效电路图，反熔丝管M2可以等效为一个电容。图8中的(b)以保护管M3通过第三源极S3与选择管M1耦合，通过第三漏极D3与反熔丝管M2耦合为例进行说明。
可选的，如图9所示，保护管M3还可以具有位于第三源极S3和第三漏极D3之间的轻掺杂漏区LDD31和LDD32，轻掺杂漏区LDD31与第三源极S3接触可用于保护第三源极S3，轻掺杂漏区LDD32与第三漏极D3接触可用于保护第三漏极D3，LDD31与LDD32不接触。上述图9中以反熔丝管M2具有多个宽度为例进行说明，图9中的(a)和(b)分别为该存储单元沿图8中的(a)所示的直线AA’和直线BB’进行切分后的剖面图。
此外，如图9所示，保护管M3还可以具有位于第三栅极G3、与轻掺杂漏区LDD31与LDD32之间的栅氧化层33。在实际应用中，保护管M3也可以包括第五侧墙和第六侧墙，第五侧墙位于第三栅极G3和栅氧化层13靠近第三源极S3的一侧，第五侧墙可用于隔离第三栅极G3和第三源极S3，第六侧墙位于第三栅极G3和栅氧化层33靠近第三漏极D3的一侧，第六侧墙可用于隔离第三栅极G3和第三漏极D3。
需要说明的是，该存储单元中可以包括串联耦合的一个或者多个保护管M3；在该存储单元包括选择管M1、反熔丝管M2和保护管M3时，选择管M1和保护管M3均可以是具有薄栅氧化层的MOSFET管。比如，选择管M1和保护管M3中栅氧化层的厚度范围均可以为0.5nm至3nm。
另外，上述图4-图9中示出的反熔丝管M2的结构仅是示例性的，上述图4-图9并不对本申请实施例构成限制。在实际应用中，反熔丝管M2中第二栅极G2在垂直于有源区1的方向上与有源区1交叠的部分，在有源区1上的正投影位于轻掺杂漏区LDD2在有源区1上的正投影的内部即可。
进一步的，该反熔丝存储器还可以包括：多个位线(bit line，BL)、多个字线(word line，WL)和多个写入线(program line，PL)。其中，对于该反熔丝存储器的存储单元，该存储单元中的选择管M1可以分别与一个字线WL和一个位线BL耦合，该存储单元中的反熔丝管M2可以与一个写入线PL耦合。
在一种可能的实施例中，当该存储单元包括选择管M1和反熔丝管M2、且不包括保护管M3时，选择管M1的第一栅极G1与一个字线WL耦合，选择管M1的第一源极S1和第一漏极D1中的一极与一个位线BL耦合，第一源极S1和第一漏极D1中的另一极与反熔丝管M2的第二源极S2和第二漏极D2中的一极耦合，第二源极S2和第二漏极D2中的另一极悬空(即不连接其它器件或信号线)，反熔丝管M2的第二栅极G2与一个写 入线PL耦合。
在一种示例中，结合图5，如图10所示，在该存储单元中，选择管M1的第一栅极G1与一个字线WL耦合，选择管M1的第一源极S1与一个位线BL耦合，第一漏极D1与反熔丝管M2的第二源极S2耦合，反熔丝管M2的第二漏极D2悬空，反熔丝管M2的第二栅极G2与一个写入线PL耦合。图10中的(a)为该存储单元的俯视图，图10中的(b)为该存储单元的等效电路图，反熔丝管M2可以等效为一个电容。
在另一种示例中，该反熔丝存储器的多个存储单元中包括第一存储单元和第二存储单元，第一存储单元和第二存储单元可以共用一个位线BL。如图11所示，第一存储单元分别与字线WL1、位线BL1和写入线PL1耦合，第二存储单元分别与字线WL2、位线BL1和写入线PL2耦合，即第一存储单元和第二存储单元共用位线BL1。图11为第一存储单元和第二存储单元的俯视图。
可选的，该反熔丝存储器包括的多个存储单元可以呈阵列分布，即该反熔丝存储器包括多行多列的存储单元，该多行多列的存储单元也可以称为存储单元阵列。其中，上述多行多列可以是指逻辑上的关系，具体可以是指逻辑上的一种“集合”或者“矩阵”，在实际物理排列上可以呈现多行多列，也可以不呈现多行多列。在实际应用中，只需多个存储单元的连接关系满足下文中关于同一行和同一列的存储单元的连接关系即可认为属于同一行或同一列。进一步的，在该反熔丝存储器包括存储单元阵列、多个位线BL、多个字线WL和多个写入线PL时，该存储单元阵列中位于同一行的存储单元共用一个位线BL，位于同一列的存储单元共用一个写入线PL和一个字线WL。
在一种实现方式中，如图12所示，该存储单元阵列包括m行n列的存储单元，该多个位线BL包括BL1至BLm，该多个字线WL包括WL1至WLn，该多个写入线PL包括PL1至PLn，该存储单元阵列中位于第i行的n个存储单元共用位线BLi，i的取值范围为1至m，该存储单元阵列中位于第j列的m个存储单元共用写入线PLj和字线WLj，j的取值范围为1至n，m和n为大于1的整数。
具体的，如下表1所示，当向该存储单元阵列中的目标存储单元写数据时，该目标存储单元对应的选中写入线SPL的电压为预设电压VPP、选中字线SWL的电压为二分之一的预设电压(即1/2×VPP)、选中位线SBL的电压为零(即0V)；共用该选中写入线SPL和该选中字线SWL的非目标存储单元对应的非选中位线UBL的电压为二分之一的预设电压(即1/2×VPP)；共用该选中位线SBL的非目标存储单元对应的非选中写入线UPL和非选中字线UWL的电压均为零(即0V)；未共用该选中位线SBL、该选中写入线SPL和该选中字线SWL的非目标存储单元对应的非选中写入线UPL和非选中字线UWL的电压均为零(即0V)、非选中位线UBL的电压为二分之一的预设电压(即1/2×VPP)。
表1
Figure PCTCN2022089605-appb-000001
如下表2所示，当从该存储单元阵列中的目标存储单元读取数据时，该目标存储单元对应的选中写入线SPL的电压和选中字线SWL的电压均为读电压VR、选中位线SBL的 电压为零(即0V)；共用该选中写入线SPL和该选中字线SWL的非目标存储单元对应的非选中位线UBL为悬空状态(floating)，即该UBL上没有电流(no current)流过；共用该选中位线SBL的非目标存储单元对应的非选中写入线UPL和非选中字线UWL的电压均为零(即0V)；未共用该选中位线SBL、该选中写入线SPL和该选中字线SWL的非目标存储单元对应的非选中写入线UPL和非选中字线UWL的电压均为零(即0V)、非选中位线UBL为悬空状态(floating)。
表2
Figure PCTCN2022089605-appb-000002
进一步的，该反熔丝存储器还可以包括：多个保护线YL。在一种可能的实施例中，当该存储单元包括选择管M1、反熔丝管M2和保护管M3时，选择管M1的第一栅极G1与一个字线WL耦合，选择管M1的第一源极S1和第一漏极D1中的一极与一个位线BL耦合，第一源极S1和第一漏极D1中的另一极与保护管M3的第三源极S3和第三漏极D3中的一极耦合，保护管M2的第三栅极G3与一个保护线YL耦合，第三源极S3和第三漏极D3中的另一极与反熔丝管M2的第二源极S2和第二漏极D2中的一极耦合，第二源极S2和第二漏极D2中的另一极悬空，反熔丝管M2的第二栅极G2与一个写入线PL耦合。
在一种示例中，结合图8，如图13所示，在该存储单元中，选择管M1的第一栅极G1与一个字线WL耦合，选择管M1的第一源极S1与一个位线BL耦合，第一漏极D1与保护管M3的第三源极S3耦合，保护管M3的第三栅极与一个保护线PL耦合，保护管M3的第三漏极D3与反熔丝管M2的第二源极S2耦合，反熔丝管M2的第二漏极D2悬空，反熔丝管M2的第二栅极G2与一个写入线PL耦合。图13中的(a)为该存储单元的俯视图，图13中的(b)为该存储单元的等效电路图，反熔丝管M2可以等效为一个电容。
在另一种示例中，该反熔丝存储器的多个存储单元中包括第一存储单元和第二存储单元，第一存储单元和第二存储单元可以共用一个位线BL。如图14所示，第一存储单元分别与字线WL1、位线BL1、保护线YL1和写入线PL1耦合，第二存储单元分别与字线WL2、位线BL1、保护线YL2和写入线PL2耦合，即第一存储单元和第二存储单元共用位线BL1。图14为第一存储单元和第二存储单元的俯视图。
可选的，在该反熔丝存储器包括存储单元阵列、多个位线BL、多个字线WL、多个写入线PL和多个保护线YL时，该存储单元阵列中位于同一行的存储单元共用一个位线BL，位于同一列的存储单元共用一个写入线PL、一个字线WL和一个保护线YL。
在一种实现方式中，如图15所示，该存储单元阵列包括m行n列的存储单元，该多个位线BL包括BL1至BLm，该多个字线WL包括WL1至WLn，该多个写入线PL包括PL1至PLn，该多个保护线YL包括YL1至YLn，该存储单元阵列中位于第i行的n个存储单元共用位线BLi，i的取值范围为1至m，该存储单元阵列中位于第j列的m个存储单元共用写入线PLj、字线WLj和保护线YLj，j的取值范围为1至n，m和n为大于1的整数。
具体的，如下表3所示，当向该存储单元阵列中的目标存储单元写数据时，该目标存 储单元对应的选中写入线SPL的电压为第一预设电压VPP、选中字线SWL的电压为写电压VWR、选中位线SBL的电压为零(即0V)；共用该选中写入线SPL和该选中字线SWL的非目标存储单元对应的非选中位线UBL的电压为写电压VWR；共用该选中位线SBL的非目标存储单元对应的非选中写入线UPL和非选中字线UBL的电压均为零(即0V)；未共用该选中位线SBL、该选中写入线SPL和该选中字线SWL的非目标存储单元对应的非选中写入线UPL和非选中字线UWL的电压均为零(即0V)、非选中位线UBL的电压为写电压VWR，保护线YL1至YLn的电压均为第二预设电压VDD2。
表3
Figure PCTCN2022089605-appb-000003
如下表4所示，当从该存储单元阵列中的目标存储单元读取数据时，该目标存储单元对应的选中写入线SPL的电压为读电压VR、选中字线SWL的电压和选中位线SBL的电压均为第三预设电压VDD；共用该选中写入线SPL和该选中字线SWL的非目标存储单元对应的非选中位线UBL为悬空状态(floating)，即该UBL上没有电流(no current)流过；共用该选中位线SBL的非目标存储单元对应的非选中写入线UPL和非选中字线UWL的电压均为零(即0V)；未共用该选中位线SBL、该选中写入线SPL和该选中字线SWL的非目标存储单元对应的非选中写入线UPL和非选中字线UWL的电压均为零(即0V)、非选中位线UBL为悬空状态(floating)，保护线YL1至YLn的电压均为第三预设电压VDD。
表4
Figure PCTCN2022089605-appb-000004
在本申请实施例中，通过对该反熔丝存储器中的不同信号线(比如，位线BL、写入线PL、字线WL、保护线YL)施加相应的电压，可以实现对目标存储单元的读写；其中，对目标存储单元进行写操作后，目标存储单元中反熔丝管M2的栅氧化层23被击穿，且无论击穿位置无论位于栅氧化层23的端侧，还是位于栅氧化层23的中间，该击穿位置均可连通第二栅极G2与轻掺杂漏区LDD2，从而形成的导电通路为第二栅极G2-轻掺杂漏区LDD2-第二源极S2(或第二漏极D2)，该导电通路的阻值较小，这样在读取目标存储单元中数据时，能够获得较大的读电流，该读电流与该目标存储单元未写入时的读电流之间具有较大的差距，从而提高了该反熔丝存储器的读取成功率。
基于此，本申请实施例还提供一种存储装置，该存储装置包括控制器、以及与控制器耦合的反熔丝存储器，该反熔丝存储器可以为上文所提供的任一种反熔丝存储器。其中， 该控制器可用于控制该反熔丝存储器的读写操作。进一步，该存储装置还可以包括与控制器耦合的处理器，该处理器可以通过控制器向该反熔丝存储器中写入数据，或者读取该反熔丝存储器中存储的数据。
本申请实施例还提供一种电子设备，该电子设备包括电路板、以及与电路板连接的存储装置，该存储装置包括反熔丝存储器，该反熔丝存储器可以为上文所提供的任一种反熔丝存储器。其中，该电路板可以为印制电路板(printed circuit board，PCB)，当然电路板还可以为柔性电路板(flexible printed circuit board，FPC)等，本实施例对电路板不作限制。可选的，该电子设备为计算机、手机、平板电脑、可穿戴设备和车载设备等不同类型的用户设备或者终端设备；该电子设备还可以为基站等网络设备。
可选的，该电子设备还包括封装基板，该封装基板通过焊球固定于印刷电路板PCB上，该反熔丝存储器通过焊球固定于封装基板上。
需要说明的是，关于存储装置和电子设备中反熔丝存储器的相关描述，具体可以参见上文中关于反熔丝存储器的描述，本申请实施例在此不再赘述。
最后应说明的是：以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何在本申请揭露的技术范围内的变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (15)

  1. 一种反熔丝存储器，其特征在于，所述反熔丝存储器包括多个位线、多个字线、多个写入线和多个存储单元，所述存储单元包括：
    有源区，以及位于所述有源区上的选择管和反熔丝管；
    所述选择管具有第一栅极、第一源极和第一漏极，所述第一栅极与所述字线耦合，所述第一源极和所述第一漏极中的第一极与所述位线耦合；
    所述反熔丝管具有第二栅极、第二源极、第二漏极、以及位于所述第二源极与所述第二漏极之间且与所述第二源极和所述第二漏极接触的轻掺杂漏区，所述第二栅极与所述写入线耦合，所述第一源极和所述第一漏极中的第二极与所述第二源极和所述第二漏极中的第一极耦合，所述第二源极和所述第二漏极中的第二极悬空；
    其中，所述第二栅极在垂直于所述有源区的方向上与所述有源区交叠的部分，在所述有源区上的正投影位于所述轻掺杂漏区在所述有源区上的正投影的内部。
  2. 根据权利要求1所述的反熔丝存储器，其特征在于，所述第二栅极包括在垂直于所述有源区的方向上与所述有源区交叠，且沿第一方向具有第一宽度的第一部分，所述第一宽度小于或等于2倍的所述轻掺杂漏区沿所述第一方向的扩展宽度，所述第一方向为所述第二源极和所述第二漏极的排列方向。
  3. 根据权利要求2所述的反熔丝存储器，其特征在于，所述第二栅极还包括在垂直于所述有源区的方向上与所述有源区至少部分交叠、且沿所述第一方向具有第二宽度的第二部分和第三部分，所述第一部分位于所述第二部分和所述第三部分之间，所述第一宽度小于所述第二宽度；
    其中，所述第二部分和所述第三部分中与所述有源区交叠的部分沿第二方向的长度等于所述轻掺杂漏区沿所述第二方向的扩展宽度，所述第二方向为与所述第一方向垂直的方向。
  4. 根据权利要求3所述的反熔丝存储器，其特征在于，所述第二栅极还包括沿所述第一方向具有第三宽度的第四部分和第五部分，所述第四部分位于所述第二部分远离所述第一部分的一侧，所述第五部分位于所述第三部分远离所述第一部分的一侧，所述第三宽度大于所述第二宽度。
  5. 根据权利要求3或4所述的反熔丝存储器，其特征在于，所述第二栅极在所述第二方向上的一条边为直线。
  6. 根据权利要求1-5任一项所述的反熔丝存储器，其特征在于，所述选择管还包括第一栅氧化层，所述反熔丝管还包括第二栅氧化层，所述第一栅氧化层的厚度大于所述第二栅氧化层的厚度。
  7. 根据权利要求1-6任一项所述的反熔丝存储器，其特征在于，所述存储器还包括多个保护线，所述存储单元还包括：位于所述有源区上的保护管；
    所述保护管串联耦合在所述选择管和所述反熔丝管之间，所述保护管具有第三栅极，所述第三栅极与所述保护线耦合。
  8. 根据权利要求1-7任一项所述的反熔丝存储器，其特征在于，所述反熔丝存储器包括具有所述多个存储单元的存储单元阵列，所述存储单元阵列中位于同一行的存储单元共 用一个所述位线，位于同一列的存储单元共用一个所述写入线和一个所述字线。
  9. 根据权利要求8所述的反熔丝存储器，其特征在于，当向所述存储单元阵列中的目标存储单元写数据时，所述目标存储单元对应的选中写入线的电压为预设电压、选中字线的电压为二分之一的所述预设电压、选中位线的电压为零；共用所述选中写入线和所述选中字线的非目标存储单元对应的非选中位线的电压为二分之一的所述预设电压；共用所述选中位线的非目标存储单元对应的非选中写入线和非选中字线的电压均为零；未共用所述选中位线、所述选中写入线和所述选中字线的非目标存储单元对应的非选中写入线和非选中字线的电压均为零、非选中位线的电压为二分之一的所述预设电压。
  10. 根据权利要求8或9所述的反熔丝存储器，其特征在于，当从所述存储单元阵列中的目标存储单元读取数据时，所述目标存储单元对应的选中写入线的电压和选中字线的电压均为读电压、选中位线的电压为零；共用所述选中写入线和所述选中字线的非目标存储单元对应的非选中位线为悬空状态；共用所述选中位线的非目标存储单元对应的非选中写入线和非选中字线的电压均为零；未共用所述选中位线、所述选中写入线和所述选中字线的非目标存储单元对应的非选中写入线和非选中字线的电压均为零、非选中位线为悬空状态。
  11. 根据权利要求8所述的反熔丝存储器，其特征在于，当所述反熔丝存储器还包括多个保护线时，所述存储单元阵列中位于同一行的存储单元还共用一个所述保护线。
  12. 根据权利要求11所述的反熔丝存储器，其特征在于，当向所述存储单元阵列中的目标存储单元写数据时，所述目标存储单元对应的选中写入线的电压为第一预设电压、选中字线的电压为写电压、选中位线的电压为零；共用所述选中写入线和所述选中字线的非目标存储单元对应的非选中位线的电压为所述写电压；共用所述选中位线的非目标存储单元对应的非选中写入线和非选中字线的电压均为零；未共用所述选中位线、所述选中写入线和所述选中字线的非目标存储单元对应的非选中写入线和非选中字线的电压均为零、非选中位线的电压为所述写电压；所述存储单元阵列对应的保护线的电压为第二预设电压。
  13. 根据权利要求11或12所述的反熔丝存储器，其特征在于，当从所述存储单元阵列中的目标存储单元读取数据时，所述目标存储单元对应的选中写入线的电压为读电压、选中字线和选中位线的电压均为第三预设电压；共用所述选中写入线和所述选中字线的非目标存储单元对应的非选中位线为悬空状态；共用所述选中位线的非目标存储单元对应的非选中写入线和非选中字线的电压均为零；未共用所述选中位线、所述选中写入线和所述选中字线的非目标存储单元对应的非选中写入线和非选中字线的电压均为零、非选中位线为悬空状态；所述存储单元阵列对应的保护线的电压为所述第三预设电压。
  14. 一种存储装置，其特征在于，所述存储装置包括：控制器和存储器，所述控制器用于控制所述存储器的读写，所述存储器为权利要求1-13任一项所述的反熔丝存储器。
  15. 一种电子设备，其特征在于，所述电子设备包括电路板、以及与所述电路板连接的存储装置，所述存储装置为权利要求14所述的存储装置。
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