WO2022252099A1 - 磁性随机存储器及其控制方法、电子设备 - Google Patents

磁性随机存储器及其控制方法、电子设备 Download PDF

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WO2022252099A1
WO2022252099A1 PCT/CN2021/097558 CN2021097558W WO2022252099A1 WO 2022252099 A1 WO2022252099 A1 WO 2022252099A1 CN 2021097558 W CN2021097558 W CN 2021097558W WO 2022252099 A1 WO2022252099 A1 WO 2022252099A1
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line
mtj
electrically connected
read
random access
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PCT/CN2021/097558
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English (en)
French (fr)
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李文静
叶力
向清懿
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华为技术有限公司
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Priority to PCT/CN2021/097558 priority Critical patent/WO2022252099A1/zh
Priority to CN202180086979.7A priority patent/CN116648749A/zh
Publication of WO2022252099A1 publication Critical patent/WO2022252099A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect

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  • the present application relates to the technical field of semiconductors, and in particular to a magnetic random access memory (MRAM), a control method thereof, and an electronic device including the magnetic random access memory.
  • MRAM magnetic random access memory
  • the magnetic random access memory based on the magnetic tunnel junction (magnetic tunnel junction, MTJ) as the storage unit has many excellent characteristics at the same time, such as: non-volatile storage of data, read Fast writing speed, unlimited erasing and writing life, low reading and writing power consumption, etc., are more and more widely used.
  • Fig. 1 shows the structure of the storage unit MTJ in the spin-orbit torque (spin-orbit torque, SOT) magnetic random access memory. layer)02 and free layer (free layer)03.
  • spin-orbit torque spin-orbit torque, SOT
  • both the reference layer 01 and the free layer 03 are ferromagnetic materials
  • the tunnel layer 02 is insulating material, semiconductor material or ferroelectric material, etc.
  • the free layer 03 is close to the spin hall effect (spin hall effect, SHE) electrode line 04, and electrically connected with SHE electrode line 04.
  • the magnetization direction of the reference layer 01 does not change during the information writing process, and the magnetization direction of the free layer 03 can be changed by a magnetic field or an electric current, so that the magnetization direction of the free layer 03 is parallel or antiparallel to the magnetization direction of the reference layer 01, That is, the information is written.
  • the MTJ When the magnetization direction of the free layer 03 is parallel to the magnetization direction of the reference layer 01, the MTJ has low resistance characteristics, and when the two are antiparallel, the MTJ has high resistance characteristics, that is, the MTJ exhibits tunneling magneto resistance (TMR). )effect.
  • TMR tunneling magneto resistance
  • the high and low resistance characteristics of the MTJ represent two different logic information (such as "0" or "1").
  • the memory cell shown in Figure 1 writes information through the spin hall effect (spin hall effect, SHE).
  • the SHE electrode line 04 is generally made of heavy metal or other materials with a large spin Hall angle.
  • the writing principle of the memory cell MTJ14 is: to pass a current into the SHE electrode line 04, and the SHE electrode line 04 will generate Spin-polarized electrons, the spin-polarized electrons diffuse into the adjacent free layer 03, interact with the magnetic moment in the free layer 03, thereby changing the magnetization direction of the free layer 03, and the magnetization direction of the free layer 03 is consistent with the SHE
  • the direction of the current in the electrode line 04 is related. When the current flow in the SHE electrode line 04 is changed, the magnetization direction of the free layer 03 can be reversed to the opposite direction, so that different logic information can be written in the MTJ14.
  • This application provides a magnetic random access memory and its control method, and electronic equipment containing the magnetic random access memory.
  • the main purpose is to introduce the MTJ with unidirectional conductivity into the MRAM, which can reduce the leakage power consumption of information reading and writing, and also It can increase storage density and increase storage capacity.
  • the present application provides a magnetic random access memory, which includes a substrate and a plurality of memory cells arrayed on the substrate, any memory cell includes: SHE electrode lines, at least one magnetic tunnel junction MTJ, and a transistor with three terminals; any MTJ includes a stacked reference layer (also called a pinning layer), a tunnel layer, and a free layer, and the free layer is closer to the SHE electrode line than the reference layer , and the free layer is electrically connected to the SHE electrode line, and the transistor is electrically connected to the SHE electrode line; in particular, the MTJ here has unidirectional conductivity, that is, the MTJ is in a forward conduction state when the current in the first direction is applied, and It is in the reverse cut-off state when the current in the second direction is passed, and the first direction and the second direction are opposite to each other. It can also be said that the current is passed from one end of the MTJ, and the MTJ has a high resistance state, and the current is reverse
  • the MTJ in the magnetic random access memory of the present application can be understood in this way.
  • the MTJ is a MTJ structure with unidirectional conduction characteristics.
  • the current flows from the reference layer to the free layer, and the MTJ structure is in a low resistance state of conduction.
  • the current flows from the free layer to the reference layer, and the MTJ structure is in a cut-off high-resistance state; for another example, when the current flows from the free layer to the reference layer, the MTJ structure is in a conduction low-resistance state, on the contrary, the current flows from the reference layer to the free layer, the MTJ structure is in a cut-off high resistance state. Therefore, by adopting the MTJ with this structure, the current crosstalk between different MTJs can be effectively reduced and leakage power consumption can be reduced when performing read and write operations.
  • the use of selectors such as pass transistors or diodes can be reduced or omitted, thereby increasing storage density and storage capacity.
  • the magnetic random access memory of the present application adopts the writing operation principle combining the voltage-regulated magnetic anisotropy VCMA effect and the spin-orbit torque SOT effect.
  • the VCMA effect means that when a voltage is applied across the MTJ, it will change the vertical anisotropy of the MTJ free layer, thereby reducing (or increasing) the critical switching current density of the free layer magnetic moment, and at the same time passing a certain write on the SHE electrode line
  • the current can make the magnetic moment of the free layer flip (or not change), and the magnitude of the VCMA effect is proportional to the voltage difference across the MTJ.
  • this application adopts the MTJ with unidirectional conductivity, it is not necessary to connect a selector in series with the MTJ to prevent the leakage of the array, so as to avoid the voltage division of the selector due to its internal resistance and reduce the actual drop.
  • the magnitude of the voltage across the MTJ weakens the VCMA effect. Therefore, by introducing an MTJ structure with unidirectional conduction characteristics, the VCMA effect can be further enhanced, and the working voltage range of read and write operations can be improved.
  • the ratio of the forward on-current I on to the reverse off-current I off of the MTJ structure is greater than or equal to 10.
  • the tunnel layer of the MTJ includes at least two tunnel layers made of different materials.
  • stacked first tunnel layer and second tunnel layer, the first tunnel layer and the second tunnel layer are made of different materials
  • the material of the first tunnel layer and the second tunnel layer can be AlO, ZnO, CoO, MgO, etc.
  • One of metal oxides, or at least one of ferroelectric materials or semiconductor materials can be selected.
  • the first tunnel layer and the second tunnel layer have different thicknesses along the stacking direction.
  • the conduction direction of the MTJ structure can be adjusted to realize the MTJ structure with unidirectional conduction.
  • the reference layer includes a SrRuO 3 material
  • the free layer includes a La 2/3 Sr 1/3 MnO 3 material.
  • the magnetic materials of the reference layer and the free layer are doped with impurities.
  • impurities By doping impurities to change the energy band structure at the Fermi energy of the two-layer structure, thereby adjusting the electrical characteristics of the MTJ structure to achieve unidirectional conduction characteristics.
  • any one of the memory cells has an MTJ
  • the magnetic random access memory further includes: a source line, a bit line, a word line and a read line; one end of the SHE electrode line is electrically connected to the bit line, The other end of the SHE electrode line is electrically connected to the first end of the transistor, the second end of the transistor is electrically connected to the source line, the gate of the transistor is electrically connected to the word line, and the reference layer is electrically connected to the read line.
  • the word line corresponding to the MTJ is used to receive a gate bias voltage, so as to turn on the transistor electrically connected to the word line;
  • the read line is used for grounding; one signal line of the source line and bit line electrically connected to the MTJ is used to receive the write voltage, and the other signal line is used for grounding to generate a write current in the SHE electrode line, in the spin track Under the action of the torque effect, the magnetic moment of the free layer of the MTJ is reversed to complete the information writing. For example, when the source line receives the write voltage and the bit line is grounded, the logic information “0” is written; on the contrary, when the bit line receives the write voltage and the source line is grounded, the logic information “1” is written.
  • the reading line electrically connected to the MTJ is used to receive the reading voltage; Both source and bit lines are connected to ground so that the MTJ is in a forward conduction state for the read current from the reference layer to the free layer.
  • the read line electrically connected to the remaining MTJ structures in the MRAM is used for grounding; the bit line electrically connected to the remaining MTJ structures is used for receiving the read voltage, and the source line can be used for grounding, In order to make the direction of the read current in the remaining MTJs be from the free layer to the reverse cut-off state of the reference layer. In this way, the leakage current of this structure is small, and the power consumption during reading is reduced. Moreover, all the word lines in the MRAM are grounded, so that the transistors controlled by the word lines are all turned off.
  • the read line electrically connected to the MTJ is used for grounding; the bit electrically connected to the MTJ
  • the source line is used to receive the read voltage, and the source line is used to ground, so that the MTJ is in the forward conduction state of the read current from the free layer to the reference layer.
  • the read lines electrically connected to the remaining MTJ structures in the MRAM are used to receive the read voltage; the source lines and bit lines electrically connected to the remaining MTJs are both used to ground, so that the remaining MTJs
  • the read current direction in is from the free layer to the reverse cut-off state of the reference layer.
  • the leakage current of this structure is small, which reduces power consumption during reading.
  • all the word lines in the MRAM are grounded, so that the transistors controlled by the word lines are all turned off.
  • the multiple MTJs can be arranged side by side, and the free layers of the multiple MTJs are electrically connected to the same SHE electrode line.
  • the number of SHE electrode lines and transistors controlling the SHE electrode line can be reduced, so as to increase the storage density of the memory.
  • the MRAM further includes: a source line, a word line, a bit line and a plurality of control lines, one end of the SHE electrode line is electrically connected to the bit line, and the other end of the SHE electrode line is connected to the transistor.
  • the first end is electrically connected
  • the second end of the transistor is electrically connected to the source line
  • the gate of the transistor is electrically connected to the word line
  • multiple reference layers in multiple MTJ structures are electrically connected to multiple control lines one-to-one.
  • the word line corresponding to the MTJ structure to be written is used to receive the gate bias voltage, so that the word line
  • the electrically connected transistor is turned on;
  • the control line electrically connected to the MTJ structure to be written is used to receive the first bias voltage, and under the action of the VCMA effect, the critical switching current density of the MTJ structure to be written is reduced;
  • One signal line of the source line and bit line electrically connected into the MTJ structure is used to receive the write voltage, and the other signal line is used to ground to generate the write current in the SHE electrode line, and the VCMA effect in the spin-orbit torque and Under the combined action, the magnetic moment of the free layer to be written into the MTJ structure is reversed, and information writing is completed.
  • the control line electrically connected to the remaining MTJ structures sharing the SHE electrode line is used to receive the voltage unequal to the first bias voltage
  • the second bias voltage under the action of the VCMA effect, increases the critical switching current density of the remaining MTJ structures, so that the free layer magnetic moments of the remaining MTJs remain unchanged. This enables selective writing.
  • the control line electrically connected to the MTJ to be read is used For receiving the read voltage; the source line and the bit line electrically connected to the MTJ to be read are both used for grounding, so that the MTJ to be read is in a forward conduction state of the read current from the reference layer to the free layer.
  • the control lines electrically connected to the remaining MTJ structures that share the SHE electrode line are all used for grounding. In this way, the reading process of the structure can read one specific MTJ on the electrode line of the SHE at a time.
  • the control lines of all MTJs on the common SHE electrode line can also be connected to the reading voltage, so as to realize reading multiple MTJs at one time.
  • the control line electrically connected to the MTJ to be read is used grounded; the source line and the bit line electrically connected to the MTJ to be read are both used to receive the read voltage, so that the MTJ to be read is in the forward conduction state of the read current from the free layer to the reference layer.
  • the control lines electrically connected to the remaining MTJ structures that share the SHE electrode line are all used to receive the read voltage, and then realize once One MTJ is read, and multiple MTJs are read at a time if the control lines of all MTJs on the common SHE electrode line are grounded.
  • the source line, the bit line and the control line all extend along a third direction parallel to the substrate; Both ends are electrically connected to the same source line; among multiple memory cells, multiple SHE electrode lines arranged along the third direction are all electrically connected to the same bit line; among multiple memory cells, the multiple SHE electrode lines arranged along the third direction
  • the reference layers of the distributed multiple MTJ structures are all electrically connected to the same control line.
  • the word line extends along a fourth direction parallel to the substrate, and the fourth direction is perpendicular to the third direction; among the plurality of memory cells, the plurality of transistors arranged along the fourth direction The gates are all electrically connected to the same word line.
  • the MRAM further includes a connection line through which a plurality of SHE electrode lines arranged in a direction perpendicular to the substrate are connected in parallel; the connection line is electrically connected to the transistor.
  • multiple SHE electrode lines arranged in a direction perpendicular to the substrate can share transistors, so that the number of transistors can be further reduced and the storage density can be increased.
  • the 3D stacking of memory cells is realized, and more memory cells can be integrated in the direction perpendicular to the substrate, so the number of memory cells per unit area is increased, and the storage area density is increased.
  • the MRAM further includes a controller, and the controller is configured to: output a voltage control signal for controlling the voltage on the source line; output a voltage control signal for controlling the voltage on the bit line; output a voltage control signal for controlling the voltage on the word line and outputting a voltage control signal for controlling the voltage on the control line.
  • the present application also provides a magnetic random access memory, which includes a substrate and a plurality of memory cells arrayed on the substrate, any memory cell includes: write information through the spin Hall effect The SHE electrode line, at least one magnetic tunnel junction MTJ and a transistor with three terminals; any MTJ includes a stacked reference layer (also called a pinning layer), a tunnel layer and a free layer, and the free layer is close to the SHE electrode relative to the reference layer line, and the free layer is electrically connected to the SHE electrode line, and the transistor is electrically connected to the SHE electrode line; in particular, the tunnel layer includes a stacked first tunnel layer and a second tunnel layer, and the first tunnel layer and the second tunnel layer are composed of Made of different materials.
  • the MTJ can be made to have a forward conduction state and a reverse cutoff state.
  • the current flows from the reference layer to the free layer, and the MTJ structure is in a conduction low resistance state.
  • the current flows from the free layer to the reference layer.
  • the MTJ structure is in a cut-off high-resistance state; for another example, when the current flows from the free layer to the reference layer, the MTJ structure is in a conduction low-resistance state; on the contrary, when the current flows from the reference layer to the free layer, the MTJ structure is in a cut-off high resistance state. resistance state.
  • the current crosstalk between different MTJs can be effectively reduced and leakage power consumption can be reduced when performing read and write operations. It is also possible to reduce or omit the use of selectors such as pass transistors or diodes, thereby increasing storage density and storage capacity.
  • selectors such as pass transistors or diodes
  • the magnitude of the voltage across the MTJ weakens the VCMA effect. Therefore, by introducing an MTJ structure with unidirectional conduction characteristics, the VCMA effect can be further enhanced, and the working voltage range of read and write operations can be improved.
  • the first tunnel layer and the second tunnel layer have different thicknesses along the stacking direction.
  • materials of the first tunnel layer and the second tunnel layer include at least one of metal oxide, ferroelectric material, or semiconductor material.
  • any memory cell has multiple MTJs, and the free layers of the multiple MTJs are electrically connected to the same SHE electrode line.
  • multiple SHE electrode lines arranged along a direction perpendicular to the substrate are electrically connected to the same transistor.
  • the MRAM further includes: a source line, a bit line, a word line, and a read line; one end of the SHE electrode line is electrically connected to the bit line, and the other end of the SHE electrode line is connected to the first end of the transistor.
  • the terminals are electrically connected, the second end of the transistor is electrically connected to the source line, the gate of the transistor is electrically connected to the word line, and the reference layer is electrically connected to the read line.
  • the source line, the bit line and the control line all extend along a third direction parallel to the substrate; among the plurality of memory cells, the second Terminals are electrically connected to the same source line; among multiple memory cells, multiple SHE electrode lines arranged along the third direction are electrically connected to the same bit line; among multiple memory cells, multiple SHE electrode lines arranged along the third direction
  • the reference plane of the MTJ is electrically connected to the same control line.
  • the word line extends along a fourth direction parallel to the substrate, and the fourth direction is perpendicular to the third direction; among the plurality of memory cells, the plurality of transistors arranged along the fourth direction The gate is electrically connected to the same word line.
  • the 3D stacking of memory cells is realized, and more memory cells can be integrated in the direction perpendicular to the substrate, so the number of memory cells per unit area is increased, and the storage surface density is increased.
  • the present application also provides a control method of a magnetic random access memory
  • the storage unit in the magnetic random access memory includes: a spin Hall effect SHE electrode line; at least one magnetic tunnel junction MTJ, any MTJ includes sequentially stacked A reference layer, a tunnel layer and a free layer, and the free layer is electrically connected to the SHE electrode line; a transistor is electrically connected to the SHE electrode line; a source line, a bit line, a word line and at least one read line, and one end of the SHE electrode line is connected to the bit line Electrically connected, the other end of the SHE electrode line is electrically connected to the first end of the transistor, the second end of the transistor is electrically connected to the source line, the gate of the transistor is electrically connected to the word line, and the reference layer is electrically connected to the read line; wherein, the MTJ It is in the forward conduction state when the current in the first direction is passed in, and it is in the reverse cut-off state when the current in the second direction is passed in.
  • the first direction and the second direction are mutually opposite directions; the control method includes: storing In the writing process of the MTJ to be written in the unit; outputting a gate bias voltage to the word line corresponding to the MTJ to be written, so as to conduct the transistor electrically connected to the word line; to be electrically connected to the MTJ to be written One signal line of the source line and the bit line outputs a write voltage, and the other signal line is grounded to generate a write current in the SHE electrode line, so that the free layer magnetic moment to be written into the MTJ is reversed.
  • any memory cell has one MTJ; during the writing process of the MTJ to be written in the memory cell; the read line electrically connected to the MTJ to be written is grounded.
  • the free layers of the multiple MTJs are electrically connected to the same SHE electrode line; during the writing process of the MTJ to be written in the memory cell; Outputting the first bias voltage to the read line electrically connected to the MTJ to be written, so as to reduce the critical switching current density of the MTJ to be written.
  • a second bias unequal to the first bias voltage is output to the control lines electrically connected to the remaining MTJs that share the SHE electrode line.
  • the voltage is set to increase the critical switching current density of the remaining MTJs so that the free layer magnetic moments of the remaining MTJs remain unchanged.
  • the conduction direction of the MTJ is from the reference layer to the direction of the free layer
  • the source line and the bit line electrically connected to the MTJ to be read are both grounded, so that the MTJ to be read is in a forward conduction state of the read current from the reference layer to the free layer.
  • the read line electrically connected to the MTJ to be read is grounded; Outputting a read voltage to both the source line and the bit line electrically connected to the MTJ to be read, so that the MTJ to be read is in a forward conduction state in which the read current flows from the free layer to the reference layer.
  • the present application further provides an electronic device, including a circuit board and the magnetic random access memory in any implementation manner of the first aspect or the second aspect above, and the circuit board is electrically connected to the magnetic random access memory.
  • the electronic device provided by the embodiment of the present application includes the magnetic random access memory of the above embodiment, so the electronic device provided by the embodiment of the present application and the magnetic random access memory of the above technical solution can solve the same technical problem and achieve the same expected effect.
  • Fig. 1 is the circuit diagram of a kind of existing MTJ and SHE electrode line
  • FIG. 2 is a circuit diagram of an electronic device provided in an embodiment of the present application.
  • FIG. 3 is a circuit diagram of a magnetic random access memory provided by an embodiment of the present application.
  • Figure 4a is a circuit diagram of a memory cell
  • Figure 4b is a circuit diagram of another memory cell
  • Figure 5a is a circuit diagram of a memory comprising the memory cell of Figure 4a;
  • Figure 5b is a circuit diagram of a memory comprising the memory cell of Figure 4b;
  • Fig. 6 is a schematic diagram of a memory comprising the memory cell of Fig. 4a when reading is performed;
  • Fig. 7 is a circuit diagram after removing the transistor connected to the MTJ in Fig. 5a;
  • FIG. 8 is a partial circuit diagram of a memory provided by the present application.
  • FIG. 9 is a partial circuit diagram of a memory provided by the present application.
  • FIG. 10 is a schematic structural diagram of an MTJ provided in the present application.
  • FIG. 11 is a schematic diagram of the memory provided in the present application when performing writing
  • FIG. 12 is a schematic diagram of the memory provided in the present application when performing writing
  • FIG. 13 is a schematic diagram of the memory provided in the present application when performing reading
  • FIG. 14 is a schematic diagram of the memory provided in the present application when performing reading
  • Fig. 15 is the circuit diagram of the storage device that the present application provides
  • Fig. 16 is the circuit diagram of the memory that the application provides
  • FIG. 17 is a schematic diagram of the memory provided in the present application when performing writing.
  • FIG. 18 is a schematic diagram of the memory provided in the present application when performing writing
  • FIG. 19 is a schematic diagram of the memory provided in the present application when performing reading
  • FIG. 20 is a schematic diagram of the memory provided in the present application when performing reading
  • FIG. 21 is a schematic diagram of the memory provided in the present application when performing reading
  • Figure 22 is a three-dimensional structural diagram of the memory provided by the present application.
  • Fig. 23 is a three-dimensional structure diagram of a memory slice of the memory provided by the present application.
  • FIG. 24 is a schematic diagram of a memory slice of the memory provided in the present application to illustrate the leakage suppression channel.
  • Spin polarized current the direction of spin during electron movement is random, half up and half down, it is a non-polarized current; the spin of moving electrons has a certain directionality, up and down Asymmetric, that is, spin-polarized current, when there are only up-polarized electrons or only down-polarized electrons, the polarizability of the polarized current is 100%.
  • SOT Spin-orbit torque
  • Tunneling magneto resistance (TMR) effect refers to the effect that in ferromagnetic-insulator-ferromagnetic thin film materials, the tunneling resistance varies with the relative direction of the ferromagnetic materials on both sides. It can also be said that the magnetic tunnel When the magnetization directions of the two ferromagnetic layers in the junction MTJ are arranged in parallel, the MTJ has a low-resistance state, and when they are anti-parallel, the MTJ has a high-resistance state.
  • Voltage-controlled magnetic anisotropy (VCMA) effect It means that when a voltage is applied across the MTJ, it will change the vertical anisotropy of the free layer in the MTJ, thereby reducing (or increasing) the magnetic properties of the free layer.
  • the critical switching current density of the moment, the magnitude of the VCMA effect is proportional to the voltage difference across the MTJ.
  • FIG. 2 is a kind of electronic equipment 200 that the embodiment of the present application provides, and this electronic equipment 200 can be terminal equipment, such as mobile phone, tablet computer, smart bracelet, also can be personal computer (personal computer, PC), server, workstation etc. .
  • the electronic device 200 may include a bus 205, and a system on chip (system on chip, SOC) 210 and a read-only memory (read-only memory, ROM) 220 connected to the bus 205.
  • the SOC 210 can be used to process data, such as processing application data, processing image data, and caching temporary data.
  • ROM 220 can be used to save non-volatile data, such as audio files, video files, etc.
  • ROM220 can be PROM (programmable read-only memory, programmable read-only memory), EPROM (erasable programmable read-only memory, erasable programmable read-only memory), flash memory (flash memory) and so on.
  • the electronic device 200 may further include a communication chip 230 and a power management chip 240 .
  • the communication chip 230 can be used to process the protocol stack, or to amplify and filter the analog radio frequency signal, or to realize the above functions at the same time.
  • the power management chip 240 can be used to supply power to other chips.
  • the SOC 210 may include an application processor (application processor, AP) 211 for processing application programs, an image processing unit (graphics processing unit, GPU) 212 for processing image data, and a cache data random access memory (random access memory, RAM) 213.
  • application processor application processor, AP
  • image processing unit graphics processing unit, GPU
  • cache data random access memory random access memory
  • the above-mentioned AP211, GPU212 and RAM213 can be integrated into one die, or respectively integrated into multiple dies, and packaged in a package structure, such as 2.5D (dimension), 3D package , or other advanced packaging technologies.
  • the above-mentioned AP211 and GPU212 are integrated in one die, RAM213 is integrated in another die, and these two dies are packaged in a package structure, so as to obtain a faster data transmission rate between dies and higher data transfer bandwidth.
  • FIG. 3 is a schematic structural diagram of a magnetic random access memory (magnetic random access memory, MRAM) 300 provided by an embodiment of the present application.
  • MRAM 300 may also be a RAM provided outside the SOC 210 .
  • the present application does not limit the location of the MRAM 300 in the device and the location relationship with the SOC 210 .
  • the MRAM 300 includes a memory array 310 , a decoder 320 , a driver 330 , a timing controller 340 , a buffer 350 and an input/output driver 360 .
  • the storage array 310 includes a plurality of storage units 400 arranged in an array, wherein each storage unit 400 can be used to store 1-bit or multi-bit data.
  • the storage array 310 also includes signal lines such as word lines (word line, WL), bit lines (bit line, BL), source lines (source line, SL) and control lines (control line, CL). Each memory cell 400 is electrically connected to the corresponding word line WL, bit line BL, source line SL and control line CL.
  • the core structure in each memory cell 400 is a magnetic tunnel junction MTJ, one or more of the above-mentioned word line WL, bit line BL, source line SL or control line CL is used to receive the control level output by the control circuit, select In the memory cell 400 to be read and written in the memory array, the magnetization directions of the two ferromagnetic layers in the magnetic tunnel junction MTJ are arranged in parallel or antiparallel, so as to write different logic information.
  • the word line WL, the bit line BL, the source line SL and the control line CL are collectively referred to as signal lines.
  • the decoder 320 is used to decode the received address to determine the storage unit 400 to be accessed.
  • the driver 330 is used to control the level of the signal line according to the decoding result generated by the decoder 320 , so as to realize the access to the specified storage unit 400 .
  • the buffer 350 is used for caching the read data, for example, first-in-first-out (FIFO) may be used for caching.
  • the timing controller 330 is used for controlling the timing of the register 350 and controlling the driver 330 to drive the signal lines in the memory array 310 .
  • the input/output driver 360 is used to drive transmission signals, such as driving received data signals and driving data signals to be sent, so that the data signals can be transmitted over long distances.
  • the memory array 310 , decoder 320 , driver 330 , timing controller 340 , buffer 350 and input/output driver 360 may be integrated into one chip, or may be integrated into multiple chips respectively.
  • spin-orbit torque MRAM spin-orbit torque
  • SOT spin-orbit torque
  • SHE spin hall effect
  • SOT-MRAM spin-orbit torque MRAM written by the spin hall effect
  • the writing path and the reading path are separated, so compared with the spin-transfer torque (STT)-MRAM, the magnetic tunnel junction MTJ is not easy to be broken down, and the device is durable. Sex is higher.
  • the magnetization orientation of the free layer in the MTJ is changed through the spin-orbit coupling effect, rather than in the STT-MRAM storage unit, electrons are spin-polarized when they pass through the reference layer of the MTJ, and the polarization When the electrons pass through the free layer, they interact with the magnetic moment of the free layer, thereby changing the magnetic moment state of the free layer.
  • the writing current does not flow through the tunnel junction region of the MTJ, which can protect the tunnel of the MTJ layer, reducing the risk of the tunnel layer being broken down, which in turn can enhance the stability of reading and writing data of the storage unit, and improve the durability of the storage unit.
  • Figure 4a and Figure 4b show two Different SOT-MRAM memory cell structures.
  • Fig. 4a is a 2T1R memory cell
  • Fig. 4b is a 1T1R1D memory cell, where T is a transistor, R is an MTJ, and D is a unidirectional conduction diode (diode).
  • one end of the SHE electrode line 04 is electrically connected to the bit line (bit line, BL), the other end of the SHE electrode line 04 is electrically connected to the first end of the transistor 051 having three terminals, and the second end of the transistor 051 It is electrically connected to the source line (source line, SL), the gate of the transistor 051 is electrically connected to the write word line (write word line, WWL), the free layer 03 of the MTJ14 is in contact with and electrically connected to the SHE electrode line 04, and the reference of the MTJ14 Layer 01 is electrically connected to a first terminal of a three-terminal transistor 052, a second terminal of transistor 052 is electrically connected to a source line SL, and a gate of transistor 052 is electrically connected to a read word line (RWL). Therefore, one memory cell shown in FIG. 4 a includes the SHE electrode line 04 , the MTJ 14 , the transistor 051 and the transistor 052 .
  • a memory cell shown in FIG. 4 b includes SHE electrode line 04 , MTJ 14 , transistor 05 and diode 06 .
  • Figure 4b can use one less transistor in a memory cell, which can effectively increase the density of memory cells, but it is difficult to find an electrical property (such as turn-on voltage, resistance value, etc.) that matches the MTJ
  • the diode 06 and thus the feasibility of using a diode as a selector is also relatively low.
  • the memory array 310 shown in FIG. 5a includes a plurality of 2T1R memory cells shown in FIG. 5a, and the memory array 310 shown in FIG. 5b includes a plurality of 1T1R1D memory cells shown in FIG. 5b.
  • multiple MTJs can be arranged side by side on one SHE electrode line, for example, in Figure 5a, a plurality of MTJ1400, MTJ1401, MTJ1402, MTJ140n, etc.
  • a plurality of MTJ1410, MTJ1411, MTJ1412, MTJ141n, etc. connected to it are arranged side by side, in addition, gates of transistors electrically connected to the SHE electrode line, and a plurality of gates electrically connected to the plurality of MTJs
  • the gates of the transistors are all electrically connected to the word line WL, for example, in FIG.
  • the gates of the transistor 051 electrically connected to the first SHE electrode line 041 and the gates of a plurality of transistors 052 are all electrically connected to the word line WL0, That is, the turn-on and turn-off of the transistor 051 and the plurality of transistors 052 is controlled through the word line WL0.
  • the two different memory arrays 310 shown in Fig. 5a and Fig. 5b are all based on the spin-orbit torque effect and the voltage-controlled magnetic anisotropy (voltage-controlled magnetic anisotropy, VCMA) effect to write information, the difference is that in Fig. In 5a, the transistor connected to the MTJ is used as the selector of the MTJ, and in Figure 5b, the diode connected to the MTJ is used as the selector of the MTJ, that is, by controlling the conduction of the transistor 052 or the diode 06 connected in series with the MTJ To select the MTJ to read and write.
  • the transistor connected to the MTJ is used as the selector of the MTJ
  • the diode connected to the MTJ is used as the selector of the MTJ, that is, by controlling the conduction of the transistor 052 or the diode 06 connected in series with the MTJ To select the MTJ to read and write.
  • FIG. 5a Now take the structure shown in FIG. 5a as an example to illustrate the principle of reading and writing of the memory, as follows.
  • a high potential "1" is applied to the control line CL connected to the transistors connected in series, and the upper and lower ends of these MTJs generate a positive voltage difference.
  • the VCMA effect increases the critical switching current density of MTJs such as MTJ1400, MTJ1402, and MTJ140n, and the current on the first SHE electrode line 041 cannot cause the free layer of these MTJs to flip, and thus no information is written.
  • a low potential "0” is applied (for example, a low potential “0” is applied to the word line WL1), and the transistors controlled by the word line WL1 are all in the off state. In this way, multiple storage devices controlled by the word line WL1 None of the cells can write information.
  • Figure 6 is a schematic diagram of the structure shown in Figure 5a when reading, and a high potential "1" is applied to the word line WL0 , then a series of transistors 052 and 051 controlled by the word line WL0 are all turned on, and Vread is applied to CL0, CL1, CL2, etc. Grounded to realize the reading of memory cells such as MTJ1400, MTJ1402...MTJ140n, etc.
  • other word lines WL apply low potential "0"
  • the transistor controlled by the word line WL with low potential "0” is turned off, and there is no power on the corresponding MTJ. read current through.
  • the two different storage structures shown in Figure 5a and Figure 5b also have an obvious feature that by connecting a transistor or a diode in series to the MTJ, the leakage channels (sneak paths) during read and write operations can be suppressed. , to reduce leakage power consumption when reading and writing information.
  • Figure 7 is a schematic diagram of the structure shown in Figure 5a by removing the transistor connected in series with the MTJ to form a leakage channel, or taking writing information to MTJ4101 as an example: apply a high potential "1" to the word line WL0, and the word line WL0 controls The transistor 051 is turned on, applying a high potential "1" to the source line SL, and applying a low potential "0" to the bit line BL, then a leftward current flows in the first SHE electrode line 041, and at the same time, it controls the connection with the MTJ1401 The low potential “0” is applied to the line CL1 , the high potential “1” is applied to the other control lines CL, and the low potential “0” is applied to the other word lines WL. Under the joint effect of VCMA effect and SOT effect, only the free layer of MTJ1401 is flipped to realize information writing.
  • each MTJ since each MTJ is connected in series with a transistor or a diode, the storage density and integration level will be reduced. If the transistor or diode connected in series with the MTJ is removed in order to increase the storage density, Leakage will occur; in order to suppress leakage, after introducing a transistor or diode in series with MTJ, because the transistor or diode in series with MTJ has internal resistance, it will have a voltage divider effect during read and write operations, which will reduce the MTJ. The voltage of the terminal weakens the VCMA effect, reduces the working voltage range of the read and write operations, and affects the accuracy of reading and writing.
  • FIG. 8 shows a structure of a memory array 310 formed by some memory cells in a memory of the present application.
  • the SHE electrode line 04 and the MTJ14 electrically connected to the SHE electrode line 04 are included, and the The SHE electrode line 04 is electrically connected to the transistor 05.
  • the MTJ14 here is a unidirectional conduction MTJ structure. It can be said that the MTJ is in a forward conduction state when the current in the first direction is passed through, and is in a reverse cut-off state when the current in the second direction is passed through. , the first direction and the second direction are mutually opposite directions. Here, the first direction and the second direction are both positive current directions.
  • the ratio I on /I off of the forward on-current and the reverse off-current of the MTJ structure 14 may be greater than 10, or, I on /I off is about 10.
  • the MTJ14 in this figure is a kind of MTJ structure that is conducted from the top end away from the SHE electrode line 04 to the bottom end close to the SHE electrode line 04 (wherein, in Figure 8, the direction of the triangle is forward conduction direction), or, as shown in FIG.
  • MTJ14 In the MTJ14 structure shown in Figure 8 and Figure 9, along the conduction direction of MTJ14, MTJ14 has a low resistance characteristic, and when the current flows in the opposite direction of the MTJ14 structure, MTJ14 has a high resistance characteristic, so in Figure 8, when MTJ14 When the top end is at high potential and the bottom end is at low potential, MTJ is in a conduction low resistance state. In FIG. 9 , when the bottom end of MTJ14 is at high potential and the top end is at low potential, MTJ14 is in a conduction low resistance state.
  • FIG. 10 shows a connection relationship diagram between a unidirectional conduction MTJ14 structure and the SHE electrode line 04.
  • the MTJ14 structure shown also includes a reference layer 01, a tunnel layer 02 and a free layer 03, and the tunnel layer 02 is formed between the reference layer 01 and the free layer 03, but the tunnel layer 02 in this structure includes at least two layers
  • the structure shows the tunnel layer 02 structure comprising a first tunnel layer 021 and a second tunnel layer 022, the first tunnel layer 021 and the second tunnel layer 022 are made of different insulating materials, For example, metal oxides such as AlO, ZnO, CoO, MgO, and MgAlO can be selected.
  • the current can pass through the reference layer 01, the tunnel layer 02 and the free layer 03 of the MTJ14 in sequence to realize the conduction and low resistance state of the MTJ14 from the top to the bottom.
  • the first tunnel layer 021 and the second tunnel layer 022 can also be made of different ferroelectric materials, or can be made of different semiconductor materials.
  • the MTJ14 has a unidirectional conduction characteristic.
  • the unidirectional conduction characteristic of the MTJ 14 can also be realized by changing the thickness of different tunnel layers.
  • the reference layer 01 can be made of SrRuO 3 material
  • the free layer 03 can be made of La 2/3 Sr 1/3 MnO 3 material
  • the tunnel layer 02 can be made of insulating material, semiconductor material or iron
  • the MTJ14 structure formed in this way also has unidirectional conductivity.
  • one end of the SHE electrode line 04 in the memory cell is electrically connected to the bit line BL, the other end is electrically connected to the first end of the transistor 05, and the second end of the transistor 05 is electrically connected to the source line SL is electrically connected, and the gate of the transistor 05 is electrically connected to the word line WL.
  • the reference layer 01 is electrically connected to a read line (read line, RL).
  • the timing controller 340 of FIG. 3 includes one or more sub-controllers for controlling these signal lines. There may be a one-to-one correspondence between these one or more sub-controllers and the above-mentioned signal lines, or a many-to-many relationship. For example, the timing controller 340 may control all signal lines through only one sub-controller. Alternatively, the timing controller 340 may also include four sub-controllers, wherein the word line sub-controller is used to control the voltage on all types of word lines, the bit line sub-controller is used to control the voltage on all types of bit lines, and the source line sub-controller is used to control the voltage on all types of bit lines. The controller is used to control the voltage on all types of source lines, and the read line controller is used to control the voltage on all types of read lines.
  • the transistor electrically connected to the SHE electrode line 04 may select NMOS (N-channel metal oxide semiconductor, N-channel metal oxide semiconductor) transistor, or may select PMOS (P-channel metal oxide semiconductor, P-channel metal-oxide-semiconductor) transistor, in this application, one of the drain or source of the MOS transistor can be referred to as the first terminal, and the corresponding other terminal can be referred to as the second terminal. .
  • the drain and source can be determined according to the flow direction of the current.
  • a plurality of memory cells are arranged in an array along the perpendicular X direction and Y direction, where the X direction and Y direction are directions parallel to the substrate, and these multiple memory cells are formed on the substrate to form the storage array 310.
  • the memory array 310 multiple memory cells arranged along the X direction share one source line SL and one BL, and multiple memory cells arranged along the Y direction share one read line RL and one word line WL. In this way, the wiring of the entire memory can be simplified, and the storage density can be improved.
  • the SHE electrode line 04 in the memory cell A1 has a rightward current flowing through it, and under the action of the spin polarization current in the SHE electrode line 04, the free layer in the MTJ14 of the memory cell A1 is flipped to realize information writing. enter. No write current flows on the SHE electrode lines of other non-written memory cells, and information cannot be written.
  • the opposite information can be written in the MTJ14 of the memory cell A1, as shown in Figure 12, if a high potential "1" is applied to WL0, then WL0 controls A series of transistors are all turned on, a write voltage is applied to SL0, and BL0 is grounded. Furthermore, a leftward current flows on the SHE electrode line 04 of the memory cell A1 to write opposite information.
  • the read line RL0 electrically connected to the reference layer of the MTJ14 of the memory cell A1 is connected to Vread
  • the bit line BL0 is grounded
  • other bit lines BL such as the bit line BL1
  • other source lines SL such as source line SL1
  • all word lines WL are connected to low potential "0”
  • all transistors of memory cells are turned off, then only MTJ14 of memory cell A1 and memory cell A4
  • There is a read voltage difference across the MTJ14 of the memory cell A1 since the MTJ14 of the memory cell A1 is in the conduction state of the low resistance state, thus the read operation of the memory cell A1 can be realized, however, the MTJ14 of the memory cell A4 is in the opposite direction of the high resistance state In the cut-off state, the leakage current of the memory cell A4 is small, and the leakage channel is suppressed.
  • FIG. 14 is a structural diagram of another memory storage array. The difference from FIG. 13 is that the forward conduction direction of the MTJ14 in FIG. 14 is opposite to the forward conduction direction of the MTJ14 in FIG. 13 .
  • the read line RL0 electrically connected to the reference layer of the MTJ14 of the memory cell A1 is grounded , other read lines RL (such as read line RL1) are connected to Vread, bit line BL0 is connected to Vread, other bit lines BL (such as bit line BL 1) are connected to ground, all word lines WL are connected to low potential "0", and then all memory cells
  • the transistors of the source lines are all turned off, because all the word lines WL are connected to the low potential "0", and the transistors electrically connected to the word lines WL are in the off state.
  • all the source lines SL can be grounded or connected to other voltages.
  • the MTJ14 of the memory cell A1 and the MTJ14 of the memory cell A4 have a read voltage difference. Since the MTJ14 of the memory cell A1 is in a low-resistance conduction state, the read operation of the memory cell A1 can be realized. However, The MTJ14 of the memory cell A4 is in the reverse cut-off state of the high resistance state, the leakage current of the memory cell A4 is small, and the leakage channel is suppressed.
  • each memory cell only has a transistor 05 electrically connected to the SHE electrode line 04, and a selector (such as a transistor or a diode) electrically connected to the MTJ is omitted.
  • a selector such as a transistor or a diode
  • Figure 15 provides another A memory that includes a unidirectional conduction MTJ14.
  • multiple MTJ14 structures with unidirectional conductivity are arranged side by side on each SHE electrode line 04, that is, multiple MTJ14 with unidirectional conductivity are electrically connected to the same SHE electrode line 04, in this case, Multiple memory cells can share one SHE electrode line 04 and transistor 05, thereby reducing the number of transistors 05 and further increasing storage density.
  • FIG. 15 only illustrates four MTJs 14 as an example.
  • the unidirectional conduction direction of the MTJ14 can be from the top end to the bottom end of the MTJ14 as shown in FIG. 15 , of course, it can also be an MTJ14 structure in which the conduction direction is from the bottom end to the top end.
  • the memory further includes a transistor 05 , a word line WL, a source line SL, a bit line BL and a control line CL.
  • One end of the SHE electrode line 04 is electrically connected to the bit line BL
  • the other end of the SHE electrode line 04 is electrically connected to the first end of the transistor 05
  • the second end of the transistor 05 is electrically connected to the source line SL
  • the MTJ14 The free layers of multiple MTJ14 are electrically connected to the MTJ14 contacts
  • the reference layer of each MTJ14 is electrically connected to the corresponding control line CL
  • the gate of the transistor 05 is electrically connected to the word line WL.
  • the conduction of the transistor can be controlled by the word line WL, and the potential applied by the bit line BL and the source line SL can be used to pass the write current to the SHE electrode line 04, and at the same time, the VCMA effect can be generated by the voltage applied on the control line CL to selectively write to specific MTJs.
  • one SHE electrode line 04 is electrically connected to one transistor 05 .
  • one SHE electrode line 04 is electrically connected to at least two transistors 05 .
  • one end of the SHE electrode line 04 is electrically connected to the first end of the transistor 051
  • the other end of the SHE electrode line 04 is electrically connected to the first end of the transistor 052
  • the second end of the transistor 051 is electrically connected to the source line SL
  • the second end of the transistor 052 is electrically connected to the bit line BL, and the gates of the transistor 051 and the transistor 052 are both electrically connected to the word line WL.
  • a plurality of memory cells are arranged in an array along the intersecting X and Y directions to form a memory array 310 .
  • a plurality of memory cells arranged along the X direction share one source line SL and a common bit line BL, and a plurality of memory cells arranged along the Y direction share one word line WL.
  • Multiple MTJs 14 share one control line CL. In this way, the wiring of the entire memory can be simplified, and the storage density can be improved.
  • information can be read from the stored data of one MTJ at a time, or the stored data of multiple MTJs that share one SHE electrode line at a time.
  • FIG. 22 shows a three-dimensional structure diagram of a memory array 310 containing unidirectional conduction MTJs.
  • multiple MTJs 14 and multiple SHE electrode lines 04 are included in the memory array 310. These multiple MTJs 14 and multiple SHE electrode lines 04 are along the The mutually perpendicular X direction, Y direction, and Z direction are arranged in an array to form a multi-layer 3D stacked structure.
  • the X direction and Y direction can be parallel to the substrate, and the Z direction is perpendicular to the substrate. direction.
  • Fig. 23 is a partial structural diagram of Fig. 22 in the Y-Z plane.
  • a plurality of SHE electrode lines are arranged side by side.
  • Fig. 23 shows the SHE electrode lines 041 and SHE electrodes arranged side by side Line 042 and SHE electrode line 043, these multiple SHE electrode lines arranged side by side in the Z direction are connected in parallel through connecting lines, and multiple SHE electrode lines connected in parallel share a transistor.
  • FIG. 23 shows the SHE electrode lines 041 and SHE electrodes arranged side by side Line 042 and SHE electrode line 043, these multiple SHE electrode lines arranged side by side in the Z direction are connected in parallel through connecting lines, and multiple SHE electrode lines connected in parallel share a transistor.
  • SHE electrode lines 041, The SHE electrode line 042 and the SHE electrode line 043 are connected in parallel through the first connection line 071 and the second connection line 072, the first connection line 071 is electrically connected to the first end of the transistor 051, and the second connection line 072 is connected to the first end of the transistor 052. Terminals are electrically connected to form a memory chip 09, so that when both the transistor 051 and the transistor 052 are turned on, read and write currents can be applied in parallel to all SOT electrode lines in the memory chip 09. It should be noted that only one transistor may be included here.
  • the present application can greatly reduce the number of transistors, further increase the storage density and storage capacity.
  • the second end of the transistor 051 is connected to the source line SL
  • the second end of the transistor 052 is connected to the bit line BL
  • the source line SL and the bit line BL are along the X line perpendicular to the Y-Z plane. direction extension.
  • multiple MTJs 14 can be connected to each SHE electrode line, for example, three MTJs 14 are arranged side by side on the SHE electrode line 041, the SHE electrode line 042 and the SHE electrode line 043 in FIG.
  • each MTJ 14 is correspondingly connected to a control line CL, and these multiple control lines CL also extend along the X direction perpendicular to the Y-Z plane.
  • Arranging a memory chip 09 structure shown in FIG. 23 into multiples along the X direction will form the structure in FIG. 22 , and the structure formed by a plurality of memory chip structures arranged along the X direction can be called a memory block (block ), for example, in FIG. 22, three memory slices are arranged along the X direction to form a memory block (block) structure.
  • a plurality of transistors 051 may share a source line SL, and a plurality of transistors 052 may share a bit line BL. Also, a plurality of MTJs 14 arranged along the X direction may share the control line CL.
  • the memory blocks shown in FIG. 22 can be arranged along the Y direction to form a memory structure with a larger capacity.
  • a transistor 051 and a transistor 052 may be formed on the substrate first, and then a multilayer stacked MTJ 14 is formed above the transistor 051 and the transistor 052 .
  • a gate bias voltage is applied to the WL connected to the memory chip where the MTJ14 to be written is located, then the transistor 051 and the transistor 052 controlled by the WL are in a conduction state, and, in When a write voltage is applied between the source line SL and the bit line BL of the memory chip where the MTJ14 is to be written, only the SHE electrode line of the memory chip where the MTJ14 is to be written has a write current flowing, that is, the only selected location where the MTJ14 is to be written is memory slice.
  • the information in all MTJ14 in the selected memory chip can be read at one time, that is, the gate bias voltage is applied to the WL connected to the memory chip to be read, and the transistor controlled by WL 051 and transistor 052 are on. Both the source line SL and the bit line BL of the memory slice to be read are grounded, and the source line SL and bit line BL of other non-read memory slices are both connected to Vread. At the same time, if all the control lines CL in the memory are connected to Vread, only the MTJ14 of the memory chip to be read will have a read current flow, so as to realize the information of all MTJ14 in the selected memory chip to be read once.
  • the memory also includes a plurality of amplifiers 08 (sense amplifiers, SA) connected to all the control lines CL in the MRAM in one-to-one correspondence, and each amplifier 08 in the plurality of amplifiers 08 is used to read the correspondingly connected The feedback information received by the control line CL.
  • SA sense amplifiers

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Abstract

本申请实施例提供一种磁性随机存储器及其控制方法，和包含有该磁性随机存储器的电子设备，涉及半导体技术领域，该磁性随机存储器包括衬底和呈阵列布设在衬底上的多个存储单元，任一个存储单元包括：SHE电极线、MTJ和具有三端子的晶体管；该MTJ包括堆叠的参考层、隧道层和自由层，自由层相对参考层靠近SHE电极线，并自由层与SHE电极线电连接，晶体管与SHE电极线电连接，特别的是，这里的MTJ具有单向导通特性。通过引入具有单向导通的MTJ不仅可以抑制漏电通道，还可以提高存储密度，增强VCMA效应，提高读写操作的可工作电压范围。

Description

磁性随机存储器及其控制方法、电子设备 技术领域
本申请涉及半导体技术领域，尤其涉及一种磁性随机存储器及其控制方法、包含有该磁性随机存储器的电子设备。
背景技术
在存储器中，基于磁性隧道结(magnetic tunnel junction，MTJ)为存储单元的磁性随机存储器(magnetic random access memory，MRAM)，由于同时具有很多优异的特性，例如：存储数据的非易失性，读写速度快，无限次的擦写寿命，较低的读写功耗等，越来越广泛的被应用。
图1示出了自旋轨道力矩(spin-orbit torque，SOT)磁性随机存储器中存储单元MTJ的结构，MTJ14主要包括参考层(pinned layer)01(也可以叫钉扎层)、隧道层(tunnel layer)02和自由层(free layer)03。其中，参考层01和自由层03均是铁磁材料，隧道层02是绝缘材料、半导体材料或铁电材料等，并且，自由层03靠近自旋霍尔效应(spin hall effect，SHE)电极线04，并与SHE电极线04电连接。
参考层01的磁化方向在信息写入过程中不改变，自由层03的磁化方向可以通过磁场或电流改变，以使自由层03的磁化方向与参考层01的磁化方向成平行或反平行排列，即写入信息。
当自由层03的磁化方向与参考层01的磁化方向平行时，MTJ具有低电阻特性，当两者反平行时，MTJ具有高电阻特性，即MTJ展现出隧穿磁电阻(tunneling magneto resistance，TMR)效应。MTJ的高低电阻特性代表了两种不同的逻辑信息(比如“0”或“1”)。
图1示出的存储单元是通过自旋霍尔效应(spin hall effect，SHE)写入信息的。SHE电极线04一般采用重金属或其他具有较大自旋霍尔角的材料制成，该存储单元MTJ14的写入原理为：给SHE电极线04中通入电流，则在SHE电极线04中产生自旋极化电子，该自旋极化电子扩散到临近的自由层03中，与自由层03中的磁矩发生相互作用，从而改变自由层03的磁化方向，自由层03的磁化方向与SHE电极线04中的电流方向有关，当改变SHE电极线04中电流的流向时，可以使自由层03的磁化方向朝相反方向翻转，从而在MTJ14中写入不同的逻辑信息。
在包含有图1所示存储单元的磁性随机存储器中，提高存储密度，减少漏电功耗，是目前本领域技术人员需要解决的技术问题。
发明内容
本申请提供一种磁性随机存储器及其控制方法、包含有该磁性随机存储器的电子设备，主要目的是将具有单向导通性的MTJ引入MRAM中，这样可以减少信息读写的漏电功耗，还可以提高存储密度，提高存储容量。
为达到上述目的，本申请的实施例采用如下技术方案：
第一方面，本申请提供了一种磁性随机存储器，该磁性随机存储器包括衬底和阵列布设在衬底上的多个存储单元，任一个存储单元包括：通过自旋霍尔效应写入信息的SHE电极线、至少一个磁性隧道结MTJ和具有三端子的晶体管；任一MTJ包括堆叠的参考层(也可以被叫做钉扎层)、隧道层和自由层，自由层相对参考层靠近SHE电极线，并且自由层与SHE电极线电连接，晶体管与SHE电极线电连接；特别的是，这里的MTJ具有单向导通性，即MTJ在通入第一方向的电流时处于正向导通状态，并在通入第二方向的电流时处于反向截止状态，第一方向和第二方向互为相反的方向，也可以这样讲，从MTJ的一端通电流，MTJ具有高电阻态，反向通电流，MTJ具有低电阻态。
可以这样理解本申请的磁性随机存储器中的MTJ，该MTJ是一种具有单向导通特性的MTJ结构，比如，电流由参考层流向自由层，该MTJ结构呈导通的低电阻态，相反的，电流由自由层流向参考层，该MTJ结构呈截止的高电阻态；再比如，电流由自由层至参考层，该MTJ结构呈导通的低电阻态，相反的，电流由参考层至自由层，该MTJ结构呈截止的高电阻态。所以，通过采用这种结构的MTJ，在执行读写操作时可以有效减小不同MTJ之间的电流串扰，减小漏电功耗。
由于本申请提供的磁性随机存储器中采用了具有单向导通特性的MTJ结构，进而，可以减少或者省略选通晶体管或二极管等选择器(selector)的使用，从而可以提升存储密度，提升存储容量。
本申请的磁性随机存储器采用的是电压调控磁各向异性VCMA效应和自旋轨道力矩SOT效应相结合的写操作原理。VCMA效应是指在MTJ的两端施加电压时，会改变MTJ自由层的垂直各向异性，从而减小(或增加)自由层磁矩的临界翻转电流密度，同时在SHE电极线上通一定写电流，可以使得自由层磁矩翻转(或者不变)，VCMA效应的大小与加在MTJ两端的电压差成正比。本申请由于采用了具有单向导通性的MTJ，不需要在MTJ上串联一个选择器(selector)来防止阵列漏电，这样就可以避免选择器(selector)因为具有内阻而分压，降低实际落在MTJ两端的电压大小，削弱VCMA效应的现象。因此，通过引入具有单向导通特性的MTJ结构，可以进一步的增强VCMA效应，提高读写操作的可工作电压范围。
在第一方面可能的实现方式中，MTJ结构的正向导通电流I on和反向截止电流I off的比值大于或者等于10。
在第一方面可能的实现方式中，MTJ的隧道层包括至少两层不同材料制得的隧道层。例如堆叠的第一隧道层和第二隧道层，第一隧道层和第二隧道层由不同的材料制得，第一隧道层和第二隧道层的材料可以为AlO、ZnO、CoO、MgO等金属氧化物中的一种，或者可以选择铁电材料或者半导体材料中的至少一种，当电流通过该结构的MTJ时，发生两步隧穿，隧穿的几率与电子运动的方向有关，因此MTJ具有某个方向低电阻态，反方向高电阻态。
也就是，通过调整隧道层的结构，采用不同的材料制得多层隧道层，实现具有单向导通的MTJ结构。
在第一方面可能的实现方式中，进一步的，第一隧道层和所述第二隧道层的沿堆 叠方向的厚度不同。
也就是说，通过调节不同隧道层的厚度和材料，可以调节MTJ结构的导通方向,实现具有单向导通的MTJ结构。
在第一方面可能的实现方式中，参考层包括SrRuO 3材料，自由层包括La 2/3Sr 1/3MnO 3材料。
也就是通过改变参考层和自由层的材料，实现具有单向导通特性的MTJ结构。
在第一方面可能的实现方式中，参考层和自由层的磁性材料中掺杂有杂质。通过掺杂杂质以改变这两层结构的费米能处的能带结构，从而调节MTJ结构的电学特性，以实现单向导通特性。
在第一方面可能的实现方式中，任一所述存储单元中具有一个MTJ，磁性随机存储器还包括：源线、位线、字线和读线；SHE电极线的一端与位线电连接，SHE电极线的另一端与晶体管的第一端电连接，晶体管的第二端与源线电连接，晶体管的栅极与字线电连接，参考层与读线电连接。
在第一方面可能的实现方式中，MTJ的写入过程中；与MTJ相对应的字线用于接收栅极偏置电压，以使与字线电连接的晶体管导通；与MTJ电连接的读线用于接地；与MTJ电连接的源线和位线中的一个信号线用于接收写入电压，另一个信号线用于接地，以在SHE电极线中产生写电流，在自旋轨道力矩效应的作用下，MTJ的自由层磁矩发生翻转，完成信息写入。比如，源线接收写入电压，位线接地时，写入逻辑信息“0”，相反的，当位线接收写入电压，源线接地时，写入逻辑信息“1”。
在第一方面可能的实现方式中，MTJ的正向导通方向为由参考层至自由层方向时，MTJ的读取过程中；与MTJ电连接的读线用于接收读取电压；与MTJ电连接的源线和位线均用于接地，以使MTJ处于读电流从参考层到自由层的正向导通状态。
在第一方面可能的实现方式中，磁性随机存储器中与其余MTJ结构电连接的读线用于接地；与其余MTJ结构电连接的位线用于接收读取电压，源线可以用于接地，以使其余MTJ中的读电流方向是从自由层到参考层的反向截止状态。这样一来，该结构的漏电流小，降低读取时的功耗。并且，磁性随机存储器中所有字线接地，使得字线控制的晶体管全关断。
在第一方面可能的实现方式中，MTJ的正向导通方向为由自由层至参考层方向时，MTJ的读取过程中；与MTJ电连接的读线用于接地；与MTJ电连接的位线用于接收读取电压，源线用于接地，以使MTJ处于读电流从自由层到参考层的正向导通状态。
在第一方面可能的实现方式中，磁性随机存储器中与其余MTJ结构电连接的读线用于接收读取电压；与其余MTJ电连接的源线和位线均用于接地，以使其余MTJ中的读电流方向是从自由层到参考层的反向截止状态。同样的，该结构的漏电流小，降低读取时的功耗。并且，磁性随机存储器中所有字线接地，使得字线控制的晶体管全关断。
在第一方面可能的实现方式中，MTJ具有多个，多个MTJ可以并排布设，且多个MTJ的自由层与同一个SHE电极线电连接。
通过使多个MTJ结构共用一个SHE电极线，这样可以减少SHE电极线和控制SHE电极线的晶体管的数量，以提升该存储器的存储密度。
在第一方面可能的实现方式中，磁性随机存储器还包括：源线、字线、位线和多个控制线，SHE电极线的一端与位线电连接，SHE电极线的另一端与晶体管的第一端电连接，晶体管的第二端与源线电连接，晶体管的栅极与字线电连接，多个MTJ结构中的多个参考层与多个控制线一对一电连接。
在第一方面可能的实现方式中，对存储单元中待写入MTJ结构的写入过程中；与待写入MTJ结构相对应的字线用于接收栅极偏置电压，以使与字线电连接的晶体管导通；与待写入MTJ结构电连接的控制线用于接收第一偏置电压，在VCMA效应作用下，以使待写入MTJ结构的临界翻转电流密度降低；与待写入MTJ结构电连接的源线和位线中的一个信号线用于接收写入电压，另一个信号线用于接地，以在SHE电极线中产生写电流，在自旋轨道力矩和的VCMA效应共同作用下，待写入MTJ结构的自由层磁矩发生翻转，完成信息写入。
也就是，在进行写入时，依靠VCMA效应和SOT效应进行写操作，这种写方式可以显著降低数据写功耗。
在第一方面可能的实现方式中，对存储单元中待写入MTJ结构的写入过程中，共用SHE电极线的其余MTJ结构电连接的控制线用于接收与第一偏置电压不相等的第二偏置电压，在VCMA效应作用下，以使其余MTJ结构的临界翻转电流密度升高，以使其余MTJ的自由层磁矩保持不变。这样就实现了选择性写入。
在第一方面可能的实现方式中，MTJ的正向导通方向为由参考层至自由层方向时，存储单元中待读取MTJ的读取过程中；与待读取MTJ电连接的控制线用于接收读取电压；与待读取MTJ电连接的源线和位线均用于接地，以使待读取MTJ处于读电流从参考层到自由层的正向导通状态。
在第一方面可能的实现方式中，对存储单元中待读取MTJ结构的读取过程中，共用SHE电极线的其余MTJ结构电连接的控制线均用于接地。这样该结构的读取过程，可以一次读取SHE电极线上的一个特定MTJ。同时，也可以将共用SHE电极线上的所有MTJ的控制线都接读取电压，实现一次读取多个MTJ。
在第一方面可能的实现方式中，MTJ的正向导通方向为由自由层至参考层方向时，存储单元中待读取MTJ的读取过程中；与待读取MTJ电连接的控制线用于接地；与待读取MTJ电连接的源线和位线均用于接收读取电压，以使待读取MTJ处于读电流从自由层到参考层的正向导通状态。
在第一方面可能的实现方式中，对磁性随机存储器中待读取MTJ结构的读取过程中，共用SHE电极线的其余MTJ结构电连接的控制线均用于接收读取电压，则实现一次读取一个MTJ，若共用SHE电极线上的所有MTJ的控制线都接地，则一次读取多个MTJ。
在第一方面可能的实现方式中，源线、位线和控制线均沿与衬底相平行的第三方向延伸；在多个存储单元中，沿第三方向排布的多个晶体管的第二端均与同一个源线电连接；在多个存储单元中，沿第三方向排布的多个SHE电极线均与同一个位线电连接；多个存储单元中，沿第三方向排布的多个MTJ结构的参考层均与同一个控制线电连接。
在第一方面可能的实现方式中，字线沿与衬底相平行的第四方向延伸，第四方向 与第三方向垂直；多个存储单元中，沿第四方向排布的多个晶体管的栅极均与同一个字线电连接。
在第一方面可能的实现方式中，多个存储单元中，沿与衬底相垂直方向排布的多个SHE电极线与同一个晶体管电连接。比如，磁性随机存储器还包括连接线，沿与衬底相垂直方向排布的多个SHE电极线通过连接线相并联；连接线与晶体管电连接。
也就是说，沿与衬底相垂直方向排布的多个SHE电极线可以共用晶体管，这样的话，就可以进一步减少晶体管的数量，提升存储密度。
另外，基于上述描述，实现了存储单元的3D堆叠，进而，在与衬底相垂直的方向上可以集成更多的存储单元，所以提高了单位面积的存储单元个数，增加了存储面密度。
在第一方面可能的实现方式中，磁性随机存储器还包括控制器，控制器用于：输出控制源线上电压的电压控制信号；输出控制位线上电压的电压控制信号；输出控制字线上电压的电压控制信号；以及，输出控制控制线上电压的电压控制信号。
第二方面，本申请还提供了一种磁性随机存储器，该磁性随机存储器包括衬底和阵列布设在衬底上的多个存储单元，任一个存储单元包括：通过自旋霍尔效应写入信息的SHE电极线、至少一个磁性隧道结MTJ和具有三端子的晶体管；任一MTJ包括堆叠的参考层(也可以被叫做钉扎层)、隧道层和自由层，自由层相对参考层靠近SHE电极线，并且自由层与SHE电极线电连接，晶体管与SHE电极线电连接；特别的是，隧道层包括堆叠的第一隧道层和第二隧道层，且第一隧道层和第二隧道层由不同的材料制得。
这样的话，可以使得该MTJ具有正向导通状态和反向截止状态，比如，电流由参考层流向自由层，该MTJ结构呈导通的低电阻态，相反的，电流由自由层流向参考层，该MTJ结构呈截止的高电阻态；再比如，电流由自由层至参考层，该MTJ结构呈导通的低电阻态，相反的，电流由参考层至自由层，该MTJ结构呈截止的高电阻态。所以，通过采用这种结构的MTJ，在执行读写操作时可以有效减小不同MTJ之间的电流串扰，减小漏电功耗。还可以减少或者省略选通晶体管或二极管等选择器(selector)的使用，从而可以提升存储密度，提升存储容量。另外，由于采用了具有单向导通性的MTJ，不需要在MTJ上串联一个选择器(selector)来防止阵列漏电，这样就可以避免选择器(selector)因为具有内阻而分压，降低实际落在MTJ两端的电压大小，削弱VCMA效应的现象。因此，通过引入具有单向导通特性的MTJ结构，可以进一步的增强VCMA效应，提高读写操作的可工作电压范围。
在第二方面可能的实现方式中，第一隧道层和第二隧道层沿堆叠方向的厚度不同。
在第二方面可能的实现方式中，第一隧道层和第二隧道层的材料包括金属氧化物、铁电材料或者半导体材料中的至少一种。
在第二方面可能的实现方式中，任一存储单元中具有多个MTJ，且多个MTJ的自由层与同一个SHE电极线电连接。
在第二方面可能的实现方式中，多个存储单元中，沿与衬底相垂直方向排布的多个SHE电极线与同一个晶体管电连接。
在第二方面可能的实现方式中，磁性随机存储器还包括：源线、位线、字线和读线；SHE电极线的一端与位线电连接，SHE电极线的另一端与晶体管的第一端电连接，晶体管的第二端与源线电连接，晶体管的栅极与字线电连接，参考层与读线电连接。
在第二方面可能的实现方式中，源线、位线和控制线均沿与衬底相平行的第三方向延伸；多个存储单元中，沿第三方向排布的多个晶体管的第二端与同一个源线电连接；多个存储单元中，沿第三方向排布的多个SHE电极线与同一个位线电连接；多个存储单元中，沿第三方向排布的多个MTJ的参考层与同一个控制线电连接。
在第二方面可能的实现方式中，字线沿与衬底相平行的第四方向延伸，第四方向与第三方向垂直；多个存储单元中，沿第四方向排布的多个晶体管的栅极与同一个字线电连接。
基于上述描述，实现了存储单元的3D堆叠，进而，在与衬底相垂直的方向上可以集成更多的存储单元，所以提高了单位面积的存储单元个数，增加了存储面密度。
第三方面，本申请还提供了一种磁性随机存储器的控制方法，磁性随机存储器中的存储单元包括：自旋霍尔效应SHE电极线；至少一个磁性隧道结MTJ，任一MTJ包括依次堆叠的参考层、隧道层和自由层，且自由层与SHE电极线电连接；晶体管，与SHE电极线电连接；源线、位线、字线和至少一个读线，SHE电极线的一端与位线电连接，SHE电极线的另一端与晶体管的第一端电连接，晶体管的第二端与源线电连接，晶体管的栅极与字线电连接，参考层与读线电连接；其中，MTJ在通入第一方向的电流时处于正向导通状态，并在通入第二方向的电流时处于反向截止状态，第一方向和第二方向互为相反的方向；控制方法包括：对存储单元中待写入MTJ的写入过程中；向与待写入MTJ相对应的字线输出栅极偏置电压，以使与字线电连接的晶体管导通；向与待写入MTJ电连接的源线和位线中的一个信号线输出写入电压，另一个信号线接地，以在SHE电极线中产生写电流，以使待写入MTJ的自由层磁矩发生翻转。
在第三方面可能的实现方式中，任一存储单元中具有一个MTJ；对存储单元中待写入MTJ的写入过程中；与待写入MTJ电连接的读线接地。
在第三方面可能的实现方式中，任一存储单元中具有多个MTJ，且多个MTJ的自由层与同一个SHE电极线电连接；对存储单元中待写入MTJ的写入过程中；向与待写入MTJ电连接的读线输出第一偏置电压，以使待写入MTJ的临界翻转电流密度降低。
在第三方面可能的实现方式中，对存储单元中待写入MTJ的写入过程中，向共用SHE电极线的其余MTJ电连接的控制线输出与第一偏置电压不相等的第二偏置电压，使其余MTJ的临界翻转电流密度升高，以使其余MTJ的自由层磁矩保持不变。
在第三方面可能的实现方式中，MTJ的导通方向为由参考层至自由层方向时，存储单元中待读取MTJ的读取过程中；向与待读取MTJ电连接的读线输出读取电压；与待读取MTJ电连接的源线和位线均接地，以使待读取MTJ处于读电流从参考层到自由层的正向导通状态。
在第三方面可能的实现方式中，MTJ的导通方向为由自由层至参考层方向时，存储单元中待读取MTJ的读取过程中；与待读取MTJ电连接的读线接地；向与待读取 MTJ电连接的源线和位线均输出读取电压，以使待读取MTJ处于读电流从自由层到参考层的正向导通状态。
第四方面，本申请还提供了一种电子设备，包括电路板和上述第一方面或者第二方面任一实现方式中的磁性随机存储器，电路板与磁性随机存储器电连接。
本申请实施例提供的电子设备包括上述实施例的磁性随机存储器，因此本申请实施例提供的电子设备与上述技术方案的磁性随机存储器能够解决相同的技术问题，并达到相同的预期效果。
附图说明
图1为现有的一种MTJ与SHE电极线的电路图；
图2为本申请实施例提供的一种电子设备中的电路图；
图3为本申请实施例提供的一种磁性随机存储器的电路图；
图4a为一种存储单元的电路图；
图4b为另一种存储单元的电路图；
图5a为包含图4a存储单元的存储器的电路图；
图5b为包含图4b存储单元的存储器的电路图；
图6为包含图4a存储单元的存储器在执行读取时的原理图；
图7为图5a中去掉与MTJ连接的晶体管后的电路图；
图8为本申请给出的一种存储器的部分电路图；
图9为本申请给出的一种存储器的部分电路图；
图10为本申请给出的一种MTJ的结构示意图；
图11为本申请给出的存储器在执行写入时的原理图；
图12为本申请给出的存储器在执行写入时的原理图；
图13为本申请给出的存储器在执行读取时的原理图；
图14为本申请给出的存储器在执行读取时的原理图；
图15为本申请给出的存储器的电路图；
图16为本申请给出的存储器的电路图；
图17为本申请给出的存储器在执行写入时的原理图；
图18为本申请给出的存储器在执行写入时的原理图；
图19为本申请给出的存储器在执行读取时的原理图；
图20为本申请给出的存储器在执行读取时的原理图；
图21为本申请给出的存储器在执行读取时的原理图；
图22为本申请给出的存储器的三维结构图；
图23为本申请给出的存储器的一个存储片的三维结构图；
图24为本申请给出的存储器的一个存储片的用于说明抑制漏电通道的原理图。
附图标记：
01-参考层；02-隧道层；021-第一隧道层；022-第二隧道层；03-自由层；04-SHE电极线；041-第一SHE电极线；042-第二SHE电极线；043-第三SHE电极线；05、 051、052-晶体管；06-二极管；071-第一连接线；072-第二连接线；08-放大器；09-存储片；14、1400、1401、1402-MTJ。
具体实施方式
在介绍本申请涉及的实施例之前，先对本申请涉及的技术术语进行详细解释，具体如下。
自旋极化电流：电子运动过程中自旋的方向是随机的，向上以及向下各一半，则为非极化的电流；运动的电子的自旋具有一定的方向性，向上和向下的不对称，即为自旋极化电流，当只有向上极化的电子或者只有向下极化的电子时，则极化电流的极化率为100％。
自旋轨道力矩(spin-orbit torque，SOT)：是电子的自旋磁矩和轨道磁矩的相互作用。
隧穿磁电阻(tunneling magneto resistance，TMR)效应：是指在铁磁-绝缘体-铁磁薄膜材料中，其穿隧电阻大小随两边铁磁材料相对方向变化的效应，也可以这样讲，磁性隧道结MTJ中的两个铁磁层磁化方向平行排列时，MTJ具有低电阻态，反平行排列时，MTJ具有高电阻态。
电压调控磁各向异性(voltage-controlled magnetic anisotropy，VCMA)效应：是指在MTJ的两端施加电压时，会改变MTJ中自由层的垂直各向异性，从而减小(或增加)自由层磁矩的临界翻转电流密度，VCMA效应的大小与加在MTJ两端的电压差成正比。
下面结合附图介绍本申请提供的实施例。
本申请实施例提供一种包含磁性随机存储器的电子设备。图2为本申请实施例提供的一种电子设备200，该电子设备200可以是终端设备，例如手机，平板电脑，智能手环，也可以是个人电脑(personal computer，PC)、服务器、工作站等。
该电子设备200可以包括总线205，以及与总线205连接的片上系统(system on chip，SOC)210和只读存储器(read-only memory，ROM)220。SOC210可以用于处理数据，例如处理应用程序的数据，处理图像数据，以及缓存临时数据。ROM220可以用于保存非易失性数据，例如音频文件、视频文件等。ROM220可以为PROM(programmable read-only memory，可编程序只读存储器)，EPROM(erasable programmable read-only memory，可擦除可编程只读存储器)，闪存(flash memory)等。
此外，电子设备200还可以包括通信芯片230和电源管理芯片240。通信芯片230可以用于协议栈的处理，或对模拟射频信号进行放大、滤波等处理，或同时实现上述功能。电源管理芯片240可以用于对其他芯片进行供电。
在一种实施方式中，SOC210可以包括用于处理应用程序的应用处理器(application processor，AP)211，用于处理图像数据的图像处理单元(graphics processing unit，GPU)212，以及用于缓存数据的随机存取存储器(random access memory，RAM)213。
上述AP211、GPU212和RAM213可以被集成于一个裸片(die)中，或者分别集 成于多个裸片(die)中，并被封装在一个封装结构中，例如采用2.5D(dimension)，3D封装，或其他的先进封装技术。在一种实施方式中，上述AP211和GPU212被集成于一个die中，RAM213被集成于另一个die中，这两个die被封装在一个封装结构中，以此获得更快的die间数据传输速率和更高的数据传输带宽。
图3为本申请实施例提供的一种磁性随机存储器(magnetic random access memory，MRAM)300的结构示意图。在一种实施方式中，磁性随机存储器300也可以是设置于SOC210外部的RAM。本申请不对磁性随机存储器300在设备中的位置以及与SOC210的位置关系进行限定。
继续如图3，磁性随机存储器300包括存储阵列310、译码器320、驱动器330、时序控制器340、缓存器350和输入输出驱动360。存储阵列310包括多个呈阵列排列的存储单元400，其中每个存储单元400可以用于存储1bit或者多bit的数据。存储阵列310还包括字线(word line，WL)、位线(bit line，BL)、源线(source line，SL)和控制线(control line，CL)等信号线。每一个存储单元400都与对应的字线WL、位线BL、源线SL和控制线CL电连接。每一个存储单元400中的核心结构是磁性隧道结MTJ，上述字线WL、位线BL、源线SL或控制线CL中的一个或多个用于通过接收控制电路输出的控制电平，选择存储阵列中待读写的存储单元400，以使磁性隧道结MTJ中的两个铁磁层磁化方向平行排列或者反平行排布，进而写入不同的逻辑信息。为了方便，本申请实施例将上述字线WL、位线BL、源线SL和控制线CL统称为信号线。
在图3所示磁性随机存储器300结构中，译码器320用于根据接收到的地址进行译码，以确定需要访问的存储单元400。驱动器330用于根据译码器320产生的译码结果来控制信号线的电平，从而实现对指定存储单元400的访问。缓存器350用于将读取的数据进行缓存，例如可以采用先入先出(first-in first-out，FIFO)来进行缓存。时序控制器330用于控制缓存器350的时序，以及控制驱动器330驱动存储阵列310中的信号线。输入输出驱动360用于驱动传输信号，例如驱动接收的数据信号和驱动需要发送的数据信号，使得数据信号可以被远距离传输。
上述存储阵列310、译码器320、驱动器330、时序控制器340、缓存器350和输入输出驱动360可以集成于一个芯片中，也可以分别集成于多个芯片中。
在上述的磁性随机存储器中，可以是通过自旋霍尔效应(spin hall effect，SHE)写入的自旋轨道力矩(spin-orbit torque，SOT)磁性随机存储器，自旋轨道力矩磁性随机存储器可以被称为SOT-MRAM。
在SOT-MRAM的存储单元中，写入通路和读取通路是分开的，因此相比自旋转移力矩(spin-transfer torque，STT)-MRAM，磁性隧道结MTJ不容易被击穿，器件耐久性更高。另外，SOT-MRAM的存储单元中是通过自旋轨道耦合效应改变MTJ中自由层的磁化取向，而不是STT-MRAM存储单元中的利用电子经过MTJ的参考层时被自旋极化，极化的电子再经过自由层时，与自由层磁矩发生作用，从而改变自由层的磁矩状态，在进行写入时，写入电流不流经MTJ的隧道层结区，这样可以保护MTJ的隧道层，降低隧道层被击穿的风险，进而可以增强该存储单元读写数据的稳定性， 提升存储单元的使用耐久性。
由于SOT-MRAM存储单元的写入通路和读取通路是分开的，所以，通常需要两个晶体管，或者，一个晶体管和一个选择器来控制读写操作，图4a和图4b所示为两种不同的SOT-MRAM存储单元结构。
图4a和图4b的区别在于，图4a是2T1R存储单元，图4b是1T1R1D存储单元，这里的T示为晶体管(transistor)，R示为MTJ，D示为单向导通的二极管(diode)。
在图4a中，SHE电极线04的一端与位线(bit line，BL)电连接，SHE电极线04的另一端与具有三端子的晶体管051的第一端电连接，晶体管051的第二端与源线(source line，SL)电连接，晶体管051的栅极与写入字线(write word line，WWL)电连接，MTJ14的自由层03与SHE电极线04接触并电连接，MTJ14的参考层01与具有三端子的晶体管052的第一端电连接，晶体管052的第二端与源线SL电连接，晶体管052的栅极与读取字线(read word line，RWL)电连接。由此，图4a所示的一个存储单元中包含SHE电极线04、MTJ14、晶体管051和晶体管052。
在图4b中，SHE电极线04的一端与BL电连接，SHE电极线04的另一端与具有三端子的晶体管05的第一端电连接，晶体管05的第二端与源线SL电连接，晶体管05的栅极与写入字线WWL电连接，MTJ14的自由层03与SHE电极线04接触并电连接，MTJ14的参考层01与二极管06的阴极端电连接，二极管06的阳极端与读取字线RWL电连接。由此，图4b所示的一个存储单元中包含SHE电极线04、MTJ14、晶体管05和二极管06。
图4b相比于图4a结构，一个存储单元中可以少用一个晶体管，这样可以有效提升存储单元密度，但是又很难找到一个电学性质(比如，开启电压、电阻值等)与MTJ相匹配的二极管06，进而采用二极管作为选择器的可行性也较低。
图5a示出的存储阵列310中包含图5a所示的多个2T1R存储单元，图5b示出的存储阵列310中包含图5b所示的多个1T1R1D存储单元。
为了增加存储单元密度，可以在一个SHE电极线上并排设置多个MTJ，比如，在图5a中，第一SHE电极线041上并排设置多个与其相连接的MTJ1400、MTJ1401、MTJ1402、MTJ140n等，在第二SHE电极线042上并排设置多个与其相连接的MTJ1410、MTJ1411、MTJ1412、MTJ141n等，还有，与SHE电极线电连接的晶体管的栅极，和与多个MTJ电连接的多个晶体管的栅极均与字线WL电连接，例如，在图5a中，与第一SHE电极线041电连接的晶体管051的栅极和多个晶体管052的栅极均与字线WL0电连接，也就是通过字线WL0控制晶体管051和多个晶体管052的导通和断开。
图5a和图5b所示的两种不同的存储阵列310，都是基于自旋轨道力矩效应和电压调控磁各向异性(voltage-controlled magnetic anisotropy，VCMA)效应写入信息，不同的是在图5a中，采用与MTJ连接的晶体管作为MTJ的选择器，在图5b中，采用与MTJ连接的二极管作为MTJ的选择器，也就是通过控制与MTJ串联的晶体管052或者二极管06的导通与否来选择要读写的MTJ。
下面介绍VCMA效应的原理：如图4a和图4b，在MTJ14两端施加偏置电压可以改变MTJ中自由层03与隧道层02的界面电荷密度，从而改变自由层03的垂直各向异性和矫顽力，进而降低MTJ14的临界翻转电流密度。这样的话，在利用VCMA效 应降低MTJ14临界翻转电流密度的同时，在SHE电极线04中通入写电流，在自旋轨道力矩SOT效应和VCMA效应的共同作用下使得自由层03中的磁矩发生翻转，实现数据的写入，这种写入方式可以显著降低数据写入的功耗。对于非写入的存储单元，可以在MTJ两端施加另一个电压，增加其临界翻转电流密度，这样即使SHE电极线中有电流流过，非写入单元的自由层磁矩方向不变。故可以通过在MTJ两端施加不同的电压，来选择MTJ是否写入。
现以图5a所示结构为例来说明该存储器的读写原理，具体如下。
在图5a中，当给MTJ1401中写入数据时，给字线WL0施加高电位“1”，则字线WL0控制的一系列晶体管052和晶体管051均导通，给位线BL施加高电位“1”，给源线SL施加低电位“0”，则第一SHE电极线041中有向左的电流流过，同时给与MTJ1401串联的晶体管052连接的控制线CL1施加低电位“0”，则MTJ1401上下端产生负电压差，在VCMA作用下，MTJ1401的临界翻转电流密度降低，同时第一SHE电极线041上的电流使得MTJ1401的自由层发生翻转，实现信息写入。
与此同时，对于WL0控制的其他非写入单元MTJ1400、MTJ1402…MTJ140n,在与他们串联连接的晶体管连接的控制线CL上施加高电位“1”，则这些MTJ的上下端产生正电压差，VCMA效应使得MTJ1400、MTJ1402、MTJ140n等MTJ的临界翻转电流密度增加，第一SHE电极线041上的电流不能使得这些MTJ的自由层翻转，进而不写入信息。
还有，对于其他字线WL则施加低电位“0”(例如给字线WL1施加低电位“0”)，字线WL1控制的晶体管均处于关闭状态，这样，字线WL1控制的多个存储单元均不能写入信息。
在读取数据时，可以同时读取多个MTJ中的数据，比如，在图6中，图6是图5a所示结构在读取时的原理图，给字线WL0施加高电位“1”，则字线WL0控制的一系列晶体管052和晶体管051均导通，给与MTJ1400、MTJ1402…MTJ140n的串联的晶体管连接的CL0、CL1、CL2等上施加Vread，以及给源线SL和位线BL接地，实现MTJ1400、MTJ1402…MTJ140n等存储单元的读取，同时其他字线WL施加低电位“0”，则施加低电位“0”的字线WL控制的晶体管处于关闭状态，相应的MTJ上无读取电流通过。
除此之外，图5a和图5b所示的两种不同的存储结构，还有一个明显的特点是通过给MTJ上串联一个晶体管或者串联一个二极管可以抑制读写操作时漏电通道(sneak paths)，减少信息读写时的漏电功耗。
下面以图5a结构为例来说明抑制漏电通道的过程，具体如下。
图7是图5a所示结构去掉与MTJ串联的晶体管，形成漏电通道的原理图，还是以向MTJ4101写入信息为例说明：给字线WL0施加高电位“1”，则字线WL0控制的晶体管051导通，给源线SL施加高电位“1”，给位线BL施加低电位“0”，则第一SHE电极线041中有向左的电流流过，同时给与MTJ1401连接的控制线CL1施加低电位“0”，其他控制线CL施加高电位“1”，其他字线WL施加低电位“0”。在VCMA效应和SOT效应的共同作用下，只有MTJ1401的自由层发生翻转，实现信息写入。
但是在该写入操作过程中，由于不同控制线CL之间有电位差，那么，在任意两个具有电位差的控制线CL之间串联的两个MTJ就会形成一条漏电通道，比如，如图7中的控制线CL1和控制线CL0之间具有电位差，MTJ1411和MTJ1401之间形成一条漏电通道，还有，控制线CL1和控制线CL2之间也具有电位差，MTJ1411和MTJ1412之间也形成一条漏电通道，以产生额外的写功耗。同时，由于漏电通道的存在，使得一个SHE电极上不同位置的MTJ实际感受到的写电流也有差异，会增加写入误差。因此，采用图5a和图5b所示存储单元时，在实现写入通路和读取通路分开的前提下，还可以减小写入时的漏电流。
当采用图5a和图5b所示存储单元时，由于每一个MTJ串联一个晶体管或者串联一个二极管，进而会降低存储密度，降低集成度，若为了提升存储密度去掉与MTJ串联的晶体管或者二极管，又会出现漏电现象；为了抑制漏电，引入与MTJ串联的晶体管或者二极管后，又会因为与MTJ串联的晶体管或者二极管具有内阻，在读写操作时会有分压作用，进而就会降低MTJ两端的电压，削弱VCMA效应，减小读写操作的可工作电压范围，影响读写的准确性。
所以，设计一种既可以抑制漏电通道，又可以提高存储密度，增强VCMA效应，提高读写操作的可工作电压范围是很有必要的。
图8示出了本申请的一种存储器中部分存储单元形成的存储阵列310结构，在该存储阵列310的存储单元中，包括SHE电极线04和与SHE电极线04电连接的MTJ14，以及与SHE电极线04电连接的晶体管05。特别的是，这里的MTJ14是单向导通的MTJ结构，可以这样讲，MTJ在通入第一方向的电流时处于正向导通状态，并在通入第二方向的电流时处于反向截止状态，第一方向和第二方向互为相反的方向。这里的第一方向和第二方向均是正电流的方向。
在一些可选择的实施方式中，MTJ结构14的正向导通电流和反向截止电流的比值I on/I off可以大于10，或者，I on/I off在10左右。
如图8所示，该图中的MTJ14是一种由远离SHE电极线04的顶端朝靠近离SHE电极线04的底端导通的MTJ结构(其中，在图8中，三角形的指向，为正向导通方向)，或者，也可以是图9所示的由靠近SHE电极线04的底端朝远离SHE电极线04的顶端导通的MTJ结构。
在图8和图9所示MTJ14结构中，沿着MTJ14的导通方向，MTJ14具有低电阻特性，电流沿着MTJ14结构反方向流动时，MTJ14具有高电阻特性，故在图8中，当MTJ14顶端为高电位，底端为低电位时，MTJ为导通低电阻态，在图9中，当MTJ14底端为高电位，顶端为低电位时，MTJ14为导通低电阻态。
图10给出了一种单向导通的MTJ14结构和SHE电极线04的连接关系图。
如图10，示出的MTJ14结构也包括参考层01、隧道层02和自由层03，隧道层02形成在参考层01和自由层03之间，只是该结构中的隧道层02包括至少两层结构，比如，在图10中，示出了包括第一隧道层021和第二隧道层022的隧道层02结构，该第一隧道层021和第二隧道层022由不同的绝缘材料制得，比如，可以选择AlO、ZnO、CoO、MgO、MgAlO等金属氧化物。这样，电流可以依次通过MTJ14的参考层 01、隧道层02和自由层03，实现MTJ14由顶端至底端的导通低电阻态。另外，第一隧道层021和第二隧道层022也可以采用不同的铁电材料制得，也可以采用不同的半导体材料制得。
不仅可以通过采用不同材料制得多层的隧道层，以使MTJ14具有单向导通特性。另外，在采用不同材料制得多层的隧道层的基础上，还可以通过改变不同隧道层的厚度实现MTJ14的单向导通特性。
在另外一些可实现的方式中，参考层01可以选择SrRuO 3材料制得，自由层03可以选择La 2/3Sr 1/3MnO 3材料制得，隧道层02采用绝缘材料、半导体材料或铁电材料等制得，这样形成的MTJ14结构也具有单向导通性。还有，也可以通过给参考层01和自由层03的磁性材料中进行掺杂，改变这两层结构的费米能处的能带结构，从而调节MTJ14的电学特性，以实现单向导通特性。
在图8和图9所示的存储器中，存储单元中的SHE电极线04的一端与位线BL电连接，另一端与晶体管05的第一端电连接，晶体管05的第二端与源线SL电连接，以及，晶体管05的栅极与字线WL电连接，结合图8和图10，MTJ14结构的自由层03形成在SHE电极线04上，并与SHE电极线04电连接，MTJ14结构的参考层01与读线(read line，RL)电连接。
在一种实施方式中，图3的时序控制器340包括用于控制这些信号线的一个或多个子控制器。这些一个或多个子控制器跟上述信号线之间可以是一一对应的关系，也可以是多对多的关系。例如，时序控制器340可以仅通过一个子控制器控制所有的信号线。或者，时序控制器340也可以包括4个子控制器，其中字线子控制器用于控制所有类型的字线上的电压，位线子控制器用于控制所有类型的位线上的电压，源线子控制器用于控制所有类型的源线上的电压，读线控制器用于控制所有类型的读线上的电压。
在本申请的实施例中，与SHE电极线04电连接的晶体管可以选择NMOS(N-channel metal oxide semiconductor，N沟道金属氧化物半导体)管，或者可以选择PMOS(P-channel metal oxide semiconductor，P沟道金属氧化物半导体)管，在本申请中可以将MOS管的漏极(drain)或源极(source)中的一极称为第一端，相应的另一极称为第二端。漏极和源极可以根据电流的流向而确定，比如，在图9中，电流从左到右时，则晶体管05的左端为漏极，右端为源极；相反，当电流从右向左时，晶体管05的左端为源极，右端为漏极。
在图8和图9中，多个存储单元沿相垂直的X方向和Y方向呈阵列布设，这里的X方向和Y方向是与衬底相平行的方向，这些多个存储单元形成在衬底上，以形成存储阵列310。在该存储阵列310中，沿X方向布设的多个存储单元共用一条源线SL和共用一条BL，沿Y方向布设的多个存储单元共用一条读线RL和共用一条字线WL。这样的话，可以简化整个存储器的布线，提升存储密度。
下面结合图11至图14介绍本申请给出的存储器的读写原理，具体如下。
在图11中，当给存储单元A1的MTJ14中写入数据时，给WL0施加高电位“1”，则WL0控制的一系列晶体管均导通，比如，图11中的存储单元A1和存储单元A2中的晶体管05均导通，其他非写入存储单元连接的字线WL施加低电位“0”，比如， 给图11中的位线WL1施加低电位“0”，这样非写入存储单元的晶体管均不导通，给位线BL0施加写入电压，给源线SL0接地，位线BL1和源线SL1均接地。则存储单元A1中的SHE电极线04中有向右的电流流过，在SHE电极线04中的自旋极化电流的作用下，存储单元A1的MTJ14中的自由层发生翻转，实现信息写入。其他非写入存储单元的SHE电极线上无写电流流过，不能写入信息。
另外，当改变存储单元A1的SHE电极线04上的写电流方向，则可以在存储单元A1的MTJ14中写入相反的信息，如图12，给WL0施加高电位“1”，则WL0控制的一系列晶体管均导通，给SL0施加写入电压，BL0接地，进而，存储单元A1的SHE电极线04上具有向左的电流流过，以写入相反的信息。
在图13中，读取存储单元A1的MTJ14中的数据时，给与存储单元A1的MTJ14的参考层电连接的读线RL0接Vread，位线BL0接地，其他位线BL(比如位线BL1)均接Vread,其他源线SL(比如源线SL1)均接地,所有字线WL接低电位“0”，进而所有存储单元的晶体管均关闭，则只有存储单元A1的MTJ14，和存储单元A4的MTJ14两端具有读电压差，由于存储单元A1的MTJ14处于低电阻态的导通状态，由此可以实现对存储单元A1的读操作，但是，存储单元A4的MTJ14处于高电阻态的反向截止状态，存储单元A4的漏电流小，该漏电通道被抑制。
图14是另外一种存储器的存储阵列的结构图，和图13的区别是，图14中的MTJ14的正向导通方向和图13中的MTJ14的正向导通方向是相反的。
那么，再结合图14所示结构介绍读取过程，如图14，依然以读取存储单元A1的MTJ14中的数据为例，给与存储单元A1的MTJ14的参考层电连接的读线RL0接地,其他读线RL(比如读线RL1)均接Vread,位线BL0接Vread，其他位线BL(比如位线BL 1)均接地，所有字线WL接低电位“0”，进而所有存储单元的晶体管均关闭，因为所有字线WL均接低电位“0”，与字线WL电连接的晶体管处于关闭状态，那么，所有的源线SL均可以接地，也可以接其他电压，这样的话，则只有存储单元A1的MTJ14，和存储单元A4的MTJ14两端具有读电压差，由于存储单元A1的MTJ14处于低电阻态的导通状态，由此可以实现对存储单元A1的读操作，但是，存储单元A4的MTJ14处于高电阻态的反向截止状态，存储单元A4的漏电流小，该漏电通道被抑制。
由图11至图14还可以看出，在每一个存储单元中仅具有与SHE电极线04电连接的晶体管05，省略了与MTJ电连接的选择器(比如，晶体管或者二极管)，进而，会提升该存储器的存储密度，提升存储容量。
从工艺角度讲，由于省略了设置在MTJ上的选择器，从而，可以简化制备工艺，提高生产效率。
在图11至图14所示的存储器的存储阵列310中，每一个存储单元的MTJ14具有与SHE电极线04电连接的一个MTJ14，为了进一步提升该存储器的存储密度，图15给出了另一种包含单向导通的MTJ14的存储器。
结合图15，每个SHE电极线04上并排设置多个具有单向导通性的MTJ14结构，也就是说，多个具有单向导通性的MTJ14与同一个SHE电极线04电连接，这样的话，多个存储单元可以共用一个SHE电极线04和晶体管05，从而，可以减少晶体管05 的数量，进一步提升存储密度。
本申请对与同一个SHE电极线04电连接的MTJ14的数量不做特殊限定，图15仅以具有四个MTJ14为例来说明。
MTJ14的单向导通方向可以是图15所示的由MTJ14的顶端至底端，当然，也可以是导通方向由底端至顶端的MTJ14结构。
继续结合图15，该存储器还包括晶体管05、字线WL、源线SL、位线BL和控制线CL。其中，SHE电极线04的一端与位线BL电连接，SHE电极线04的另一端与晶体管05的第一端电连接，晶体管05的第二端与源线SL电连接，与该MTJ14电连接的多个MTJ14的自由层均与MTJ14接触电连接，每一个MTJ14的参考层与相对应的控制线CL电连接，晶体管05的栅极与字线WL电连接。
也就是写操作时可以通过字线WL来控制晶体管的导通，以及位线BL和源线SL所加电位来给SHE电极线04通写电流，同时通过控制线CL上施加的电压产生VCMA效应来选择性写入特定MTJ。
在图15中，一个SHE电极线04与一个晶体管05电连接，在另外一些可选择的实施方式中，如图16，一个SHE电极线04与至少两个晶体管05电连接。如图16所示的，SHE电极线04的一端与晶体管051的第一端电连接，SHE电极线04的另一端与晶体管052的第一端电连接，晶体管051的第二端与源线SL电连接，晶体管052的第二端与位线BL电连接，还有，晶体管051的栅极和晶体管052的栅极均与字线WL电连接。通过与SHE电极线04串联两个晶体管，可以进一步减小漏电，降低漏电功耗。
继续结合图15和图16，多个存储单元沿相交的X方向和Y方向呈阵列布设，以形成存储阵列310。在该存储阵列310中，沿X方向布设的多个存储单元共用一条源线SL和共用一条位线BL，沿Y方向布设的多个存储单元共用一条字线WL，另外，沿X方向布设的多个MTJ14共用一条控制线CL。这样的话，可以简化整个存储器的布线，提升存储密度。
结合图17，以向虚线框起来的MTJ1400写入数据为例来说明写入操作过程：给字线WL1施加高电位“1”，则WL1控制的一行晶体管(如图17的晶体管052和晶体管052)均处于导通状态，其他字线WL加低电位“0”(比如，字线WL2接低电位“0”)，则其他行的晶体管处于关闭状态，给与SHE电极线041连接的位线BL1施加高电位“1”，源线SL1接地，其他非写入单元连接的源线SL和位线BL均接地(比如，源线SL2和位线BL2均接地)，那么则只有SHE电极线041上有自右向左的写电流流过，与此同时，给与MTJ1400连接的控制线CL1施加低电位“0”，与SHE电极线041连接的其他MTJ的控制线CL施加高电位“1”，还给其他与MTJ1400不共用SHE电极线的MTJ的控制线CL施加低电位“0”，比如给与SHE电极线042连接的MTJ的控制线CL施加低电位“0”，根据VCMA效应，当MTJ顶端与底端电压差为负值时，VCMA效应会降低MTJ的临界翻转电流密度。故在SHE电极线041写电流和VCMA效应共同作用下，只有MTJ1400的自由层能发生翻转，其他非写入单元MTJ的自由层磁矩方向不变，即向MTJ1400写入信息。
通过改变SHE电极线041中电流方向，如图18所示，给源线SL1施加高电位“1”， 位线BL1接地，可以向MTJ1400写入相反的信息。
图15至图18所示的存储器中，信息的读取可以一次读取一个MTJ的存储数据，也可以一次读取共用一个SHE电极线的多个MTJ的存储数据。
结合图19，以向虚线框起来的四个MTJ读取数据为例来说明读操作过程：给字线WL1施加高电位“1”，则字线WL1控制的一行晶体管均处于导通状态，其他字线WL加低电位“0”(比如，字线WL2接低电位“0”)，则其他行的晶体管处于关闭状态，给与虚线框出的四个MTJ连接的控制线CL1、控制线CL2、控制线CL3和控制线CL4分别施加高电位“1”，其他非读取MTJ连接的控制线CL均接地，所有的源线SL和位线BL均接地，这样的话，只有虚线框起来的四个MTJ内有从参考层至自由层的读电流流过，即实现选定存储单元的信息读取。
结合图20，以向虚线框起来的一个MTJ读取数据为例再来说明读操作过程：给WL1施加高电位“1”，则WL1控制的一行晶体管均处于导通状态，其他WL加低电位“0”(比如，WL2接低电位“0”)，则其他行的晶体管处于关闭状态，给与虚线框出的MTJ1400连接的控制线CL1施加高电位“1”，控制线CL2、控制线CL3和控制线CL4，以及其他非读取MTJ连接的控制线CL均接地，还有，所有的源线SL和位线BL均接地，这样的话，只有虚线框起来的MTJ1400内有从参考层至自由层的读电流流过，即实现MTJ1400信息的读取。
在图20中，MTJ的正向导通方向为从参考层至自由层，在图21中，MTJ的正向导通方向为从自由层至参考层，下面再结合图21介绍该结构的读取过程。
结合图21，仍以向虚线框起来的一个MTJ读取数据为例再来说明读操作过程：给WL1施加高电位“1”，则WL1控制的一行晶体管均处于导通状态，其他WL加低电位“0”(比如，WL2接低电位“0”)，则其他行的晶体管处于关闭状态，给与虚线框出的MTJ1400连接的源线SL和位线BL均施加高电位“1”，给与虚线框出的MTJ1400连接的控制线CL1施加低电位“0”，控制线CL2、控制线CL3和控制线CL4施加高电位“1”，以及其他非读取MTJ连接的控制线CL均接地，这样的话，只有虚线框起来的MTJ1400内有从自由层至参考层的读电流流过，即实现MTJ1400信息的读取。
在上述的图15至图21所示的存储器中，由于多个MTJ共用一个SHE电极线，并且共用的SHE电极线通过一个或者两个晶体管控制，相比现有技术，可以大大减少晶体管的数量，提高存储密度，同时由于每一个MTJ没有串联晶体管或者二极管，会进一步提升存储密度，并且单向导通MTJ的使用可以避免串联晶体管或者二极管的分压，写操作时落在MTJ两端的电压增大，VCMA效应增强，提高了写操作的可工作电压范围，降低功耗。
图22给出了包含单向导通MTJ的存储阵列310的三维结构图，在存储阵列310中，包含多个MTJ14和多个SHE电极线04，这些多个MTJ14和多个SHE电极线04沿彼此互相垂直的X方向和Y方向，以及Z方向呈阵列布设，形成多层呈3D堆叠的结构，这里的X方向和Y方向可以是与衬底相平行的方向，Z方向是与衬底相垂直的方向。
图23是图22的在Y-Z平面内的部分结构图，结合图23，在Z方向上，并排布设 多个SHE电极线，比如，图23中示出了并排布设的SHE电极线041、SHE电极线042和SHE电极线043，这些在Z方向上并排布设的多个SHE电极线通过连接线并联连接，并联连接的多个SHE电极线共用晶体管，比如，在图23中，SHE电极线041、SHE电极线042和SHE电极线043通过第一连接线071和第二连接线072并联连接，第一连接线071与晶体管051的第一端电连接，第二连接线072与晶体管052的第一端电连接，以形成一个存储片09，这样一来，在晶体管051和晶体管052均导通的情况下，可以给存储片09中所有SOT电极线上并行施加读写电流。需要说明的是，这里也可以是仅包括有一个晶体管。
与现有的给沿Z方向上并排布设的多个SHE电极线中的每一个SHE电极线连接晶体管相比，本申请可以大大减少晶体管的数量，进一步提升存储密度，提升存储容量。
继续结合图23，在一个存储片09中，晶体管051的第二端与源线SL连接，晶体管052的第二端与位线BL连接，源线SL和位线BL沿与Y-Z平面垂直的X方向延伸。还有，在该存储片09中，每一个SHE电极线上可以连接多个MTJ14，比如，在图23中的SHE电极线041、SHE电极线042和SHE电极线043上均并排设置三个MTJ14，每一个MTJ14都对应连接有控制线CL，并且这些多个控制线CL也沿与Y-Z平面垂直的X方向延伸。
将图23所示的一个存储片09结构沿着X方向排布成多个，就会形成图22的结构，可以把沿X方向排布的多个存储片结构形成的结构叫存储块(block)，比如，在图22，沿X方向排布了三个存储片，组成了一个存储块(block)结构。
在图22中，沿X方向排布的多个存储片中，多个晶体管051可以共用源线SL，以及多个晶体管052共用位线BL。还有，沿X方向排布的多个MTJ14可以共用控制线CL。
例如还需要更多的存储单元时，可以将图22所示的存储块沿Y方向排布，形成容量更大的存储器结构。
在一些可选择的实施方式中，如图22和图23所示，可以先在衬底上形成晶体管051和晶体管052，然后在晶体管051和晶体管052的上方形成多层堆叠的MTJ14。
在图22所示的存储器在进行写操作时，在待写入MTJ14所在存储片连接的WL上施加栅极偏置电压，则该WL控制的晶体管051和晶体管052处于导通状态，并且，在待写入MTJ14所在存储片的源线SL和位线BL之间施加写电压，则只有待写入MTJ14所在存储片的SHE电极线上有写电流流过，即唯一选中了待写入MTJ14所在存储片。同时，在待写入MTJ14连接的控制线CL上施加低电位“0”，选中存储片中其他控制线CL均施加高电位“1”。在SOT效应和VCMA效应的共同作用下，可以实现对待写入MTJ14的选择性写入。
在图22所示的存储器在进行读操作时，可以一次读取选中存储片内所有的MTJ14中的信息，即在待读取存储片连接的WL上施加栅极偏置电压，WL控制的晶体管051和晶体管052处于导通状态。将待读取存储片的与源线SL和位线BL均接地，其他非读取存储片的源线SL和位线BL均接Vread。同时，将存储器中所有控制线CL接Vread，则只有待读取存储片的MTJ14上有读电流流过，实现一次读取选中存储片中所有 MTJ14的信息。
在该3D堆叠的存储器结构中，当两个控制线CL上施加的电压不一样(也就是具有高低电位)，即有电压差时，两个控制线CL之间串联的两个MTJ14就会形成一条漏电通道，漏电通道会显著增加3D阵列写入的功耗，进而会限制了3D堆叠的层数。例如，在图24中，当对与MTJ1402连接的控制线CL2施加高电位“1”，对与MTJ1401连接的控制线CL1，和对与MTJ1403连接的控制线CL3均施加低电位“0”时，就会在串联的MTJ1401和MTJ1402之间，以及MTJ1402和MTJ1403之间形成漏电通道，但是，由于在本申请中给出的MTJ为单向导通，这样的话，MTJ1402处于低电阻态，MTJ1401和MTJ1403均处于高电阻态，因此漏电通道的电阻值非常大，漏电流很小，因此本方案可以实现高密度低功耗的存储。
另外，该存储器还包括分别与磁性随机存储器中的所有控制线CL一一对应连接的多个放大器08(sense amplifier，SA)，多个放大器08中的每个放大器08用于读取对应连接的控制线CL所接收的反馈信息。
在本说明书的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (36)

  1. 一种磁性随机存储器，其特征在于，包括：衬底和呈阵列布设在所述衬底上的多个存储单元，任一所述存储单元包括：
    自旋霍尔效应SHE电极线；
    至少一个磁性隧道结MTJ，任一所述MTJ包括堆叠的参考层、隧道层和自由层，且所述自由层与所述SHE电极线电连接；
    晶体管，与所述SHE电极线电连接；
    其中，所述MTJ在通入第一方向的电流时处于正向导通状态，并在通入第二方向的电流时处于反向截止状态，所述第一方向和所述第二方向互为相反的方向。
  2. 根据权利要求1所述的磁性随机存储器，其特征在于，所述MTJ的正向导通电流和反向截止电流的比值大于或者等于10。
  3. 根据权利要求1或2所述的磁性随机存储器，其特征在于，所述隧道层包括堆叠的第一隧道层和第二隧道层，所述第一隧道层和所述第二隧道层由不同的材料制得。
  4. 根据权利要求3所述的磁性随机存储器，其特征在于，所述第一隧道层和所述第二隧道层沿堆叠方向的厚度不同。
  5. 根据权利要求3或4所述的磁性随机存储器，其特征在于，所述第一隧道层和所述第二隧道层的材料包括金属氧化物、铁电材料或者半导体材料中的至少一种。
  6. 根据权利要求1或2所述的磁性随机存储器，其特征在于，所述参考层包括SrRuO 3材料，所述自由层包括La 2/3Sr 1/3MnO 3材料。
  7. 根据权利要求1-6中任一项所述的磁性随机存储器，其特征在于，任一所述存储单元中具有一个所述MTJ，所述磁性随机存储器还包括：源线、位线、字线和读线；
    所述SHE电极线的一端与所述位线电连接，所述SHE电极线的另一端与所述晶体管的第一端电连接，所述晶体管的第二端与所述源线电连接，所述晶体管的栅极与所述字线电连接，所述参考层与所述读线电连接。
  8. 根据权利要求7所述的磁性随机存储器，其特征在于，所述MTJ的写入过程中；
    与所述MTJ相对应的所述字线用于接收栅极偏置电压，以使与所述字线电连接的所述晶体管导通；
    与所述MTJ电连接的所述读线用于接地；
    与所述MTJ电连接的所述源线和所述位线中的一个信号线用于接收写入电压，另一个信号线用于接地，以在所述SHE电极线中产生写电流。
  9. 根据权利要求7或8所述的磁性随机存储器，其特征在于，所述MTJ的正向导通方向为由所述参考层至所述自由层方向时，所述MTJ的读取过程中；
    与所述MTJ电连接的所述读线用于接收读取电压；
    与所述MTJ电连接的所述源线和所述位线均用于接地，以使所述MTJ处于读电流从所述参考层到所述自由层的正向导通状态。
  10. 根据权利要求7或8所述的磁性随机存储器，其特征在于，所述MTJ的正向导通方向为由所述自由层至所述参考层方向时，所述MTJ的读取过程中；
    与所述MTJ电连接的所述读线用于接地；
    与所述MTJ电连接的所述位线用于接收读取电压，以使所述MTJ处于读电流从 所述自由层到所述参考层的正向导通状态。
  11. 根据权利要求1-6中任一项所述的磁性随机存储器，其特征在于，任一所述存储单元中具有多个所述MTJ，且多个所述MTJ的所述自由层与同一个所述SHE电极线电连接；
    所述磁性随机存储器还包括：源线、位线、字线和多个控制线；
    所述SHE电极线的一端与所述位线电连接，所述SHE电极线的另一端与所述晶体管的第一端电连接，所述晶体管的第二端与所述源线电连接，所述晶体管的栅极与所述字线电连接，多个所述MTJ中的多个所述参考层与所述多个控制线一对一电连接。
  12. 根据权利要求11所述的磁性随机存储器，其特征在于，所述存储单元中待写入MTJ的写入过程中；
    与所述待写入MTJ相对应的所述字线用于接收栅极偏置电压，以使与所述字线电连接的所述晶体管导通；
    与所述待写入MTJ电连接的所述控制线用于接收第一偏置电压；
    与所述待写入MTJ电连接的所述源线和所述位线中的一个信号线用于接收写入电压，另一个信号线用于接地，以在所述SHE电极线中产生写电流。
  13. 根据权利要求12所述的磁性随机存储器，其特征在于，所述存储单元中待写入MTJ的写入过程中，共用所述SHE电极线的其余所述MTJ电连接的所述控制线用于接收与所述第一偏置电压不相等的第二偏置电压。
  14. 根据权利要求11-13中任一项所述的磁性随机存储器，其特征在于，所述MTJ的正向导通方向为由所述参考层至所述自由层方向时，所述存储单元中待读取MTJ的读取过程中；
    与所述待读取MTJ电连接的所述控制线用于接收读取电压；
    与所述待读取MTJ电连接的所述源线和所述位线均用于接地，以使所述待读取MTJ处于读电流从所述参考层到所述自由层的正向导通状态。
  15. 根据权利要求14所述的磁性随机存储器，其特征在于，所述存储单元中所述待读取MTJ的读取过程中，共用所述SHE电极线的其余所述MTJ电连接的所述控制线均用于接地。
  16. 根据权利要求11-15中任一项所述的磁性随机存储器，其特征在于，所述MTJ的正向导通方向为由所述自由层至所述参考层方向时，所述存储单元中待读取MTJ的读取过程中；
    与所述待读取MTJ电连接的所述控制线用于接地；
    与所述待读取MTJ电连接的所述源线和所述位线均用于接收读取电压，以使所述待读取MTJ处于读电流从所述自由层到所述参考层的正向导通状态。
  17. 根据权利要求16所述的磁性随机存储器，其特征在于，所述存储单元中所述待读取MTJ的读取过程中，共用所述SHE电极线的其余所述MTJ电连接的所述控制线均用于接收所述读取电压。
  18. 根据权利要求11-17中任一项所述的磁性随机存储器，其特征在于，所述源线、所述位线和所述控制线均沿与所述衬底相平行的第三方向延伸；
    所述多个存储单元中，沿所述第三方向排布的多个所述晶体管的第二端与同一个 所述源线电连接；
    所述多个存储单元中，沿所述第三方向排布的多个所述SHE电极线与同一个所述位线电连接；
    所述多个存储单元中，沿所述第三方向排布的多个所述MTJ的所述参考层与同一个所述控制线电连接。
  19. 根据权利要求18所述的磁性随机存储器，其特征在于，所述字线沿与所述衬底相平行的第四方向延伸，所述第四方向与所述第三方向垂直；
    所述多个存储单元中，沿所述第四方向排布的多个所述晶体管的栅极与同一个所述字线电连接。
  20. 根据权利要求1-19中任一项所述的磁性随机存储器，其特征在于，所述多个存储单元中，沿与所述衬底相垂直方向排布的多个所述SHE电极线与同一个所述晶体管电连接。
  21. 根据权利要求11-20中任一项所述的磁性随机存储器，其特征在于，所述磁性随机存储器还包括控制器，所述控制器用于：
    输出控制所述源线上电压的电压控制信号；
    输出控制所述位线上电压的电压控制信号；
    输出控制所述字线上电压的电压控制信号；以及，
    输出控制所述控制线上电压的电压控制信号。
  22. 一种磁性随机存储器，其特征在于，包括：衬底和呈阵列布设在所述衬底上的多个存储单元，任一所述存储单元包括：
    自旋霍尔效应SHE电极线；
    至少一个磁性隧道结MTJ，任一所述MTJ包括堆叠的参考层、第一隧道层、第二隧道层和自由层，且所述自由层与所述SHE电极线电连接；
    晶体管，与所述SHE电极线电连接；
    其中，所述第一隧道层和所述第二隧道层由不同的材料制得。
  23. 根据权利要求22所述的磁性随机存储器，其特征在于，所述第一隧道层和所述第二隧道层沿堆叠方向的厚度不同。
  24. 根据权利要求22或23所述的磁性随机存储器，其特征在于，所述第一隧道层和所述第二隧道层的材料包括金属氧化物、铁电材料或者半导体材料中的至少一种。
  25. 根据权利要求22-24中任一项所述的磁性随机存储器，其特征在于，任一所述存储单元中具有多个所述MTJ，且多个所述MTJ的所述自由层与同一个所述SHE电极线电连接。
  26. 根据权利要求22-25中任一项所述的磁性随机存储器，其特征在于，所述多个存储单元中，沿与所述衬底相垂直方向排布的多个所述SHE电极线与同一个所述晶体管电连接。
  27. 根据权利要求22-26中任一项所述的磁性随机存储器，其特征在于，所述磁性随机存储器还包括：源线、位线、字线和读线；
    所述SHE电极线的一端与所述位线电连接，所述SHE电极线的另一端与所述晶体管的第一端电连接，所述晶体管的第二端与所述源线电连接，所述晶体管的栅极与 所述字线电连接，所述参考层与所述读线电连接。
  28. 根据权利要求27所述的磁性随机存储器，其特征在于，所述源线、所述位线和所述控制线均沿与所述衬底相平行的第三方向延伸；
    所述多个存储单元中，沿所述第三方向排布的多个所述晶体管的第二端与同一个所述源线电连接；
    所述多个存储单元中，沿所述第三方向排布的多个所述SHE电极线与同一个所述位线电连接；
    所述多个存储单元中，沿所述第三方向排布的多个所述MTJ的所述参考层与同一个所述控制线电连接。
  29. 根据权利要求28所述的磁性随机存储器，其特征在于，所述字线沿与所述衬底相平行的第四方向延伸，所述第四方向与所述第三方向垂直；
    所述多个存储单元中，沿所述第四方向排布的多个所述晶体管的栅极与同一个所述字线电连接。
  30. 一种磁性随机存储器的控制方法，其特征在于，所述磁性随机存储器中的存储单元包括：
    自旋霍尔效应SHE电极线；
    至少一个磁性隧道结MTJ，任一所述MTJ包括堆叠的参考层、隧道层和自由层，且所述自由层与所述SHE电极线电连接；
    晶体管，与所述SHE电极线电连接；
    源线、位线、字线和至少一个读线，所述SHE电极线的一端与所述位线电连接，所述SHE电极线的另一端与所述晶体管的第一端电连接，所述晶体管的第二端与所述源线电连接，晶体管的栅极与字线电连接，参考层与读线电连接；
    其中，MTJ在通入第一方向的电流时处于正向导通状态，并在通入第二方向的电流时处于反向截止状态，第一方向和第二方向互为相反的方向；
    所述控制方法包括：
    所述存储单元中待写入MTJ的写入过程中；
    向所述待写入MTJ相对应的所述字线输出栅极偏置电压，以使与所述字线电连接的所述晶体管导通；
    向所述待写入MTJ电连接的所述源线和所述位线中的一个信号线输出写入电压，另一个信号线接地，以在所述SHE电极线中产生写电流。
  31. 根据权利要求30所述的磁性随机存储器的控制方法，其特征在于，任一所述存储单元中具有一个所述MTJ；
    所述存储单元中待写入MTJ的写入过程中；
    与所述待写入MTJ电连接的所述读线接地。
  32. 根据权利要求30所述的磁性随机存储器的控制方法，其特征在于，任一所述存储单元中具有多个所述MTJ，且多个所述MTJ的所述自由层与同一个所述SHE电极线电连接；
    所述存储单元中待写入MTJ的写入过程中；
    向与所述待写入MTJ电连接的所述读线输出第一偏置电压。
  33. 根据权利要求32所述的磁性随机存储器的控制方法，其特征在于，所述存储单元中待写入MTJ的写入过程中，向共用所述SHE电极线的其余所述MTJ电连接的所述控制线输出与所述第一偏置电压不相等的第二偏置电压。
  34. 根据权利要求30-33中任一项所述的磁性随机存储器的控制方法，其特征在于，所述MTJ的导通方向为由所述参考层至所述自由层方向时，所述存储单元中待读取MTJ的读取过程中；
    向与所述待读取MTJ电连接的所述读线输出读取电压；
    与所述待读取MTJ电连接的所述源线和所述位线均接地，以使所述待读取MTJ处于读电流从所述参考层到所述自由层的正向导通状态。
  35. 根据权利要求30-33中任一项所述的磁性随机存储器的控制方法，其特征在于，所述MTJ的导通方向为由所述自由层至所述参考层方向时，所述存储单元中待读取MTJ的读取过程中；
    与所述待读取MTJ电连接的所述读线接地；
    向与所述待读取MTJ电连接的所述源线和所述位线均输出读取电压，以使所述待读取MTJ处于读电流从所述自由层到所述参考层的正向导通状态。
  36. 一种电子设备，其特征在于，包括：
    电路板；
    如权利要求1～29中任一项所述的磁性随机存储器；所述电路板与所述磁性随机存储器电连接。
PCT/CN2021/097558 2021-05-31 2021-05-31 磁性随机存储器及其控制方法、电子设备 WO2022252099A1 (zh)

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