WO2023023879A1 - 一种磁性随机存储器及电子设备 - Google Patents

一种磁性随机存储器及电子设备 Download PDF

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WO2023023879A1
WO2023023879A1 PCT/CN2021/113928 CN2021113928W WO2023023879A1 WO 2023023879 A1 WO2023023879 A1 WO 2023023879A1 CN 2021113928 W CN2021113928 W CN 2021113928W WO 2023023879 A1 WO2023023879 A1 WO 2023023879A1
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line
voltage control
transistor
voltage
lines
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PCT/CN2021/113928
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English (en)
French (fr)
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李文静
叶力
金国栋
向清懿
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华为技术有限公司
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Priority to PCT/CN2021/113928 priority Critical patent/WO2023023879A1/zh
Priority to CN202180098333.0A priority patent/CN117378009A/zh
Publication of WO2023023879A1 publication Critical patent/WO2023023879A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements

Definitions

  • the present application relates to the field of storage technology, in particular to a magnetic random access memory and electronic equipment.
  • MRAM magnetic random access memory
  • MTJ magnetic tunnel junction
  • the core storage unit of MRAM is MTJ, and each MTJ includes a free layer, a potential barrier layer and a reference layer.
  • each MTJ includes a free layer, a potential barrier layer and a reference layer.
  • different data can be written by changing the direction of the magnetic moment of the free layer (that is, controlling the parallel or antiparallel arrangement of the magnetic moments of the MTJ free layer and the reference layer).
  • reading data from MTJ it can be realized by judging the high and low resistance states of MTJ.
  • the memory array of the MRAM is usually two-dimensional (2 dimensions, 2D).
  • 2D the number of memory cells per unit area
  • this method can increase the storage density of MRAM to a certain extent, when the size of MTJ is reduced to a certain extent, the thermal stability of MTJ will decrease, resulting in a decrease in the reliability of stored data, which in turn leads to a lower storage density of MRAM. Low.
  • Embodiments of the present application provide a magnetic random access memory and electronic equipment, which are used to increase the storage density of the magnetic random access memory.
  • the embodiment of the present application provides a magnetic random access memory, which includes N memory blocks, and N is an integer greater than 0; each memory block may include multiple structural units (cells) and multiple voltage control lines; multiple Each structural unit in the structural unit may include a multi-layer storage structure stacked in sequence, each storage structure in the multi-layer storage structure includes an electrode line and a plurality of storage units arranged on the electrode line, each of the plurality of storage units Each memory cell can include an MTJ and a unidirectional conduction selector, one end of each memory cell is connected to the electrode line, and the other end is connected to a voltage control line in a plurality of voltage control lines; one end of the unidirectional conduction selector is connected to the electrode line. One end of the magnetic tunnel junction MTJ is connected, the other end of the unidirectional conduction selector is connected with the voltage control line, and the other end of the magnetic tunnel junction MTJ is connected with the electrode line.
  • each memory cell includes an MTJ and a unidirectional conduction selector, when there is a voltage difference between any two memory cells to form a leakage channel, there is always a single MTJ in one memory cell.
  • the conduction selector is in the reverse cut-off state, so it can effectively limit the sneak paths between different memory cells, thereby reducing the write leakage power consumption of the MRAM.
  • the unidirectional conduction selector can be a unidirectional conduction device, and when the voltage difference applied to both ends of the unidirectional conduction selector is greater than its turn-on threshold voltage Vth (Vth>0), the unidirectional conduction selector is in the conduction state. In the low-resistance state, when the voltage difference applied to both ends of the unidirectional conduction selector is less than its turn-on threshold voltage Vth, the unidirectional conduction selector is in the cut-off high resistance state.
  • the unidirectional conduction selector when the voltage difference between the positive pole and the negative pole of the unidirectional conduction selector is greater than Vth, the unidirectional conduction selector is in a conduction low resistance state; when the voltage difference between the positive pole and the negative pole of the unidirectional conduction selector is less than Vth, The unidirectional conduction selector is in the cut-off high resistance state.
  • the positive pole of the one-way conduction selector can be connected to the voltage control line, and the negative pole of the one-way conduction selector can be connected to the MTJ, then the forward current direction of the one-way conduction selector is from the voltage control line to the electrode line, when When the voltage difference between the voltage control line and the electrode line is greater than Vth, the one-way conduction selector is in the low resistance state, and when the voltage difference between the voltage control line and the electrode line is less than Vth, the one-way conduction selector is in the cut-off state high resistance state.
  • the positive pole of the one-way conduction selector can be connected with the MTJ, and the negative pole of the one-way conduction selector can be connected with the voltage control line, then the forward current direction of the one-way conduction selector is from the electrode line to the voltage control line, when the electrode When the voltage difference between the electrode line and the voltage control line is greater than Vth, the one-way conduction selector is in the conduction low resistance state; when the voltage difference between the electrode line and the voltage control line is less than Vth, the one-way conduction selector is in the cut-off high state resistance state.
  • the electrical characteristics, heat treatment temperature, and scalability of the unidirectional conduction selector need to match the MTJ, for example, to meet: a certain turn-on voltage/current (0-2V, ⁇ A), a higher rectification ratio, High durability (Endurance), operating speed in the order of nanoseconds, low heat treatment temperature, etc.
  • the unidirectional conduction selector in this application may be a unidirectional conduction diode, such as a Schottky diode or a PN junction diode, etc., which is not specifically limited herein.
  • the unidirectional conduction selector is a Schottky diode
  • the anode of the Schottky diode can point to the voltage control line or to the electrode line, which is not limited here.
  • the unidirectional conduction selector is a PN junction diode
  • the anode of the PN junction diode can point to the voltage control line or to the electrode line, which is not limited here.
  • each MTJ may include a free layer, a barrier layer and a reference layer stacked in sequence.
  • the magnetic moment direction of the reference layer is fixed, and the magnetic moment direction of the free layer can be changed when data is written.
  • the barrier layer is used for produce tunnel magnetoresistance effect.
  • the free layer is connected to the electrode lines, and the reference layer is connected to the voltage control line through a unidirectional conduction selector. That is to say, the free layer is close to the electrode line, the reference layer is farthest from the electrode line, and the barrier layer is located between the free layer and the reference layer.
  • the magnetic moment directions of the free layer and the reference layer there is no specific limitation on the magnetic moment directions of the free layer and the reference layer, as long as the magnetic moment directions of the free layer and the reference layer are arranged in parallel or antiparallel.
  • the multiple voltage control lines are parallel; the planes where the multiple structural units are located are parallel, and the plane where each structural unit is located is perpendicular to the multiple voltage control lines.
  • each memory block all the electrode wires in each structural unit are connected in parallel through metal wires, so that when writing data or reading data in the magnetic random access memory, it can be realized simultaneously in the structural unit Read and write currents are applied to all electrode lines in the device, thereby reducing the wiring space of the group selection lines in the peripheral circuit plane, and realizing addressing and access to the multi-layer storage structure in the magnetic random access memory through fewer group selection lines.
  • the process of applying a voltage or passing a current on the electrode line can be realized by two transistors respectively connected to the two selection lines, one of which is the selection line
  • the line is connected to one end of the electrode line through a transistor, and the other group selection line is connected to the other end of the electrode line through another transistor.
  • the switching on and off of the two transistors is controlled by the word line. Apply gate bias voltage to the two transistors on the word line to make the two transistors turn on, and apply different voltages to the two selection lines, so as to apply voltage or current to the electrode line.
  • each memory block may also include: a first group selection line and a second group selection line; the first group selection line, the second group selection line, and a plurality of voltage control lines are parallel to each other; All electrode lines are respectively connected in parallel through metal wires, and each structural unit also includes a word line, a first transistor and a second transistor. Wherein, the gates of the first transistor and the second transistor are respectively connected to the word line, and the word line can be used to provide a gate bias voltage for the first transistor and the second transistor, so that the first transistor and the second transistor are turned on.
  • the source of the first transistor is connected to the first group selection line, the drain of the second transistor is connected to the second selection group line, the drain of the first transistor is connected to the first end of the electrode line through a metal wire, and the drain of the second transistor is connected to the first end of the electrode line through a metal wire.
  • the source is connected to the second end of the electrode line through a metal wire.
  • different structural units in each memory block may share the first group selection line and the second group selection line, and structural units at corresponding positions in different memory blocks share a word line.
  • the first group selection line and the second group selection line may be parallel to the voltage control lines
  • the word lines may be parallel to the electrode lines.
  • the material of the metal wire is different from that of the electrode wire
  • the metal wire may be a low-resistance metal interconnection wire
  • the electrode wire may be a material with a large spin Hall effect.
  • the first transistor and the second transistor may be N-type metal oxide semiconductor (N metal oxide semiconductor, NMOS) transistors.
  • the first transistor and the second transistor may also be other types of transistors, for example, they may be P-type metal oxide semiconductor (P metal oxide semiconductor, NMOS) transistors. This embodiment of the present application does not specifically limit it.
  • the voltage control lines corresponding to different memory blocks may be different or the same, which is not limited herein.
  • each memory block further includes: a plurality of first bit lines respectively connected to a plurality of voltage control lines in one-to-one correspondence, each of the plurality of first bit lines The bit lines are connected to corresponding voltage control lines through metal wires. In this way, different memory blocks do not run simultaneously during the write operation, thereby reducing the leakage power consumption of the entire MRAM.
  • each memory block also includes: a plurality of amplifiers respectively connected to the plurality of first bit lines in one-to-one correspondence, and each amplifier in the plurality of amplifiers is used to read the correspondingly connected first bit line The received feedback information is used to indicate the data stored in the correspondingly connected storage unit.
  • each amplifier and its peripheral circuits together form a readout loop for outputting feedback information of the storage unit corresponding to the voltage control line connected to the amplifier, so as to read data in the storage unit.
  • each amplifier can judge whether the storage unit is in a high-resistance state or a low-resistance state by comparing the feedback information (such as voltage, current, capacitance, charge and discharge time) of the storage unit with a reference value, and then determine the The data stored in the storage unit.
  • the feedback information such as voltage, current, capacitance, charge and discharge time
  • the embodiment of the present application provides a magnetic random access memory, including N memory blocks, N is an integer greater than 1; each memory block includes a plurality of structural units (cells) and a plurality of voltage control lines; a plurality of structures Each structural unit in the unit includes a multi-layer storage structure stacked in sequence, and each storage structure in the multi-layer storage structure includes an electrode line and a plurality of storage units arranged on the electrode line, and each of the plurality of storage units stores The cell includes an MTJ, and one end of each memory cell is connected to an electrode line, and the other end is connected to a voltage control line among a plurality of voltage control lines.
  • the memory block may also include a plurality of first bit lines connected to a plurality of voltage control lines in one-to-one correspondence, and each first bit line in the plurality of first bit lines is controlled by a metal wire and a corresponding voltage. line connection.
  • the magnetic random access memory provided by the embodiment of the present application, since the storage array is 3D, compared with the 2D array in the prior art, this solution can increase the surface area by superimposing the storage units in the vertical direction on the premise of ensuring the thermal stability of the storage units. storage density, thereby increasing the storage density of the magnetic random access memory.
  • the corresponding voltage control lines and the first bit lines are different between different memory blocks. In this way, different memory blocks will not run at the same time during the write operation, thereby reducing the number of memory blocks running in parallel during the write operation, reducing the sneak paths between the memory blocks, and thereby reducing the write leakage power consumption of the MRAM.
  • each MTJ may include a free layer, a barrier layer and a reference layer stacked in sequence.
  • the magnetic moment direction of the reference layer is fixed, and the magnetic moment direction of the free layer can be changed when data is written.
  • the barrier layer is used for produce tunnel magnetoresistance effect.
  • the free layer is connected to the electrode lines, and the reference layer is connected to the voltage control lines. That is to say, the free layer is close to the electrode line, the reference layer is farthest from the electrode line, and the barrier layer is located between the free layer and the reference layer.
  • the magnetic moment directions of the free layer and the reference layer there is no specific limitation on the magnetic moment directions of the free layer and the reference layer, as long as the magnetic moment directions of the free layer and the reference layer are arranged in parallel or antiparallel.
  • the multiple voltage control lines are parallel; the planes where the multiple structural units are located are parallel, and the plane where each structural unit is located is perpendicular to the multiple voltage control lines.
  • each memory block all the electrode wires in each structural unit are connected in parallel through metal wires, so that when writing data or reading data in the magnetic random access memory, it can be realized simultaneously in the structural unit Read and write currents are applied to all electrode lines in the device, thereby reducing the wiring space of the group selection lines in the peripheral circuit plane, and realizing addressing and access to the multi-layer storage structure in the magnetic random access memory through fewer group selection lines.
  • the process of applying a voltage or passing a current on the electrode line can be realized by two transistors respectively connected to the two selection lines, one of which is the selection line
  • the line is connected to one end of the electrode line through a transistor, and the other group selection line is connected to the other end of the electrode line through another transistor.
  • the switching on and off of the two transistors is controlled by the word line. Applying a gate bias voltage to the two transistors on the word line makes the two transistors turn on, and applying different voltages on the two select lines, so as to apply a voltage to the electrode line or pass in a current.
  • each memory block may also include: a first group selection line and a second group selection line; the first group selection line, the second group selection line, and a plurality of voltage control lines are parallel to each other; All electrode lines are respectively connected in parallel through metal wires, and each structural unit also includes a word line, a first transistor and a second transistor. Wherein, the gates of the first transistor and the second transistor are respectively connected to the word line, and the word line can be used to provide a gate bias voltage for the first transistor and the second transistor, so that the first transistor and the second transistor are turned on.
  • the source of the first transistor is connected to the first group selection line, the drain of the second transistor is connected to the second selection group line, the drain of the first transistor is connected to the first end of the electrode line through a metal wire, and the drain of the second transistor is connected to the first end of the electrode line through a metal wire.
  • the source is connected to the second end of the electrode line through a metal wire.
  • different structural units in each memory block may share the first group selection line and the second group selection line, and structural units at corresponding positions in different memory blocks share a word line.
  • the first group selection line and the second group selection line may be parallel to the voltage control lines
  • the word lines may be parallel to the electrode lines.
  • the material of the metal wire is different from that of the electrode wire
  • the metal wire may be a low-resistance metal interconnection wire
  • the electrode wire may be a material with a large spin Hall effect.
  • the first transistor and the second transistor may be N-type metal oxide semiconductor (N metal oxide semiconductor, NMOS) transistors.
  • the first transistor and the second transistor may also be other types of transistors, for example, they may be P-type metal oxide semiconductor (P metal oxide semiconductor, NMOS) transistors. This embodiment of the present application does not specifically limit it.
  • each memory block also includes: a plurality of amplifiers respectively connected to the plurality of first bit lines in one-to-one correspondence, and each amplifier in the plurality of amplifiers is used to read the correspondingly connected first bit line The received feedback information is used to indicate the data stored in the correspondingly connected storage unit.
  • each amplifier and its peripheral circuits together form a readout loop for outputting feedback information of the storage unit corresponding to the voltage control line connected to the amplifier, so as to read data in the storage unit.
  • each amplifier can judge whether the storage unit is in a high-resistance state or a low-resistance state by comparing the feedback information (such as voltage, current, capacitance, charge and discharge time) of the storage unit with a reference value, and then determine the The data stored in the storage unit.
  • the feedback information such as voltage, current, capacitance, charge and discharge time
  • an embodiment of the present application provides an electronic device, where the electronic device includes a processor and any one of the foregoing magnetic random access memories provided in the embodiments of the present application coupled with the processor.
  • the processor can call the software program stored in the magnetic random access memory to execute the corresponding method and realize the corresponding function of the electronic device.
  • FIG. 1 is a schematic structural diagram of a magnetic random access memory provided in an embodiment of the present application
  • FIG. 2 is a schematic structural diagram of another magnetic random access memory provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of another magnetic random access memory provided by an embodiment of the present application.
  • Fig. 4 is a schematic diagram of the leakage channel existing in the magnetic random access memory provided by the embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of another magnetic random access memory provided by an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of another magnetic random access memory provided by the embodiment of the present application.
  • Fig. 7 is a schematic diagram of the magnetic random access memory provided by the embodiment of the present application to prevent the leakage channel
  • FIG. 8 is a schematic structural diagram of another magnetic random access memory provided by an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of another magnetic random access memory provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of another magnetic random access memory provided by the embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of another magnetic random access memory provided by the embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of an electronic device provided by an embodiment of the present application.
  • Embodiments of the present application provide a magnetic random access memory and electronic equipment, which are used to increase the storage density of the magnetic random access memory.
  • the embodiment of the present application may be applied to the magnetic random access memory shown in FIG. 1 .
  • the MRAM includes a control circuit and at least one storage circuit.
  • each storage circuit includes a plurality of storage units, the storage unit is the smallest unit with data storage and read-write functions in the magnetic random access memory, and can be used to store a minimum information unit, that is, 1-bit data (such as 0 or 1 ), that is, a binary bit.
  • the control circuit is used to control the process of writing and reading data in the storage unit in the storage circuit. For example, when writing data, the control circuit selects the storage unit to write data, applies the corresponding voltage to the selected storage unit and passes Input the corresponding current to realize writing data in the selected memory cell. For another example, when reading data, the control circuit selects the memory cell to be read, and realizes from Read data from the selected storage unit.
  • the magnetic random access memory may include N storage blocks (i.e. Block): 10(1) to 10(N), where N is greater than 1 integer.
  • N storage blocks 10(1)-10(N) can be regarded as N storage circuits in FIG. 1 .
  • each memory block 10 (n) (n is any integer from 1 to N) includes a plurality of structural units (cell) 101 and a plurality of voltage control lines 102; each of the plurality of structural units 101
  • Each structural unit 101 includes a multilayer storage structure stacked in sequence (a three-layer storage structure is used as an example in FIG. 3 for illustration), and each layer of storage structure in the multilayer storage structure includes electrode lines 103 and electrodes arranged on the electrode lines 103.
  • Multiple memory cells 104 each memory cell 104 in the multiple memory cells 104 includes an MTJ, one end of each memory cell 104 is connected to the electrode line 103, and the other end is connected to one of the multiple voltage control lines 102 for voltage control Line 102 connects.
  • 2 and 3 both take the storage block 10(n) including 4 structural units 101 and each structural unit 101 including 9 storage units 104 as an example for schematic illustration.
  • the magnetic random access memory includes a plurality of memory blocks, in order to reduce the leakage path (sneak paths) between different memory blocks, the voltage control line in each memory block can be controlled separately, that is, the voltage in different memory blocks
  • the control lines are independent of each other. Therefore, in this application, for each memory block, referring to FIG. lines (BL0-BL8 are taken as an example in FIG. 3 for illustration), and each first bit line BLn among the plurality of first bit lines BLn is connected to the corresponding voltage control line 102 through a metal wire.
  • different storage blocks 10(n) operate independently through their respective bit lines during the write operation, thereby reducing the sneak paths between different storage blocks of the entire MRAM during data writing, thereby reducing the writing leakage work of the MRAM consumption.
  • the magnetic random access memory may include N memory blocks (i.e. Block): 10(1) ⁇ 10 (N), N is an integer greater than 0.
  • N storage blocks 10(1)-10(N) can be regarded as N storage circuits in FIG. 1 .
  • each storage block 10 (n) (n is any integer from 1 to N) can include a plurality of structural units (cell) 101 and a plurality of voltage control lines 102;
  • Each structural unit 101 in the structure may include a multi-layer storage structure stacked in sequence, and each layer of storage structure in the multi-layer storage structure includes an electrode line 103 and a plurality of memory cells 104 arranged on the electrode line 103, and the plurality of memory cells 104
  • Each storage unit 104 in the battery can include an MTJ and a unidirectional conduction selector D, one end of each storage unit 104 is connected to the electrode line 103, and the other end is connected to a voltage control line 102 in a plurality of voltage control lines 102
  • One end of the unidirectional conduction selector D is connected to one end of the magnetic tunnel junction MTJ, the other end of the unidirectional conduction selector D is connected to the voltage control line 102, and the other end of the magnetic tunnel junction MTJ is connected to the electrode line 103
  • the unidirectional conduction selector D can be a unidirectional conduction device.
  • Vth turn-on threshold voltage
  • the unidirectional conduction selector D is in an on-low resistance state
  • the voltage difference applied across the unidirectional conduction selector D is less than its turn-on threshold voltage Vth
  • the unidirectional conduction selector D is in a cut-off high resistance state.
  • the one-way conduction selector D when the voltage difference between the positive pole and the negative pole of the one-way conduction selector D is greater than Vth, the one-way conduction selector D is in a conduction low resistance state, and when the voltage difference between the positive pole and the negative pole of the one-way conduction selector D is less than At Vth, the one-way conduction selector D is in a cut-off high-resistance state.
  • Fig. 5 shows that the conduction current direction of the one-way conduction selector D is directed from the voltage control line 102 to the direction of the electrode line 103 as an example.
  • the negative pole of the one-way conduction selector D is connected to the MTJ, then the forward current direction of the one-way conduction selector D is from the voltage control line 102 to the electrode line 103, when the voltage between the voltage control line 102 and the electrode line 103
  • Vth turn-on threshold voltage
  • Vth>0 the one-way conduction selector D is in a turn-on low resistance state, and when the voltage difference between the voltage control line 102 and the electrode line 103 is less than the turn-on threshold voltage Vth (Vth>0)
  • Vth turn-on threshold voltage
  • Fig. 6 is illustrated by taking the conduction current direction of the unidirectional conduction selector D from the electrode line 103 to the direction of the voltage control line 102 as an example.
  • the negative pole of the selector D is connected to the voltage control line 102, then the forward current direction of the one-way conduction selector D is from the electrode line 103 to the voltage control line 102, when the voltage difference between the electrode line 103 and the voltage control line 102 is greater than
  • the threshold voltage Vth Vth>0
  • the one-way conduction selector D is in a conduction low resistance state, and when the voltage difference between the electrode line 103 and the voltage control line 102 is less than the threshold voltage Vth (Vth>0)
  • the one-way conduction selector D is in a cut-off high resistance state.
  • each memory cell 104a, 104b and 104c includes a MTJ and a unidirectional conduction selector D, therefore, in the channel of the storage unit 104b pointing to the storage unit 104a, the unidirectional conduction selector D in the storage unit 104a is in a cut-off state, and in the channel of the storage unit 104b pointing to the storage unit 104c In the above, the unidirectional conduction selector D in the storage unit 104c is in the cut-off state, so the sneak paths between different storage units 104 can be effectively limited, so that the write leakage power consumption of the MRAM can be better reduced.
  • the electrical characteristics, heat treatment temperature, and scalability of the unidirectional conduction selector need to match the MTJ, for example, to meet: a certain turn-on voltage/current (0-2V, ⁇ A), a higher rectification ratio, High durability (Endurance), operating speed in the order of nanoseconds, low heat treatment temperature, etc.
  • the unidirectional conduction selector in this application may be a unidirectional conduction diode, such as a Schottky diode or a PN junction diode, etc., which is not specifically limited herein.
  • the unidirectional conduction selector is a Schottky diode
  • the anode of the Schottky diode can point to the voltage control line or to the electrode line, which is not limited here.
  • the unidirectional conduction selector is a PN junction diode
  • the anode of the PN junction diode can point to the voltage control line or to the electrode line, which is not limited here.
  • the multiple memory blocks 10_n may be arranged in parallel along the direction of the electrode lines 103 .
  • the voltage control line 102 is in one-to-one correspondence with the storage unit 104, that is to say, each storage unit 104 has a voltage control line 102 corresponding to it, which is used to supply the storage unit 104 Apply voltage.
  • the multiple voltage control lines are parallel; the planes where the multiple structural units are located are parallel, and the plane where each structural unit is located is perpendicular to the multiple voltage control lines.
  • the xyz coordinate system is shown in the MRAM shown in FIG. 2 , FIG. 3 , FIG. 5 and FIG. 6 .
  • the voltage control lines are arranged in parallel along the x-axis;
  • the electrode lines in each memory block 10(n) are arranged in parallel along the y-axis, and a plurality of memory blocks 10(n) are arranged in parallel along the y-axis axes are arranged in parallel;
  • multi-layer memory structures are stacked sequentially along the z-axis direction.
  • the plane where each structural unit is located is perpendicular to the x-axis.
  • a storage unit is the smallest unit in the MRAM with data storage and read/write functions, and can be used to store a minimum information unit, that is, 1-bit data (such as 0 or 1), that is, a binary bit.
  • 1-bit data such as 0 or 1
  • a binary bit a minimum information unit
  • the storage of multiple binary bit data can be realized.
  • one storage unit is used to store one binary bit.
  • each MTJ may include a free layer, a barrier layer and a reference layer stacked in sequence.
  • the magnetic moment direction of the reference layer is fixed, and the magnetic moment direction of the free layer can be changed when data is written.
  • the barrier layer is used for produce tunnel magnetoresistance effect.
  • the free layer is connected to the electrode line, the reference layer is connected to the voltage control line, or the reference layer is connected to the voltage control line through a unidirectional conduction selector. That is to say, the free layer is close to the electrode line, the reference layer is farthest from the electrode line, and the barrier layer is located between the free layer and the reference layer.
  • the magnetic moment directions of the free layer and the reference layer can be in the xy plane, and can be perpendicular to xy plane, or at a certain oblique angle to the xy plane.
  • the magnetic moment directions of the free layer and the reference layer there is no specific limitation on the magnetic moment directions of the free layer and the reference layer, as long as the magnetic moment directions of the free layer and the reference layer are arranged in parallel or antiparallel.
  • the MRAM provided by the embodiment of the present application utilizes the SOT effect and the VCMA effect when writing data, and utilizes the tunnel magneto resistance (TMR) effect when reading data.
  • TMR tunnel magneto resistance
  • the principle of the SOT effect is: passing a current through the electrode wire will generate a spin-polarized current that diffuses upward (that is, to the positive direction of the z-axis) and enters the free layer of the MTJ.
  • a certain value critical switching current density
  • the magnetic moment of the free layer is flipped to realize data writing.
  • the principle of the VCMA effect is that applying a bias voltage across the MTJ can change the interface charge density between the MTJ free layer and the barrier layer, thereby changing the vertical anisotropy and coercive force of the free layer, thereby reducing the critical switching current density of the MTJ. . While using the VCMA effect to reduce the critical switching current density of the MTJ, a current is passed into the electrode line, and the magnetic moment in the free layer is reversed under the joint action of the SOT effect and the VCMA effect, and data writing is realized. This method can reduce the power consumption of data writing.
  • the electrode wires can be made of heavy metal materials, or other materials that can generate spin currents, and the electrode wires can also be called SOT electrode wires.
  • the voltage control line independently performs selective operations on the memory cells connected to it, for example, the first The bias voltage reduces the critical switching current density of the memory cells that need to write data.
  • a second bias voltage is applied to the voltage control line connected to the memory cells that do not need to write data, so as to increase (or not change) the critical switching current density of the non-written memory cells.
  • a write current is passed into the electrode line connected to the memory cell that needs to write data (different data can be written by passing current in different directions), resulting in upward (that is, to the positive direction of the z-axis) diffusion
  • the spin flow of the MTJ enters the free layer of the MTJ, so that data can be written in the memory cells that need to be written.
  • the principle of the TMR effect is: when the magnetic moments of the free layer of the MTJ and the reference layer are arranged in parallel, the MTJ is in a low-resistance state; when the magnetic moments of the free layer and the reference layer are arranged in antiparallel (that is, parallel and opposite), the MTJ is high resistance state.
  • High and low resistance represent two different data states, such as 0 or 1; different data can be read according to whether the MTJ is in a high resistance state or a low resistance state.
  • the MRAM when reading data from the MRAM, it is necessary to obtain feedback information stored in the storage unit that needs to read data through a readout loop (for example, including an amplifier) connected to the voltage control line.
  • the feedback information is used to indicate the data stored in the correspondingly connected storage unit.
  • the MTJ corresponding to the voltage control line connected to the amplifier is in a high-impedance state or a low-impedance state, and then judge whether the data stored in the MTJ is 0 or 1 .
  • the MTJ can have high resistance characteristics, such as the MTJ The resistance value is not less than 100K ⁇ , so that the resistance value of MTJ is much larger than that of the electrode wire, which can effectively prevent the writing current from flowing through the MTJ and reduce the impact of sneak paths on the accuracy of written data.
  • each memory block 10(n) in each memory block 10(n), all the electrode lines 103 in each structural unit 101 are connected in parallel through metal wires, so that the magnetic When writing or reading data in the random access memory, it is possible to apply read and write currents to all the electrode lines 103 in the structural unit 101 at the same time, thereby reducing the wiring space of the selected group lines in the peripheral circuit plane, and through less selected
  • the assembly wire realizes the addressing and access to the multi-layer storage structure in the magnetic random access memory.
  • the process of applying a voltage or passing a current on the electrode line can be realized by two transistors respectively connected to the two selection lines, one of which is the selection line
  • the line is connected to one end of the electrode line through a transistor, and the other group selection line is connected to the other end of the electrode line through another transistor.
  • the switching on and off of the two transistors is controlled by the word line. Applying a gate bias voltage to the two transistors on the word line makes the two transistors turn on, and applying different voltages on the two select lines, so as to apply a voltage to the electrode line or pass in a current.
  • each memory block 10(n) may also include: the first group selection line bl and the second group selection line sl; the first group selection line bl, the second group selection line
  • the group line sl and the plurality of voltage control lines 102 are parallel to each other; all the electrode lines 103 in each structural unit 101 are respectively connected in parallel through metal wires, and each structural unit 101 also includes a word line WL, a first transistor T1 and a second transistor T1. Two transistors T2.
  • the gates of the first transistor T1 and the second transistor T2 are respectively connected to the word line WL, and the word line WL can be used to provide the gate bias voltage for the first transistor T1 and the second transistor T2, so that the first transistor T1 and the second transistor T2
  • the second transistor T2 is turned on.
  • the source of the first transistor T1 is connected to the first group selection line bl
  • the drain of the second transistor T2 is connected to the second group selection line sl
  • the drain of the first transistor T1 is connected to the first end of the electrode line 103 through a metal wire.
  • the source of the second transistor T2 is connected to the second end of the electrode line 103 through a metal wire.
  • Applying different voltages on the first group selection line bl and the second group selection line sl, respectively, can cause current to flow through the electrode lines 103, that is, to provide parallel writing for memory cells 104 on all electrode lines 103 in a structural unit. into the current.
  • the different structural units 101 in each memory block 10(n) can share the first group selection line bl and the second group selection line sl, and the structural units 101 at the corresponding positions of different memory blocks 10(n) share the word Line WL.
  • the first group selection line bl and the second group selection line sl can be parallel to the voltage control line 102
  • the word line WL can be parallel to the electrode line 103.
  • the first group selection line b1, the second group selection line sl and the voltage control line 102 all extend along the x direction
  • the word line WL and the electrode line 103 all extend along the y direction.
  • the material of the metal wire is different from that of the electrode wire
  • the metal wire may be a low-resistance metal interconnection wire
  • the electrode wire may be a material with a large spin Hall effect.
  • the first transistor and the second transistor may be N-type metal oxide semiconductor (N metal oxide semiconductor, NMOS) transistors.
  • the first transistor and the second transistor may also be other types of transistors, for example, they may be P-type metal oxide semiconductor (P metal oxide semiconductor, NMOS) transistors. This embodiment of the present application does not specifically limit it.
  • the magnetic random access memory includes a plurality of storage blocks: 10(1)-10(N), and each storage block 10(n) includes a plurality of structural units 101, a plurality of voltage control lines 102, and A plurality of voltage control lines 102 are connected in one-to-one correspondence with a plurality of first bit lines BLn (in FIG. 3, n is equal to 0 to 8 as an example for illustration), the first group selection line bl and the second group selection line sl; The group selection line bl, the second group selection line sl and the plurality of voltage control lines 102 are parallel to each other; each of the plurality of first bit lines BLn is connected to the corresponding voltage control line 102 through a metal wire.
  • Each structural unit 101 in the plurality of structural units 101 includes a sequentially stacked multi-layer storage structure, a word line WL, a first transistor T1 and a second transistor T2, which are shared between different memory blocks 10(n) along the y direction. word line WL.
  • Each storage structure in the multilayer storage structure includes an electrode line 103 and a plurality of storage units 104 arranged on the electrode line 103, each storage unit 104 in the plurality of storage units 104 includes an MTJ, and each storage unit 104 One end is connected to the electrode line 103 , and the other end is connected to one voltage control line 102 among the plurality of voltage control lines 102 .
  • All the electrode lines 103 in each structural unit 101 are respectively connected in parallel through metal wires, the gates of the first transistor T1 and the second transistor T2 are respectively connected to the word line WL, the source of the first transistor T1 is connected to the first selection line b1 is connected, the drain of the second transistor T2 is connected to the second group selection line sl, the drain of the first transistor T1 is connected to the first end of the electrode line 103 through a metal wire, and the source of the second transistor T2 is connected to the first end of the electrode line 103 through a metal wire.
  • the second ends of the electrode wires 103 are connected.
  • the metal wire may be a low-resistance interconnection metal wire.
  • the corresponding voltage control line 102 and the first bit line BLn are different among different memory blocks 10(n).
  • different memory blocks 10(n) will not run at the same time during the write operation, which can reduce the number of memory blocks that perform read and write operations in parallel during the write operation, so as to reduce the sneak paths between the memory blocks, thereby reducing the writing of the magnetic random access memory. Leakage power consumption.
  • the process of writing data to the magnetic random access memory can be as follows:
  • the word line WL corresponding to the structural unit 101 to which the storage unit 104 of the data needs to be written belongs is respectively connected to the The gate bias voltage is applied to the first transistor T1 and the second transistor T2, so that the first transistor T1 and the second transistor T2 are turned on, and the write voltage is applied to the first selection line bl, and the second selection line sl Grounding, or grounding the first group selection line bl, applying a write voltage to the second group selection line sl; the first bit line BLn corresponding to the memory cell 104 that needs to write data is controlled to the voltage connected to the memory cell 104
  • the first bias voltage is applied to the line 102, and the other first bit line BLn applies the second bias voltage to the voltage control line 102 connected to the memory cell 104 that does not need to write data.
  • the first bias voltage and the second bias voltage not equal.
  • the first bias voltage is used to reduce (or not change) the critical switching current density of the memory cells 104 that need to write data
  • the second bias voltage is used to not change (or increase) the memory cells that do not need to write data.
  • the critical switching current density of 104 The values of the first bias voltage and the second bias voltage are different, and the specific values of the first bias voltage and the second bias voltage can be determined according to the specific structure and material parameters of the memory unit 104 . That is to say, when the voltage control line 102 applies the first bias voltage, data can be written into the memory cell 104 connected to the voltage control line 102; The memory cells 104 connected by the lines 102 are written with data.
  • the difference between the first bias voltage and the voltage of the electrode line 103 is a negative value, and the difference between the second bias voltage and the voltage of the electrode line 103 is a positive value or zero; or, the first bias voltage
  • the difference between the voltage of the second bias voltage and the electrode line 103 is a positive value, and the difference between the second bias voltage and the voltage of the electrode line 103 is a negative value or zero.
  • the current direction required in the electrode line 103 can be judged according to the data (0 or 1) to be written, and then determine whether to apply the write voltage or Apply a write voltage on the second selection line sl; at the same time, apply a first bias to the voltage control line 102 connected to the memory cell 104 through the first bit line BLn corresponding to the memory cell 104 that needs to write data Voltage, the second bias voltage is applied to the voltage control line 102 connected to the memory cell 104 through the first bit line BLn corresponding to the memory cell 104 that does not need to write data, so as to realize writing to a certain memory cell 104 data process.
  • the process of reading data from the magnetic random access memory can be as follows:
  • the data stored in all storage units 104 in a certain structural unit 101 in the storage block 10(n) can be read at one time.
  • the reading of data in the memory cell 104 utilizes the TMR effect.
  • the first transistor T1 and the The gate bias voltage is applied to the second transistor T2, and the first transistor T1 and the second transistor T2 are turned on;
  • the line sl applies a read voltage or a read current to the correspondingly connected memory cells 104, and grounds all the voltage control lines 102 in the memory block 10(n) to which the structural unit 101 to which data needs to be read belongs, and passes all the voltage control lines 102 to the ground.
  • the line 102 receives feedback information from the correspondingly connected storage unit 104 , where the feedback information is used to indicate the data stored in the correspondingly connected storage unit 104 .
  • a read voltage or a read current is applied to all the voltage control lines 102 in the memory block 10(n) to which the structural unit 101 to which data needs to be read belongs, and the first selected group line bl and the second selected group line sl ground to provide a ground return.
  • the feedback information of the storage unit 104 may be information such as the current and capacitance of the storage unit 104, and the information applied on each voltage control line 102 In the case of the same read voltage, when the storage unit 104 is in different resistance states, the feedback current or capacitance is different; when each voltage control line 102 applies a read current to the correspondingly connected storage unit 104, the feedback information of the storage unit 104 It may be information such as the voltage and capacitance of the storage unit 104.
  • the read current applied by each voltage control line 102 is the same, when the storage unit 104 is in a different resistance state, the feedback voltage or capacitance is different.
  • the storage block 10(n) may also include a plurality of amplifiers SA connected to the plurality of voltage control lines 102 in one-to-one correspondence, and each amplifier in the plurality of amplifiers is used to read the corresponding connection The feedback information received by the first bit line BLn.
  • each amplifier and its peripheral circuits together form a read loop for outputting feedback information of the storage unit 104 corresponding to the first bit line BLn connected to the amplifier, so as to read data in the storage unit 104 .
  • each amplifier can judge whether the storage unit 104 is in a high-impedance state or a low-impedance state by comparing the feedback information (such as voltage, current, capacitance, charging and discharging time) of the storage unit 104 with a reference value, and then The data stored in the storage unit 104 is determined.
  • the feedback information such as voltage, current, capacitance, charging and discharging time
  • the above-mentioned process of applying a voltage or passing a current on the first group selection line bl, the second selection line sl, and each first bit line BLn can be performed by the MRAM
  • the level control circuit configured in is controlled, and the level control circuit is used to provide the required voltage or current for the first selection line bl, the second selection line sl and each first bit line BLn.
  • the process of applying a voltage or passing a current on each first bit line BLn can also be controlled by the level control circuit, and the level control circuit is used for each first bit line BLn Bit line BLn provides the required voltage or current.
  • the MRAM may also include a row address decoding circuit and a column address decoding circuit, which are used to select the corresponding memory cell 104 through the word line WL and the bit line when writing or reading data.
  • the above-mentioned level control circuit can be based on the row address
  • the selection of the decoding circuit and the column address decoding circuit is used to judge the voltage or current that needs to be applied on the first selection line bl, the second selection line sl and each first bit line BLn, so as to realize the decoding of the row address decoding circuit and the column address
  • One or several storage units 104 selected by the circuit perform read and write operations.
  • control circuit the row address decoding circuit and the column address decoding circuit may be collectively referred to as a control circuit.
  • the six voltage control lines 102 of the first layer and the second layer can be drawn out from the right end of the memory block 10(n) through metal wires and connected to the plane where the peripheral circuit is located, respectively by 6 Controlled by the first bit lines BL0-BL5; the three voltage control lines on the third layer are led out from the left end of the memory block 10(n) through metal wires and connected to the plane where the peripheral circuit is located, respectively by the three first bit lines BL6 ⁇ BL8 control.
  • the first bit lines BL0-BL8 can be arranged around the storage block 10(n), not limited to the left and right ends in FIG.
  • All the first bit lines BL0-BL8 of the memory block 10(n) solve the problem of addressing different memory planes in the 3D MRAM solution.
  • the word line WL and the first bit line BLn are respectively connected to row and column address decoding circuits.
  • a gate bias voltage is applied to the word line WL connected to the structural unit 101 where the memory unit 104 where the data needs to be written is located, and the first transistor T1 and the second transistor T2 controlled by the word line WL are in a conductive state.
  • Another bias voltage is applied to the word line WL connected to other structural units 101 that do not need to write data, and the first transistor T1 and the second transistor T2 of other structural units 101 that do not need to write data are turned off.
  • the first transistor T1 and the second transistor T2 are turned off. Both the first group selection line sl and the second group selection line bl of the structural unit 101 that needs to read data are grounded. At the same time, if all the first bit lines BLn in the memory block 10(n) are connected to the read voltage or read current, only the memory unit 104 of the structural unit 101 that needs to read data will flow through the read current, so as to realize a read The feedback information of all storage units 104 in the structural unit 101 is selected.
  • this solution can store the memory cells in the vertical direction under the premise of ensuring the thermal stability of the storage cells.
  • the superposition of increases the areal storage density, thereby improving the storage density of the magnetic random access memory.
  • the corresponding voltage control lines and the first bit lines are different between different memory blocks. In this way, different memory blocks will not run at the same time during the write operation, thereby reducing the number of memory blocks running in parallel during the write operation, reducing the sneak paths between the memory blocks, and thereby reducing the write leakage power consumption of the MRAM.
  • the MRAM includes at least one storage block 10(n).
  • Each storage block 10(n) includes a plurality of structural units 101, a plurality of voltage control lines 102, a first group selection line bl and a second group selection line sl; the first group selection line bl, the second group selection line sl and Multiple voltage control lines 102 are parallel to each other, and different structural units 101 of the same memory block 10(n) share the first group selection line bl and the second group selection line sl.
  • Each structural unit 101 in the plurality of structural units 101 includes a sequentially stacked multi-layer storage structure, a word line WL, a first transistor T1 and a second transistor T2, which are shared between different memory blocks 10(n) along the y direction.
  • word line WL is shared between different memory blocks 10(n) along the y direction.
  • Each storage structure in the multi-layer storage structure includes an electrode line 103 and a plurality of memory cells 104 arranged on the electrode line 103, and each memory cell 104 in the plurality of memory cells 104 includes an MTJ and a unidirectional conduction selector D, one end of each memory cell 104 is connected to the electrode line 103, and the other end is connected to a voltage control line 102 in a plurality of voltage control lines 102; the negative pole of the unidirectional conduction selector D is connected to one end of the magnetic tunnel junction MTJ, The anode of the unidirectional conduction selector D is connected to the voltage control line 102 , and the other end of the magnetic tunnel junction MTJ is connected to the electrode line 103 .
  • All the electrode lines 103 in each structural unit 101 are respectively connected in parallel through metal wires, the gates of the first transistor T1 and the second transistor T2 are respectively connected to the word line WL, the source of the first transistor T1 is connected to the first selection line b1 is connected, the drain of the second transistor T2 is connected to the second group selection line sl, the drain of the first transistor T1 is connected to the first end of the electrode line 103 through a metal wire, and the source of the second transistor T2 is connected to the first end of the electrode line 103 through a metal wire.
  • the second ends of the electrode wires 103 are connected.
  • the material of the metal wire may be a low-resistance interconnected metal material
  • the electrode wire may be a material with a large spin Hall effect.
  • the process of writing data to the magnetic random access memory can be as follows:
  • the connected first transistor T1 and the second transistor T2 apply a gate bias voltage to turn on the first transistor T1 and the second transistor T2, and apply another word line WL connected to the structural unit 101 that does not need to write data.
  • a bias voltage, other first transistor T1 and second transistor T2 that do not need to be written into the data structure unit 101 are turned off.
  • the first bit line BLn corresponding to the memory cell 104 for inputting data applies the first bias voltage to the voltage control line 102 connected to the memory cell 104, and the other first bit lines BLn are connected to the memory cell 104 that does not need to write data.
  • the voltage control line 102 applies a second bias voltage, and the first bias voltage is not equal to the second bias voltage.
  • the free layer and the reference layer are in-plane magnetized CoFeB materials, and the barrier layer is MgO. Then the first bias voltage is used to make the voltage difference between the voltage control line 102 and the electrode line 103 smaller than that of the unidirectional conduction selector
  • the turn-on threshold voltage of D, the one-way conduction selector D is in the non-conduction high resistance state, the voltage difference between the two ends of the MTJ is small, the VCMA effect is weak, and the corresponding critical switching current density of the MTJ is basically unchanged.
  • the second bias voltage is used to make the voltage difference between the voltage control line 102 and the electrode line 103 greater than the turn-on threshold voltage of the one-way conduction selector D, and the one-way conduction selector D is in a conduction low-resistance state.
  • the critical switching current density of the memory cells 104 that do not need to be written with data increases.
  • the barrier layer is MgO.
  • the first bias voltage is used to make the voltage difference between the voltage control line 102 and the electrode line 103 greater than the turn-on threshold voltage of the unidirectional conduction selector D, and the unidirectional conduction selector D is in a conduction low resistance state, and the VCMA effect makes it necessary to The critical switching current density of the memory cell 104 for writing data is reduced, and the second bias voltage is used to make the voltage difference between the voltage control line 102 and the electrode line 103 smaller than the turn-on threshold voltage of the unidirectional conduction selector D.
  • the pass selector D is in the cut-off high resistance state, the VCMA effect is very weak, the vertical anisotropy of the free layer of the storage unit 104 that does not need to write data is basically unchanged, and the corresponding critical switching current density is unchanged.
  • passing an appropriate current into the SOT electrode line can cause the free layer of the memory cell under the first bias voltage to flip, while the memory cell under the second bias voltage does not flip.
  • the values of the first bias voltage and the second bias voltage are different, and the specific values of the first bias voltage and the second bias voltage can be determined according to the specific structure and material parameters of the memory unit 104 . That is to say, when the voltage control line 102 applies the first bias voltage, data can be written into the memory cell 104 connected to the voltage control line 102; The memory cells 104 connected by the lines 102 are written with data.
  • the current direction required in the electrode line 103 can be judged according to the data (0 or 1) to be written, and then determine whether to apply the write voltage or Apply a write voltage on the second selection line sl; at the same time, apply a first bias to the voltage control line 102 connected to the memory cell 104 through the first bit line BLn corresponding to the memory cell 104 that needs to write data Voltage, the second bias voltage is applied to the voltage control line 102 connected to the memory cell 104 through the first bit line BLn corresponding to the memory cell 104 that does not need to write data, so as to realize writing to a certain memory cell 104 data process.
  • the process of reading data from the magnetic random access memory can be as follows:
  • the data stored in all storage units 104 in a certain structural unit 101 in the storage block 10(n) can be read at one time.
  • the reading of data in the memory cell 104 utilizes the TMR effect.
  • the first transistor T1 and the The gate bias voltage is applied to the second transistor T2, and the first transistor T1 and the second transistor T2 are turned on.
  • the feedback information of the storage unit 104 may be information such as the current and capacitance of the storage unit 104, and the information applied on each voltage control line 102 In the case of the same read voltage, when the storage unit 104 is in different resistance states, the feedback current or capacitance is different; when each voltage control line 102 applies a read current to the correspondingly connected storage unit 104, the feedback information of the storage unit 104 It may be information such as the voltage and capacitance of the storage unit 104.
  • the read current applied by each voltage control line 102 is the same, when the storage unit 104 is in a different resistance state, the feedback voltage or capacitance is different.
  • the storage block 10(n) may also include a plurality of amplifiers SA connected to the plurality of voltage control lines 102 in one-to-one correspondence, and each amplifier in the plurality of amplifiers is used to read Feedback information received.
  • each amplifier and its peripheral circuits jointly form a readout circuit for outputting feedback information of the storage unit 104 corresponding to the voltage control line 102 connected to the amplifier, thereby reading data in the storage unit 104 .
  • each amplifier can judge whether the storage unit 104 is in a high-impedance state or a low-impedance state by comparing the feedback information (such as voltage, current, capacitance, charging and discharging time) of the storage unit 104 with a reference value, and then The data stored in the storage unit 104 is determined.
  • the feedback information such as voltage, current, capacitance, charging and discharging time
  • the above-mentioned process of applying a voltage or passing a current on the first group selection line bl, the second selection line sl and each voltage control line 102 can be performed by the MRAM
  • the configured level control circuit is controlled, and the level control circuit is used to provide the required voltage or current for the first group selection line bl, the second group selection line sl and each voltage control line 102 .
  • the process of applying a voltage or passing a current to each voltage control line 102 can also be controlled by the level control circuit, and the level control circuit is used for each voltage control line 102. 102 provides the required voltage or current.
  • the MRAM may also include a row address decoding circuit and a column address decoding circuit, which are used to select the corresponding memory cell 104 through the word line WL and the bit line when writing or reading data.
  • the above-mentioned level control circuit can be based on the row address
  • the selection of the decoding circuit and the column address decoding circuit determines the voltage or current that needs to be applied on the first group selection line bl, the second group selection line sl and each voltage control line 102, so as to realize the row address decoding circuit and the column address decoding circuit
  • the selected one or several storage units 104 perform read and write operations.
  • control circuit the row address decoding circuit and the column address decoding circuit may be collectively referred to as a control circuit.
  • each memory cell 104 includes an MTJ and a unidirectional conduction selector D, when there is a voltage difference between two adjacent memory cells 104, there is always a single cell in one memory cell 104.
  • the conduction selector D is in the reverse cut-off state, so it can effectively limit the sneak path between different storage units 104, so that the write leakage power consumption of the MRAM can be better reduced.
  • the voltage control lines corresponding to different memory blocks 10(n) may be different or the same, which is not limited herein.
  • each memory block 10(n) further includes: multiple There are one first bit line BLn (in FIG. 9 ).
  • n is equal to 0 to 8 for illustration
  • each bit line BLn in the plurality of first bit lines BLn is connected to the corresponding voltage control line 102 through a metal wire.
  • the amplifiers SA corresponding to each voltage control line 102 are connected to the voltage control line 102 through the first bit line BLn, that is, one end of the first bit line BLn is connected to the voltage control line 102.
  • the other end of the first bit line BLn is connected to the amplifier SA.
  • the six voltage control lines 102 of the first layer and the second layer can be drawn from the right end of the memory block 10(n) through metal wires and connected to the The planes are respectively controlled by six first bit lines BL0-BL5; the three voltage control lines 102 of the third layer are led out from the left end of the memory block 10(n) through metal wires and connected to the plane where the peripheral circuits are located, and are respectively controlled by Three first bit lines BL6-BL8 control.
  • the first bit lines BL0-BL8 can be arranged around the storage block 10(n), not limited to the left and right ends in FIG.
  • All the first bit lines BL0-BL8 of the storage block 10(n) solve the problem of addressing different storage planes in the 3D MRAM scheme.
  • the word line WL and the first bit line BLn are respectively connected to row and column address decoding circuits.
  • a gate bias voltage is applied to the word line WL connected to the structural unit 101 where the memory unit 104 where the data needs to be written is located, and the first transistor T1 and the second transistor T2 controlled by the word line WL are in a conducting state;
  • Another bias voltage is applied to the word line WL connected to other structural units 101 that do not need to write data, so that the connected first transistor T1 and second transistor T2 are in an off state.
  • the feedback information in all memory cells 104 in the selected structural unit 101 is read once, that is, the gate bias voltage is applied to the word line WL connected to the structural unit 101 that needs to read data, and the word line WL controls
  • the first transistor T1 and the second transistor T2 are in the conduction state, and another bias voltage is applied to the word line WL connected to other structural units 101 that do not need to read data, so that the connected first transistor T1 and the second transistor T2 is off.
  • this solution can store the memory cells in the vertical direction under the premise of ensuring the thermal stability of the storage cells.
  • the superposition of increases the areal storage density, thereby improving the storage density of the magnetic random access memory.
  • each memory cell includes an MTJ and a unidirectional conduction selector, when there is a voltage difference between any two memory cells to form a leakage channel, there is always a single MTJ in one memory cell.
  • the conduction selector is in the reverse cut-off state, so it can effectively limit the sneak paths between different memory cells, thereby reducing the write leakage power consumption of the MRAM.
  • the MRAM includes at least one memory block (n).
  • Each storage block 10(n) includes a plurality of structural units 101, a plurality of voltage control lines 102, a first group selection line bl and a second group selection line sl; the first group selection line bl, the second group selection line sl and Multiple voltage control lines 102 are parallel to each other, and different structural units 101 of the same memory block 10(n) share the first group selection line bl and the second group selection line sl.
  • Each structural unit 101 in the plurality of structural units 101 includes a sequentially stacked multi-layer storage structure, a word line WL, a first transistor T1 and a second transistor T2, which are shared between different memory blocks 10(n) along the y direction.
  • word line WL is shared between different memory blocks 10(n) along the y direction.
  • Each storage structure in the multi-layer storage structure includes an electrode line 103 and a plurality of memory cells 104 arranged on the electrode line 103, and each memory cell 104 in the plurality of memory cells 104 includes an MTJ and a unidirectional conduction selector D, one end of each memory cell 104 is connected to the electrode line 103, and the other end is connected to a voltage control line 102 in a plurality of voltage control lines 102; the positive pole of the unidirectional conduction selector D is connected to one end of the magnetic tunnel junction MTJ, The negative pole of the unidirectional conduction selector D is connected to the voltage control line 102 , and the other end of the magnetic tunnel junction MTJ is connected to the electrode line 103 .
  • All the electrode lines 103 in each structural unit 101 are respectively connected in parallel through metal wires, the gates of the first transistor T1 and the second transistor T2 are respectively connected to the word line WL, the source of the first transistor T1 is connected to the first selection line b1 is connected, the drain of the second transistor T2 is connected to the second group selection line sl, the drain of the first transistor T1 is connected to the first end of the electrode line 103 through a metal wire, and the source of the second transistor T2 is connected to the first end of the electrode line 103 through a metal wire.
  • the second ends of the electrode wires 103 are connected.
  • the material of the metal wire may be a low-resistance interconnected metal material
  • the electrode wire may be a material with a large spin Hall effect.
  • the process of writing data to the magnetic random access memory can be as follows:
  • the word line WL corresponding to the structural unit 101 to which the storage unit 104 to which data needs to be written belongs to its respective
  • the connected first transistor T1 and the second transistor T2 apply a gate bias voltage to turn on the first transistor T1 and the second transistor T2, apply a write voltage to the first selection line bl, and ground the second selection line sl , or the first group selection line bl is grounded, and the second selection line sl applies a write voltage;
  • the first bit line BLn corresponding to the memory cell 104 that needs to write data applies to the voltage control line 102 connected to the memory cell 104
  • the first bias voltage, the other first bit line BLn applies the second bias voltage to the voltage control line 102 connected to the memory cell 104 that does not need to write data, and the first bias voltage is not equal to the second bias voltage.
  • the barrier layer is MgO.
  • the first bias voltage is used to make the voltage difference between the electrode line 103 and the voltage control line 102 greater than the turn-on threshold voltage of the one-way conduction selector D, and the one-way conduction selector D is in a conduction low resistance state, and data needs to be written
  • the critical switching current density of the memory cell 104 becomes smaller, and the second bias voltage is used to make the voltage difference between the electrode line 103 and the voltage control line 102 smaller than the turn-on threshold voltage of the unidirectional conduction selector D, and the unidirectional conduction selector D is in the cut-off high resistance state, the VCMA effect is very weak, the vertical anisotropy of the free layer of the memory cell 104 not written with data is basically unchanged, and the corresponding critical switching current density is unchanged.
  • the first bias voltage is used to make the voltage difference between the electrode line 103 and the voltage control line 102 less than the turn-on threshold voltage of the unidirectional conduction selector D, and the unidirectional conduction selection
  • the device D is in a cut-off high-resistance state, and the VCMA effect is weak, so that the critical switching current density of the free layer of the memory cell 104 that needs to be written into data remains unchanged
  • the second bias voltage is used to make the voltage between the electrode line 103 and the voltage control line 102
  • the voltage difference is greater than the turn-on threshold voltage of the unidirectional conduction selector D, the unidirectional conduction selector D is in a conduction low resistance state, the vertical anisotropy of the free layer of the non-writing unit is enhanced, and the critical switching current density becomes larger.
  • passing an appropriate current into the SOT electrode line can cause the free layer of the memory cell under the first bias voltage to flip, while the memory cell
  • the values of the first bias voltage and the second bias voltage are different, and the specific values of the first bias voltage and the second bias voltage can be determined according to the specific structure and material parameters of the memory unit 104 . That is to say, when the voltage control line 102 applies the first bias voltage, data can be written into the memory cell 104 connected to the voltage control line 102; The memory cells 104 connected by the lines 102 are written with data.
  • the current direction required in the electrode line 103 can be judged according to the data (0 or 1) to be written, and then determine whether to apply the write voltage or Apply a write voltage on the second selection line sl; at the same time, apply a first bias to the voltage control line 102 connected to the memory cell 104 through the first bit line BLn corresponding to the memory cell 104 that needs to write data Voltage, the second bias voltage is applied to the voltage control line 102 connected to the memory cell 104 through the first bit line BLn corresponding to the memory cell 104 that does not need to write data, so as to realize writing to a certain memory cell 104 data process.
  • the process of reading data from the magnetic random access memory can be as follows:
  • the data stored in all storage units 104 in a certain structural unit 101 in the storage block 10(n) can be read at one time.
  • the reading of data in the memory cell 104 utilizes the TMR effect.
  • the first transistor T1 and the The gate bias voltage is applied to the second transistor T2, and the first transistor T1 and the second transistor T2 are turned on.
  • the first group selection line bl and the second group selection line s1 in the storage block 10 (n) to which the data structure unit 101 belongs apply a read voltage or a read current, and make the data structure unit 101 that needs to be read belong to All voltage control lines 102 in the storage block 10(n) are grounded, and receive feedback information from correspondingly connected storage units 104 via all voltage control lines 102 , the feedback information being used to indicate data stored in the correspondingly connected storage units 104 .
  • the feedback information of the storage unit 104 may be the current of the storage unit 104, Capacitance and other information, in the case of the same reading voltage, when the storage unit 104 is in different resistance states, the feedback current or capacitance is different;
  • the feedback information of the storage unit 104 may be information such as the voltage and capacitance of the storage unit 104.
  • the storage block 10(n) may also include a plurality of amplifiers SA connected to the plurality of voltage control lines 102 in one-to-one correspondence, and each amplifier in the plurality of amplifiers is used to read Feedback information received.
  • each amplifier and its peripheral circuits together form a readout loop for outputting feedback information of the storage unit 104 corresponding to the voltage control line 102 connected to the amplifier, thereby reading data in the storage unit 104 .
  • each amplifier can judge whether the storage unit 104 is in a high-impedance state or a low-impedance state by comparing the feedback information (such as voltage, current, capacitance, charging and discharging time) of the storage unit 104 with a reference value, and then The data stored in the storage unit 104 is determined.
  • the feedback information such as voltage, current, capacitance, charging and discharging time
  • the above-mentioned process of applying a voltage or passing a current on the first group selection line bl, the second selection line sl and each voltage control line 102 can be performed by the MRAM
  • the configured level control circuit is controlled, and the level control circuit is used to provide the required voltage or current for the first group selection line bl, the second group selection line sl and each voltage control line 102 .
  • the process of applying a voltage or passing a current to each voltage control line 102 can also be controlled by the level control circuit, and the level control circuit is used for each voltage control line 102. 102 provides the required voltage or current.
  • the MRAM may also include a row address decoding circuit and a column address decoding circuit, which are used to select the corresponding memory cell 104 through the word line WL and the bit line when writing or reading data.
  • the above-mentioned level control circuit can be based on the row address
  • the selection of the decoding circuit and the column address decoding circuit determines the voltage or current that needs to be applied on the first group selection line bl, the second group selection line sl and each voltage control line 102, so as to realize the row address decoding circuit and the column address decoding circuit
  • the selected one or several storage units 104 perform read and write operations.
  • control circuit the row address decoding circuit and the column address decoding circuit may be collectively referred to as a control circuit.
  • each memory cell 104 includes an MTJ and a unidirectional conduction selector D, when there is a voltage difference between two adjacent memory cells 104, there is always a single cell in one memory cell 104.
  • the conduction selector D is in the reverse cut-off state, so the sneak paths between different storage units 104 can be effectively restricted. Therefore, the write leakage power consumption of the MRAM can be better reduced.
  • the voltage control lines corresponding to different memory blocks 10(n) may be different or the same, which is not limited herein.
  • each memory block 10(n) further includes: multiple There are one first bit line BLn (in FIG. 11 ).
  • each bit line BLn in the plurality of first bit lines BLn is connected to the corresponding voltage control line 102 through a metal wire.
  • different storage blocks 10(n) will not run simultaneously during the write operation, so that the total leakage power consumption of the entire MRAM can be reduced.
  • the amplifiers SA corresponding to each voltage control line 102 are connected to the voltage control line 102 through the first bit line BLn, that is, one end of the first bit line BLn is connected to the voltage control line 102.
  • the other end of the first bit line BLn is connected to the amplifier SA.
  • the six voltage control lines 102 of the first layer and the second layer can be drawn from the right end of the memory block 10(n) through metal wires and connected to the The planes are respectively controlled by six first bit lines BL0-BL5; the three voltage control lines 102 of the third layer are led out from the left end of the memory block 10(n) through metal wires and connected to the plane where the peripheral circuits are located, and are respectively controlled by Three first bit lines BL6-BL8 control.
  • the first bit lines BL0-BL8 can be arranged around the storage block, not limited to the left and right ends in FIG.
  • All the first bit lines BL0-BL8 solve the problem of addressing different storage planes in the 3D MRAM scheme.
  • the word line WL and the first bit line BLn are respectively connected to row and column address decoding circuits.
  • a gate bias voltage is applied to the word line WL connected to the structural unit 101 where the memory unit 104 where the data needs to be written is located, and the first transistor T1 and the second transistor T2 controlled by the word line WL are in a conductive state.
  • Another bias voltage is applied to the word line WL connected to other structural units 101 that do not need to write data, so that the connected first transistor T1 and second transistor T2 are in an off state.
  • the feedback information in all memory cells 104 in the selected structural unit 101 is read once, that is, the gate bias voltage is applied to the word line WL connected to the structural unit 101 that needs to read data, and the word line WL controls
  • the first transistor T1 and the second transistor T2 are in the conduction state, and another bias voltage is applied to the word line WL connected to other structural units 101 that do not need to read data, so that the connected first transistor T1 and the second transistor T2 is off.
  • this solution can store the memory cells in the vertical direction under the premise of ensuring the thermal stability of the storage cells.
  • the superposition of increases the areal storage density, thereby improving the storage density of the magnetic random access memory.
  • each memory cell includes an MTJ and a unidirectional conduction selector, when there is a voltage difference between any two memory cells to form a leakage channel, there is always a single MTJ in one memory cell.
  • the conduction selector is in the reverse cut-off state, so it can effectively limit the sneak paths between different memory cells, thereby reducing the write leakage power consumption of the MRAM.
  • the number of storage blocks included in the magnetic random access memory provided by the embodiment of the present application, the number of structural units included in each storage block, the number of layers of the storage structure included in each structural unit, and The number of memory cells included on each electrode line is not specifically limited. Since the voltage control lines are in one-to-one correspondence with the memory cells, in the examples shown in Fig. 3, Fig. 8 to Fig. 11, the number of voltage control lines connected to the memory cells in each layer of memory structure is also three. In practical applications , the number of voltage control lines connected to the memory cells varies with the number of memory cells.
  • the embodiment of the present application also provides an electronic device.
  • the electronic device includes a processor 1001 and an MRAM 1002 coupled to the processor 1001 .
  • the MRAM 1002 may be the MRAM shown in FIG. 1 .
  • the processor 1001 may call the software program stored in the MRAM 1002 to execute a corresponding method and realize a corresponding function of the electronic device.

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Abstract

一种磁性随机存储器及电子设备，用以提高磁性随机存储器的存储密度。包括N个存储块（10(n)），存储块包括多个结构单元（101）以及多个电压控制线（102）；每个结构单元包括依次堆叠的多层存储结构，每层存储结构包括电极线（103）以及设置于电极线上的多个存储单元（104），每个存储单元的一端与电极线连接，另一端与多个电压控制线中的一个电压控制线连接。每个存储单元包括一个磁性隧道结和一个单向导通选择器，以通过降低存储单元之间的sneak paths来降低漏电功耗。或者，每个存储单元包括一个磁性隧道结，每一存储块还包括分别与多个电压控制线一一对应连接的多个第一位线（BLn），每一个位线通过金属导线与对应的电压控制线连接，以通过降低存储块之间的sneak paths来降低漏电功耗。

Description

一种磁性随机存储器及电子设备 技术领域
本申请涉及存储技术领域，尤其涉及一种磁性随机存储器及电子设备。
背景技术
信息技术的发展对存储介质提出了更高要求，相比于传统的半导体存储技术，以磁性隧道结(magnetic tunnel junction，MTJ)为存储单元的磁性随机存储器(magnetic random access memory，MRAM)由于同时具有很多优异的特性，例如：读写速度快、低功耗、读写次数多、耐辐射等，被认为是具有广阔应用前景的高密度存储器。
MRAM的核心存储单元是MTJ，每个MTJ包括自由层、势垒层和参考层。在MTJ中写入数据时，可以通过改变自由层的磁矩方向(即控制MTJ自由层和参考层的磁矩平行排列或反平行排列)写入不同的数据。从MTJ中读取数据时，可以通过判断MTJ的高低阻态来实现。
现有技术中，MRAM的存储阵列通常是二维(2 dimensions，2D)的。为了提高MRAM的存储密度，一般是通过不断缩小MTJ的尺寸和间距，从而增加单位面积内的存储单元个数。这种方式虽然可以在一定程度上提高MRAM的存储密度，但是当MTJ的尺寸缩小到一定程度时，MTJ的热稳定性就会下降，导致存储数据的可靠性降低，进而导致MRAM的存储密度较低。
发明内容
本申请实施例提供了一种磁性随机存储器及电子设备，用以提高磁性随机存储器的存储密度。
第一方面，本申请实施例提供一种磁性随机存储器，包括N个存储块，N为大于0的整数；每个存储块可以包括多个结构单元(cell)以及多个电压控制线；多个结构单元中的每个结构单元可以包括依次堆叠的多层存储结构，多层存储结构中的每层存储结构包括电极线以及设置于电极线上的多个存储单元，多个存储单元中的每个存储单元可以包括一个MTJ和一个单向导通选择器，每个存储单元的一端与电极线连接，另一端与多个电压控制线中的一个电压控制线连接；单向导通选择器的一端与磁性隧道结MTJ的一端连接，单向导通选择器的另一端与电压控制线连接，磁性隧道结MTJ的另一端与电极线连接。
采用本申请实施例提供的磁性随机存储器，由于存储阵列是3D的，该方案相比现有技术中的2D阵列，可以在保证存储单元的热稳定的前提下，通过垂直方向存储单元的叠加增加面存储密度，进而提高磁性随机存储器的存储密度。此外，在该实施例中，由于每个存储单元包括一个MTJ和一个单向导通选择器，因此，在任意两个存储单元之间有电压差形成漏电通道时，总有一个存储单元中的单向导通选择器是处于反向截止状态，因此可 以有效限制不同存储单元之间的sneak paths，从而降低磁性随机存储器的写入漏电功耗。
需要说明的是，单向导通选择器可以为单向导通器件，当施加在单向导通选择器的两端的电压差大于其开启阈值电压Vth(Vth＞0)时，单向导通选择器处于导通低电阻态，当施加在单向导通选择器两端的电压差小于其开启阈值电压Vth时，单向导通选择器处于截止高电阻态。例如，当单向导通选择器的正极和负极之间的电压差大于Vth时，单向导通选择器处于导通低电阻态，当单向导通选择器的正极和负极的电压差小于Vth时，单向导通选择器处于截止高电阻态。
具体地，单向导通选择器的正极可以与电压控制线连接，单向导通选择器的负极可以与MTJ连接，则单向导通选择器的正向电流方向为从电压控制线到电极线，当电压控制线与电极线之间的电压差大于Vth时，单向导通选择器处于导通低电阻态，当电压控制线与电极线之间的电压差小于Vth时，单向导通选择器处于截止高电阻态。
或者，单向导通选择器的正极可以与MTJ连接，单向导通选择器的负极可以与电压控制线连接，则单向导通选择器的正向电流方向为从电极线到电压控制线，当电极线与电压控制线之间的电压差大于Vth时，单向导通选择器处于导通低电阻态，当电极线与电压控制线之间的电压差小于Vth时，单向导通选择器处于截止高电阻态。
在具体实施时，单向导通选择器的电学特性、热处理温度以及可微缩性等需要与MTJ相匹配，例如满足：一定的开启电压/电流(0～2V，μA)，较高的整流比，耐久性(Endurance)高，操作速度在纳秒量级，热处理温度低等。
示例性的，本申请中单向导通选择器可以为单向导通二极管，例如肖特基二极管或者PN结二极管等，在此不作具体限定。当单向导通选择器为肖特基二极管时，肖特基二极管的正极可以指向电压控制线，也可以指向电极线，在此不作限定。同理，当单向导通选择器为PN结二极管时，PN结二极管的正极可以指向电压控制线，也可以指向电极线，在此不作限定。
在具体实施时，每个MTJ可以包括依次堆叠的自由层、势垒层和参考层。其中，参考层的磁矩方向固定，自由层的磁矩方向可以在数据写入时发生改变，自由层与参考层的磁矩呈平行或反平行排列时对应不同的数据，势垒层用于产生隧道磁电阻效应。具体地，本申请中，自由层与电极线连接，参考层通过单向导通选择器与电压控制线连接。也就是说，自由层靠近电极线，参考层与该电极线距离最远，势垒层位于自由层和参考层之间。
本申请实施例中对自由层和参考层的磁矩方向不做具体限定，只要自由层和参考层的磁矩方向平行排列或反平行排列即可。
可选地，在每个存储块中，多个电压控制线平行；多个结构单元所在的平面平行，且每个结构单元所在的平面与多个电压控制线垂直。
在磁性随机存储器中，在各存储块中，每个结构单元中的所有电极线分别通过金属导线并联连接，从而在向磁性随机存储器中写入数据或者读取数据时，可以实现同时在结构单元中的所有电极线上施加读写电流，从而减少选组线在外围电路平面的排线空间，通过较少的选组线实现对磁性随机存储器中多层存储结构的寻址和访问。
进一步地，为了实现磁性随机存储器中数据的写入和读取，在电极线上施加电压或通入电流的过程可以由分别与两个选组线所连接的两个晶体管实现，其中一个选组线通过一个晶体管与电极线的一端连接，另一个选组线通过另一个晶体管与电极线的另一端连接。两个晶体管的导通和关断由字线控制。在字线上分别向两个晶体管施加栅极偏置电压使得 两个晶体管导通，并在两个选组线上施加不同的电压，可以实现向电极线施加电压或通入电流。
例如，每一存储块还可以包括：第一选组线和第二选组线；第一选组线、第二选组线以及多个电压控制线之间相互平行；每个结构单元中的所有电极线分别通过金属导线并联连接，每个结构单元还包括字线、第一晶体管和第二晶体管。其中，第一晶体管和第二晶体管的栅极分别与字线连接，字线可用于为第一晶体管和第二晶体管提供栅极偏置电压，以使得第一晶体管和第二晶体管导通。第一晶体管的源极与第一选组线连接，第二晶体管的漏极与第二选组线连接，第一晶体管的漏极通过金属导线与电极线的第一端连接，第二晶体管的源极通过金属导线与电极线的第二端连接。分别在第一选组线和第二选组线上施加不同的电压，可以使得电极线中有电流通过，即为一个结构单元中的所有电极线上的存储单元并行提供写入电流。
在本申请中，每一存储块中的不同结构单元可以共用第一选组线和第二选组线，不同存储块对应位置的结构单元共用字线。其中，第一选组线和第二选组线可以与电压控制线平行，字线可以与电极线平行。
其中，金属导线的材料与电极线的材料不同，金属导线可为低电阻的金属互联线，电极线可为具有较大自旋霍尔效应的材料。第一晶体管和第二晶体管可以是N型金属氧化物半导体(N metal oxide semiconductor，NMOS)晶体管。当然，第一晶体管和第二晶体管也可以是其他类型的晶体管，例如可以是P型金属氧化物半导体(P metal oxide semiconductor，NMOS)晶体管。本申请实施例对此不做具体限定。
在本申请中，当磁性随机存储器中包括多个存储块时，不同存储块对应的电压控制线可以是不同的，也可以是相同，在此不作限定。
为了进一步降低磁性随机存储器的写入漏电功耗，当磁性随机存储器中包括多个存储块时，可以通过减小一次写操作过程中同时工作的存储块的数量，来减少不同存储块之间的sneak paths，从而减小写操作时整个磁性随机存储器的漏电功耗。为了减小一次写操作过程中同时工作的存储块的数量，可以单独控制每个存储块中的电压控制线，即不同存储块中的电压控制线是相互独立的。示例性的，在本申请中，针对每个存储块，每一存储块还包括：分别与多个电压控制线一一对应连接的多个第一位线，多个第一位线中每一个位线通过金属导线与对应的电压控制线连接。这样写操作时不同存储块不会同时运行，从而可以降低整个磁性随机存储器的漏电功耗。
此外，磁性随机存储器中，每一存储块还包括：分别与多个第一位线一一对应连接的多个放大器，多个放大器中的每个放大器用于读取对应连接的第一位线所接收的反馈信息，所述反馈信息用于指示对应连接的所述存储单元中存储的数据。
其中，每个放大器及其外围电路等共同组成读出回路，用于输出放大器所连接的电压控制线对应的存储单元的反馈信息，从而读取存储单元中的数据。
具体地，每个放大器可以通过将存储单元的反馈信息(例如电压、电流、电容量、充放电时间)与参考值做比较，来判断该存储单元处于高阻态还是低阻态，进而确定该存储单元中存储的数据。
第二方面，本申请实施例提供一种磁性随机存储器，包括N个存储块，N为大于1的整数；每个存储块包括多个结构单元(cell)以及多个电压控制线；多个结构单元中的每个结构单元包括依次堆叠的多层存储结构，多层存储结构中的每层存储结构包括电极线以及 设置于电极线上的多个存储单元，多个存储单元中的每个存储单元中包括一个MTJ，每个存储单元的一端与电极线连接，另一端与多个电压控制线中的一个电压控制线连接。针对每个存储块，存储块还可以包括与多个电压控制线一一对应连接的多个第一位线，多个第一位线中每一个第一位线通过金属导线与对应的电压控制线连接。
本申请实施例提供的磁性随机存储器，由于存储阵列是3D的，该方案相比现有技术中的2D阵列，可以在保证存储单元的热稳定的前提下，通过垂直方向存储单元的叠加增加面存储密度，进而提高磁性随机存储器的存储密度。此外，由于不同的存储块之间，对应的电压控制线和第一位线均是不同的。这样写操作时不同存储块不会同时运行，从而可以降低写操作时并行运行的存储块的数量，减少存储块之间的sneak paths，进而降低磁性随机存储器的写入漏电功耗。
在具体实施时，每个MTJ可以包括依次堆叠的自由层、势垒层和参考层。其中，参考层的磁矩方向固定，自由层的磁矩方向可以在数据写入时发生改变，自由层与参考层的磁矩呈平行或反平行排列时对应不同的数据，势垒层用于产生隧道磁电阻效应。具体地，本申请中，自由层与电极线连接，参考层与电压控制线连接。也就是说，自由层靠近电极线，参考层与该电极线距离最远，势垒层位于自由层和参考层之间。
本申请实施例中对自由层和参考层的磁矩方向不做具体限定，只要自由层和参考层的磁矩方向平行排列或反平行排列即可。
可选地，在每个存储块中，多个电压控制线平行；多个结构单元所在的平面平行，且每个结构单元所在的平面与多个电压控制线垂直。
在磁性随机存储器中，在各存储块中，每个结构单元中的所有电极线分别通过金属导线并联连接，从而在向磁性随机存储器中写入数据或者读取数据时，可以实现同时在结构单元中的所有电极线上施加读写电流，从而减少选组线在外围电路平面的排线空间，通过较少的选组线实现对磁性随机存储器中多层存储结构的寻址和访问。
进一步地，为了实现磁性随机存储器中数据的写入和读取，在电极线上施加电压或通入电流的过程可以由分别与两个选组线所连接的两个晶体管实现，其中一个选组线通过一个晶体管与电极线的一端连接，另一个选组线通过另一个晶体管与电极线的另一端连接。两个晶体管的导通和关断由字线控制。在字线上分别向两个晶体管施加栅极偏置电压使得两个晶体管导通，并在两个选组线上施加不同的电压，可以实现向电极线施加电压或通入电流。
例如，每一存储块还可以包括：第一选组线和第二选组线；第一选组线、第二选组线以及多个电压控制线之间相互平行；每个结构单元中的所有电极线分别通过金属导线并联连接，每个结构单元还包括字线、第一晶体管和第二晶体管。其中，第一晶体管和第二晶体管的栅极分别与字线连接，字线可用于为第一晶体管和第二晶体管提供栅极偏置电压，以使得第一晶体管和第二晶体管导通。第一晶体管的源极与第一选组线连接，第二晶体管的漏极与第二选组线连接，第一晶体管的漏极通过金属导线与电极线的第一端连接，第二晶体管的源极通过金属导线与电极线的第二端连接。分别在第一选组线和第二选组线上施加不同的电压，可以使得电极线中有电流通过，即为一个结构单元中的所有电极线上的存储单元并行提供写入电流。
在本申请中，每一存储块中的不同结构单元可以共用第一选组线和第二选组线，不同存储块对应位置的结构单元共用字线。其中，第一选组线和第二选组线可以与电压控制线 平行，字线可以与电极线平行。
其中，金属导线的材料与电极线的材料不同，金属导线可为低电阻的金属互联线，电极线可为具有较大自旋霍尔效应的材料。第一晶体管和第二晶体管可以是N型金属氧化物半导体(N metal oxide semiconductor，NMOS)晶体管。当然，第一晶体管和第二晶体管也可以是其他类型的晶体管，例如可以是P型金属氧化物半导体(P metal oxide semiconductor，NMOS)晶体管。本申请实施例对此不做具体限定。
此外，磁性随机存储器中，每一存储块还包括：分别与多个第一位线一一对应连接的多个放大器，多个放大器中的每个放大器用于读取对应连接的第一位线所接收的反馈信息，所述反馈信息用于指示对应连接的所述存储单元中存储的数据。
其中，每个放大器及其外围电路等共同组成读出回路，用于输出放大器所连接的电压控制线对应的存储单元的反馈信息，从而读取存储单元中的数据。
具体地，每个放大器可以通过将存储单元的反馈信息(例如电压、电流、电容量、充放电时间)与参考值做比较，来判断该存储单元处于高阻态还是低阻态，进而确定该存储单元中存储的数据。
第三方面，本申请实施例提供一种电子设备，该电子设备包括处理器以及与处理器耦合的本申请实施例提供的上述任一种磁性随机存储器。
具体地，处理器可以调用磁性随机存储器中存储的软件程序，以执行相应的方法，实现电子设备的相应功能。
附图说明
图1为本申请实施例提供的一种磁性随机存储器的结构示意图；
图2为本申请实施例提供的另一种磁性随机存储器的结构示意图；
图3为本申请实施例提供的又一种磁性随机存储器的结构示意图；
图4为本申请实施例提供的磁性随机存储器存在的漏电通道的示意图；
图5为本申请实施例提供的又一种磁性随机存储器的结构示意图；
图6为本申请实施例提供的又一种磁性随机存储器的结构示意图；
图7为本申请实施例提供的磁性随机存储器阻止漏电通道的示意图；
图8为本申请实施例提供的又一种磁性随机存储器的结构示意图；
图9为本申请实施例提供的又一种磁性随机存储器的结构示意图；
图10为本申请实施例提供的又一种磁性随机存储器的结构示意图；
图11为本申请实施例提供的又一种磁性随机存储器的结构示意图；
图12为本申请实施例提供的一种电子设备的结构示意图。
具体实施方式
本申请实施例提供一种磁性随机存储器及电子设备，用以提高磁性随机存储器的存储密度。
本申请实施例可以应用于图1所示的磁性随机存储器。该磁性随机存储器包括控制电路以及至少一个存储电路。具体地，每个存储电路中包括多个存储单元，存储单元是磁性随机存储器中具有数据存储和读写功能的最小单元，可以用于存储一个最小信息单位，即 1比特数据(例如0或1)，也就是一个二进制位。控制电路用于对存储电路中存储单元写入和读取数据的过程进行控制，比如，在写入数据时控制电路选择要写入数据的存储单元、通过给选择的存储单元施加相应电压和通入相应电流以实现在选择的存储单元中写入数据，再比如，在读取数据时控制电路选择要读取的存储单元，通过给选择的存储单元施加相应电压和通入相应电流以实现从选择的存储单元中读取数据。下面将结合附图对本申请实施例作进一步地详细描述。
需要说明的是，本申请中所涉及的多个，是指两个或两个以上。另外，需要理解的是，在本申请的描述中，“第一”、“第二”等词汇，仅用于区分描述的目的，而不能理解为指示或暗示相对重要性，也不能理解为指示或暗示顺序。
参见图2，为本申请实施例提供的一种磁性随机存储器的结构示意图，该磁性随机存储器可以包括N个存储块(即Block)：10(1)～10(N)，N为大于1的整数。N个存储块10(1)～10(N)可以视为图1中的N个存储电路。
参见图2和图3，每个存储块10(n)(n为1至N的任意整数)包括多个结构单元(cell)101以及多个电压控制线102；多个结构单元101中的每个结构单元101包括依次堆叠的多层存储结构(图3中是以3层存储结构为例进行示意)，多层存储结构中的每层存储结构包括电极线103以及设置于电极线103上的多个存储单元104，多个存储单元104中的每个存储单元104中包括一个MTJ，每个存储单元104的一端与电极线103连接，另一端与多个电压控制线102中的一个电压控制线102连接。其中，图2和图3均以存储块10(n)包括4个结构单元101、每个结构单元101包括9个存储单元104为例进行示意说明。
在具体实施时，磁性随机存储器包括多个存储块，为了减小不同存储块之间的漏电通道(sneak paths)，可以单独控制每个存储块中的电压控制线，即不同存储块中的电压控制线是相互独立的，因此，在本申请中，针对每个存储块，参见图3，存储块10(n)还可以包括与多个电压控制线102一一对应连接的多个第一位线(图3中以BL0～BL8为例进行示意)，多个第一位线BLn中每一个第一位线BLn通过金属导线与对应的电压控制线102连接。这样写操作时不同存储块10(n)通过各自的位线独立操作，从而可以降低数据写入时整个磁性随机存储器的不同存储块之间的sneak paths，进而降低磁性随机存储器的写入漏电功耗。
但是，上述方式尽管可以降低不同存储块之间的sneak paths，但是同一存储块中的不同存储单元之间依然存在sneak paths。参见图4，在磁性随机存储器中，假设在三个电压控制线102上分别施加电平“0”、“1”和“0”，由于“1”和“0”之间存在电压差，因此如图4中箭头所指，在存储单元104b和存储单元104a之间以及存储单元104b和存储单元104c之间依然会存在sneak paths，即在存储块中的存储单元104a、104b、104c之间仍然会存在sneak paths，写功耗依旧较大，限制了磁性随机存储器堆叠层数。
在本申请中，为了限制磁性随机存储器的存储块中不同存储单元之间的sneak paths，参见图5和图6，磁性随机存储器可以包括N个存储块(即Block)：10(1)～10(N)，N为大于0的整数。N个存储块10(1)～10(N)可以视为图1中的N个存储电路。
如图5和图6所示，每个存储块10(n)(n为1至N的任意整数)可以包括多个结构单元(cell)101以及多个电压控制线102；多个结构单元101中的每个结构单元101可以包括依次堆叠的多层存储结构，多层存储结构中的每层存储结构包括电极线103以及设置于电极线103上的多个存储单元104，多个存储单元104中的每个存储单元104可以包括一 个MTJ和一个单向导通选择器D，每个存储单元104的一端与电极线103连接，另一端与多个电压控制线102中的一个电压控制线102连接；单向导通选择器D的一端与磁性隧道结MTJ的一端连接，单向导通选择器D的另一端与电压控制线102连接，磁性隧道结MTJ的另一端与电极线103连接。
需要说明的是，单向导通选择器D可以为单向导通器件，当施加在单向导通选择器D的两端的电压差大于其开启阈值电压Vth(Vth＞0)时，单向导通选择器D处于导通低电阻态，当施加在单向导通选择器D两端的电压差小于其开启阈值电压Vth时，单向导通选择器D处于截止高电阻态。例如，当单向导通选择器D的正极和负极之间的电压差大于Vth时，单向导通选择器D处于导通低电阻态，当单向导通选择器D的正极和负极的电压差小于Vth时，单向导通选择器D处于截止高电阻态。
其中，图5以单向导通选择器D的导通电流方向由电压控制线102指向电极线103方向为例进行示意，如图5所示，单向导通选择器D的正极与电压控制线102连接，单向导通选择器D的负极与MTJ连接，则单向导通选择器D的正向电流方向为从电压控制线102到电极线103，当电压控制线102与电极线103之间的电压差大于开启阈值电压Vth(Vth>0)时，单向导通选择器D处于导通低电阻态，当电压控制线102与电极线103之间的电压差小于开启阈值电压Vth(Vth>0)时，单向导通选择器D处于截止高电阻态。图6以单向导通选择器D的导通电流方向由电极线103指向电压控制线102方向为例进行示意，如图6所示，单向导通选择器D的正极与MTJ连接，单向导通选择器D的负极与电压控制线102连接，则单向导通选择器D的正向电流方向为从电极线103到电压控制线102，当电极线103与电压控制线102之间的电压差大于开启阈值电压Vth(Vth>0)时，单向导通选择器D处于导通低电阻态，当电极线103与电压控制线102之间的电压差小于开启阈值电压Vth(Vth>0)时，单向导通选择器D处于截止高电阻态。
本申请中，如图7所示，假设同样在三个电压控制线102上分别施加电平“0”、“1”和“0”，但是由于每个存储单元104a、104b和104c均包括一个MTJ和一个单向导通选择器D，因此，在存储单元104b指向存储单元104a的通道中，存储单元104a中的单向导通选择器D是处于截止状态，在存储单元104b指向存储单元104c的通道中，存储单元104c中的单向导通选择器D是处于截止状态，因此可以有效限制不同存储单元104之间的sneak paths，从而可以较好降低磁性随机存储器的写入漏电功耗。
在具体实施时，单向导通选择器的电学特性、热处理温度以及可微缩性等需要与MTJ相匹配，例如满足：一定的开启电压/电流(0～2V，μA)，较高的整流比，耐久性(Endurance)高，操作速度在纳秒量级，热处理温度低等。
示例性的，本申请中单向导通选择器可以为单向导通二极管，例如肖特基二极管或者PN结二极管等，在此不作具体限定。当单向导通选择器为肖特基二极管时，肖特基二极管的正极可以指向电压控制线，也可以指向电极线，在此不作限定。同理，当单向导通选择器为PN结二极管时，PN结二极管的正极可以指向电压控制线，也可以指向电极线，在此不作限定。
在本申请中，当N大于1时，即该磁性随机存储器包括多个存储块时，多个存储块10_n可以沿着电极线103的方向平行排列。在每个存储块10_n中，电压控制线102与存储单元104是一一对应的，也就是说，每个存储单元104均有与之对应的一个电压控制线102，用于向该存储单元104施加电压。
可选地，在每个存储块中，多个电压控制线平行；多个结构单元所在的平面平行，且每个结构单元所在的平面与多个电压控制线垂直。
需要说明的是，本申请实施例中，多个电压控制线平行的概念并不是严格意义上的平行，在磁性随机存储器的制备过程中，由于制备工艺和制备设备的影响，可能存在多个电压控制线并非严格平行的情况，这种情况是由于具体制备流程导致的，并不能说明多个电压控制线不严格平行的情况超脱本申请的保护范围。此外，对于平面平行和垂直这两种位置关系也有类似理解，此处不再赘述。
为了方便描述，在附图2、附图3、附图5和附图6所示的磁性随机存储器中均示出了xyz坐标系。其中，在每个存储块10(n)中，电压控制线沿x轴平行排列；每个存储块10(n)中的电极线沿y轴平行排列，多个存储块10(n)沿y轴平行排列；在每个存储块10(n)中，多层存储结构沿着z轴方向依次堆叠。每个结构单元所在的平面均与x轴垂直。
应理解，存储单元是磁性随机存储器中具有数据存储和读写功能的最小单元，可以用于存储一个最小信息单位，即1比特数据(例如0或1)，也就是一个二进制位。通过多个存储单元，可以实现多个二进制位数据的存储。具体地，本申请实施例中，一个存储单元用于存储一个二进制位。
在具体实施时，每个MTJ可以包括依次堆叠的自由层、势垒层和参考层。其中，参考层的磁矩方向固定，自由层的磁矩方向可以在数据写入时发生改变，自由层与参考层的磁矩呈平行或反平行排列时对应不同的数据，势垒层用于产生隧道磁电阻效应。具体地，本申请中，自由层与电极线连接，参考层与电压控制线连接，或者参考层通过单向导通选择器与电压控制线连接。也就是说，自由层靠近电极线，参考层与该电极线距离最远，势垒层位于自由层和参考层之间。
具体地，本申请实施例中，对于自由层和参考层的磁矩方向平行排列或反平行排列，可以有如下理解：自由层和参考层的磁矩方向可以在xy平面内，可以垂直于xy平面，或者与xy平面呈一定倾斜角度。本申请实施例中对自由层和参考层的磁矩方向不做具体限定，只要自由层和参考层的磁矩方向平行排列或反平行排列即可。
本申请实施例提供的磁性随机存储器在写入数据时利用了SOT效应和VCMA效应，在读取数据时利用了隧穿磁电阻(tunnel magneto resistance，TMR)效应。
SOT效应的原理是：在电极线中通入电流，将会产生向上(即向z轴正方向)扩散的自旋极化电流，进入MTJ的自由层中。当电流达到一定值(临界翻转电流密度)时，在自旋轨道相互作用力矩作用下，自由层的磁矩发生翻转，实现数据的写入。改变电极线中电流的方向，自旋流的极化方向发生改变，自由层的磁矩翻转方向也相应改变，实现不同数据的写入。
VCMA效应的原理是：在MTJ两端施加偏置电压可以改变MTJ自由层与势垒层的界面电荷密度，从而改变自由层的垂直各向异性和矫顽力，进而降低MTJ的临界翻转电流密度。利用VCMA效应降低MTJ临界翻转电流密度的同时，在电极线中通入电流，在SOT效应和VCMA效应的共同作用下使得自由层中的磁矩发生翻转，实现数据的写入，这种写入方式可以降低数据写入的功耗。
实际应用中，电极线可以由重金属材料制成，或者由其他可以产生自旋流的材料制成，电极线也可以称为SOT电极线。
具体地，在向磁性随机存储器写入数据时，由电压控制线独立地对其连接的存储单元 进行选择性操作，例如可以在需要写入数据的存储单元所连接的电压控制线上施加第一偏置电压，降低需要写入数据的存储单元的临界翻转电流密度。在不需要写入数据的存储单元所连接的电压控制线上施加第二偏置电压，提高(或不改变)非写入存储单元的临界翻转电流密度。与此同时，在需要写入数据的存储单元所连接的电极线中通入写入电流(通入不同方向的电流，可以写入不同的数据)，产生向上(即向z轴正方向)扩散的自旋流进入MTJ的自由层中，从而实现在需要写入数据的存储单元写入数据。
TMR效应的原理是：当MTJ的自由层和参考层的磁矩平行排列时，MTJ为低电阻态；当自由层和参考层的磁矩反平行排列(即平行且方向相反)时，MTJ为高电阻态。高低电阻代表了两种不同的数据状态，例如0或1；根据MTJ为高阻态或低阻态可以读取出不同的数据。
具体地，在从磁性随机存储器读取数据时，需要通过与电压控制线连接的读出回路(例如包括放大器)获取需要读取数据的存储单元中存储的反馈信息。所述反馈信息用于指示所述对应连接的存储单元中存储的数据。
示例性地，通过读出回路中的放大器的输出电压，可以判断该放大器所连接的电压控制线对应的MTJ为高阻态或低阻态，进而判断该MTJ中存储的数据为0还是为1。
为了避免在写入数据时，电极线上的电流流经MTJ形成漏电通路(sneak paths)，对写入数据的准确性产生影响，本申请实施例中，MTJ可以具有高电阻特性，例如MTJ的电阻值不低于100KΩ，使得MTJ的电阻值远大于电极线的电阻值，这样可以有效避免写入电流流经MTJ，降低sneak paths对写入数据准确性的影响。
在磁性随机存储器中，如图3、图8和图10所示，在各存储块10(n)中，每个结构单元101中的所有电极线103分别通过金属导线并联连接，从而在向磁性随机存储器中写入数据或者读取数据时，可以实现同时在结构单元101中的所有电极线103上施加读写电流，从而减少选组线在外围电路平面的排线空间，通过较少的选组线实现对磁性随机存储器中多层存储结构的寻址和访问。
进一步地，为了实现磁性随机存储器中数据的写入和读取，在电极线上施加电压或通入电流的过程可以由分别与两个选组线所连接的两个晶体管实现，其中一个选组线通过一个晶体管与电极线的一端连接，另一个选组线通过另一个晶体管与电极线的另一端连接。两个晶体管的导通和关断由字线控制。在字线上分别向两个晶体管施加栅极偏置电压使得两个晶体管导通，并在两个选组线上施加不同的电压，可以实现向电极线施加电压或通入电流。
例如，如图3、图8和图10所示，每一存储块10(n)还可以包括：第一选组线bl和第二选组线sl；第一选组线bl、第二选组线sl以及多个电压控制线102之间相互平行；每个结构单元101中的所有电极线103分别通过金属导线并联连接，每个结构单元101还包括字线WL、第一晶体管T1和第二晶体管T2。其中，第一晶体管T1和第二晶体管T2的栅极分别与字线WL连接，字线WL可用于为第一晶体管T1和第二晶体管T2提供栅极偏置电压，以使得第一晶体管T1和第二晶体管T2导通。第一晶体管T1的源极与第一选组线bl连接，第二晶体管T2的漏极与第二选组线sl连接，第一晶体管T1的漏极通过金属导线与电极线103的第一端连接，第二晶体管T2的源极通过金属导线与电极线103的第二端连接。分别在第一选组线bl和第二选组线sl上施加不同的电压，可以使得电极线103中有电流通过，即为一个结构单元中的所有电极线103上的存储单元104并行提供写入电流。
在本申请中，每一存储块10(n)中的不同结构单元101可以共用第一选组线bl和第二选组线sl，不同存储块10(n)对应位置的结构单元101共用字线WL。其中，第一选组线bl和第二选组线sl可以与电压控制线102平行，字线WL可以与电极线103平行，例如在图3、图8和图10中，第一选组线bl、第二选组线sl以及电压控制线102均沿着x方向延伸，字线WL和电极线103均沿着y方向延伸。
其中，金属导线的材料与电极线的材料不同，金属导线可为低电阻的金属互联线，电极线可为具有较大自旋霍尔效应的材料。第一晶体管和第二晶体管可以是N型金属氧化物半导体(N metal oxide semiconductor，NMOS)晶体管。当然，第一晶体管和第二晶体管也可以是其他类型的晶体管，例如可以是P型金属氧化物半导体(P metal oxide semiconductor，NMOS)晶体管。本申请实施例对此不做具体限定。
下面通过具体实施例说明本申请提供的磁性随机存储器的具体结构和工作过程。
实施例一、
参见图2和图3，磁性随机存储器包括多个存储块：10(1)～10(N)，每个存储块10(n)中包括多个结构单元101、多个电压控制线102、与多个电压控制线102一一对应连接的多个第一位线BLn(图3中以n等于0～8为例进行示意)、第一选组线bl和第二选组线sl；第一选组线bl、第二选组线sl以及多个电压控制线102之间相互平行；多个第一位线BLn中每一个第一位线BLn通过金属导线与对应的电压控制线102连接。同一个存储块10(n)的不同结构单元101之间共用第一选组线bl和第二选组线sl。多个结构单元101中的每个结构单元101包括依次堆叠的多层存储结构、字线WL、第一晶体管T1和第二晶体管T2，沿着y方向的不同存储块10(n)之间共用字线WL。多层存储结构中的每层存储结构包括电极线103以及设置于电极线103上的多个存储单元104，多个存储单元104中的每个存储单元104包括一个MTJ，每个存储单元104的一端与电极线103连接，另一端与多个电压控制线102中的一个电压控制线102连接。每个结构单元101中的所有电极线103分别通过金属导线并联连接，第一晶体管T1和第二晶体管T2的栅极分别与字线WL连接，第一晶体管T1的源极与第一选组线bl连接，第二晶体管T2的漏极与第二选组线sl连接，第一晶体管T1的漏极通过金属导线与电极线103的第一端连接，第二晶体管T2的源极通过金属导线与电极线103的第二端连接。示例性的，金属导线可为低电阻的互联金属线。
在该实施例中，不同的存储块10(n)之间，对应的电压控制线102和第一位线BLn均是不同的。这样写操作时不同存储块10(n)不会同时运行，可以降低写操作时并行执行读写操作的存储块的数量，以减少存储块之间的sneak paths，从而降低磁性随机存储器的写入漏电功耗。
向磁性随机存储器写入数据的过程具体可以如下：
在向磁性随机存储器写入数据时，针对需要写入数据的存储单元104所属的存储块10(n)，需要写入数据的存储单元104所属的结构单元101对应的字线WL分别向与其连接的第一晶体管T1和第二晶体管T2施加栅极偏置电压，使第一晶体管T1和第二晶体管T2导通，向第一选组线bl施加写入电压、且使第二选组线sl接地，或者使第一选组线bl接地、向第二选组线sl施加写入电压；与需要写入数据的存储单元104对应的第一位线BLn向与该存储单元104连接的电压控制线102施加第一偏置电压，其它第一位线BLn向与不需要写入数据的存储单元104连接的电压控制线102施加第二偏置电压，第一偏置电压与第二偏置电压不相等。
其中，第一偏置电压用于降低(或不改变)需要写入数据的存储单元104的临界翻转电流密度，第二偏置电压用于不改变(或提高)不需要写入数据的存储单元104的临界翻转电流密度。第一偏置电压和第二偏置电压的值不相同，第一偏置电压和第二偏置电压的具体数值可以根据存储单元104的具体结构和材料参数确定。也就是说，当电压控制线102施加第一偏置电压时，可以实现向电压控制线102连接的存储单元104写入数据；当电压控制线102施加第二偏置电压时，无法向电压控制线102连接的存储单元104写入数据。
在一个具体的示例中，第一偏置电压与电极线103的电压之差为负值，第二偏置电压与电极线103的电压之差为正值或零；或者，第一偏置电压与电极线103的电压之差为正值，第二偏置电压与电极线103的电压之差为负值或零。
在向某个存储单元104写入数据时，可以根据需要写入的数据(0或1)判断电极线103中所需的电流方向，进而确定在第一选组线bl上施加写入电压还是在第二选组线sl上施加写入电压；同时，通过需要写入数据的存储单元104所对应的第一位线BLn向该存储单元104所连接的电压控制线102上施加第一偏置电压，通过不需要写入数据的存储单元104所对应的第一位线BLn向该存储单元104所连接的电压控制线102上施加第二偏置电压，从而实现向某个存储单元104写入数据的过程。
从磁性随机存储器读取数据的过程具体可以如下：
在从磁性随机存储器读取数据时，针对每一存储块10(n)，可以一次性读取该存储块10(n)中某个结构单元101中所有存储单元104中存储的数据。存储单元104中数据的读取利用TMR效应。在读取某个结构单元101中所有存储单元104中存储的数据时，通过需要读取数据的结构单元101对应的字线WL分别向需要读取数据的结构单元101中的第一晶体管T1和第二晶体管T2施加栅极偏置电压，第一晶体管T1和第二晶体管T2导通；以及通过需要读取数据的结构单元101所属的存储块中的第一选组线bl和第二选组线sl向对应连接的存储单元104施加读取电压或读取电流，并使需要读取数据的结构单元101所属的存储块10(n)中的所有电压控制线102接地，以及通过所有电压控制线102接收对应连接的存储单元104的反馈信息，该反馈信息用于指示对应连接的存储单元104中存储的数据。或者，通过需要读取数据的结构单元101所属的存储块10(n)中的所有电压控制线102施加读取电压或读取电流，并使第一选组线bl和第二选组线sl接地，从而提供接地回路。
其中，通过每个电压控制线102向对应连接的存储单元104施加读取电压时，存储单元104的反馈信息可以是存储单元104的电流、电容量等信息，在每个电压控制线102施加的读取电压相同的情况下，存储单元104处于不同阻态时，反馈的电流或电容量不同；每个电压控制线102向对应连接的存储单元104施加读取电流时，存储单元104的反馈信息可以是存储单元104的电压、电容量等信息，在每个电压控制线102施加的读取电流相同的情况下，存储单元104处于不同阻态时，反馈的电压或电容量不同。
此外，如图3所示，存储块10(n)中还可以包括分别与多个电压控制线102一一对应连接的多个放大器SA，多个放大器中的每个放大器用于读取对应连接的第一位线BLn所接收的反馈信息。
其中，每个放大器及其外围电路等共同组成读出回路，用于输出放大器所连接的第一位线BLn对应的存储单元104的反馈信息，从而读取存储单元104中的数据。
具体地，每个放大器可以通过将存储单元104的反馈信息(例如电压、电流、电容量、充放电时间)与参考值做比较，来判断该存储单元104处于高阻态还是低阻态，进而确定 该存储单元104中存储的数据。
实际应用中，在向磁性随机存储器写入数据时，上述在第一选组线bl、第二选组线sl和各第一位线BLn上施加电压或通入电流的过程可以由磁性随机存储器中配置的电平控制电路进行控制，该电平控制电路用于为第一选组线bl、第二选组线sl和各第一位线BLn提供所需的电压或电流。同样地，在从磁性随机存储器读取数据时，在各第一位线BLn上施加电压或通入电流的过程也可以由该电平控制电路控制，该电平控制电路用于为各第一位线BLn提供所需的电压或电流。
磁性随机存储器中还可以包括行地址解码电路和列地址解码电路，用于在写入或读取数据时通过字线WL和位线选择对应的存储单元104，上述电平控制电路可以根据行地址解码电路和列地址解码电路的选择来判断需要在第一选组线bl、第二选组线sl和各第一位线BLn上施加的电压或电流，实现对行地址解码电路和列地址解码电路选择的某一个或某几个存储单元104进行读写操作。
其中，电平控制电路、行地址解码电路和列地址解码电路可以统称为控制电路。
进一步地，如图3所示，可以将第一层和第二层的6根电压控制线102通过金属导线从存储块10(n)的右端引出并连接到外围电路所在的平面，分别由6根第一位线BL0～BL5控制；第三层的3根电压控制线通过金属导线从存储块10(n)的左端引出并连接到外围电路所在的平面，分别由3根第一位线BL6～BL8控制。在具体实施时，第一位线BL0～BL8可以设置在存储块10(n)的四周，不限于图3中的左端和右端，实现在一个存储块10(n)的外围电路平面内容纳该存储块10(n)所有的第一位线BL0～BL8，解决了3D MRAM方案中对不同存储平面的寻址问题。字线WL和第一位线BLn分别连接行列地址解码电路。写操作时，在需要写入数据的存储单元104所在结构单元101连接的字线WL上施加栅极偏置电压，字线WL控制的第一晶体管T1和第二晶体管T2处于导通状态，在其他不需要写入数据的结构单元101连接的字线WL上施加另一偏置电压，其他不需要写入数据的结构单元101的第一晶体管T1和第二晶体管T2关断。在需要写入数据的存储单元104所在的结构单元101的第一选组线sl和第二选组线bl之间施加写电压，则只有需要写入数据的存储单元104所在的结构单元101的电极线103上有写电流流过，即唯一选中了需要写入数据的存储单元104所属的结构单元101。同时，在需要写入数据的存储单元104连接的电压控制线102所连接的第一位线BLn上施加写入电压，在选中的结构单元101中其他电压控制线102连接的BLn都施加非写入电压(非写入电压与写入电压不相同)。在SOT和VCMA效应的共同作用下，可以实现对需要写入数据的存储单元104的选择性写入。改变第一选组线sl和第二选组线bl之间的电压极性，则可以在电极线103中产生相反方向的电流，从而写入不同信息。读操作时，一次读取选中结构单元101内所有的存储单元104中的反馈信息，即在需要读取数据的结构单元101连接的字线WL上施加栅极偏置电压，字线WL控制的第一晶体管T1和第二晶体管T2处于导通状态，在其他不需要读取数据的结构单元101连接的字线WL上施加另一偏置电压，其他不需要读取数据的结构单元101的第一晶体管T1和第二晶体管T2关断。将需要读取数据的结构单元101的第一选组线sl和第二选组线bl都接地。同时，将存储块10(n)中所有第一位线BLn接读取电压或读取电流，则只有需要读取数据的结构单元101的存储单元104上有读电流流过，实现一次读取选中结构单元101中所有存储单元104的反馈信息。
综上，采用本申请实施例提供的磁性随机存储器，由于存储阵列是3D的，该方案相 比现有技术中的2D阵列，可以在保证存储单元的热稳定的前提下，通过垂直方向存储单元的叠加增加面存储密度，进而提高磁性随机存储器的存储密度。此外，由于不同的存储块之间，对应的电压控制线和第一位线均是不同的。这样写操作时不同存储块不会同时运行，从而可以降低写操作时并行运行的存储块的数量，减少存储块之间的sneak paths，进而降低磁性随机存储器的写入漏电功耗。
实施例二、
参见图5和图8，该磁性随机存储器包括至少1个存储块10(n)。各存储块10(n)中包括多个结构单元101、多个电压控制线102、第一选组线bl和第二选组线sl；第一选组线bl、第二选组线sl以及多个电压控制线102之间相互平行，同一个存储块10(n)的不同结构单元101之间共用第一选组线bl和第二选组线sl。多个结构单元101中的每个结构单元101包括依次堆叠的多层存储结构、字线WL、第一晶体管T1和第二晶体管T2，沿着y方向的不同存储块10(n)之间共用字线WL。多层存储结构中的每层存储结构包括电极线103以及设置于电极线103上的多个存储单元104，多个存储单元104中的每个存储单元104包括一个MTJ和一个单向导通选择器D，每个存储单元104的一端与电极线103连接，另一端与多个电压控制线102中的一个电压控制线102连接；单向导通选择器D的负极与磁性隧道结MTJ的一端连接，单向导通选择器D的正极与电压控制线102连接，磁性隧道结MTJ的另一端与电极线103连接。每个结构单元101中的所有电极线103分别通过金属导线并联连接，第一晶体管T1和第二晶体管T2的栅极分别与字线WL连接，第一晶体管T1的源极与第一选组线bl连接，第二晶体管T2的漏极与第二选组线sl连接，第一晶体管T1的漏极通过金属导线与电极线103的第一端连接，第二晶体管T2的源极通过金属导线与电极线103的第二端连接。示例性的，金属导线的材料可为低电阻的互联金属材料，电极线可为具有大的自旋霍尔效应的材料。
向磁性随机存储器写入数据的过程具体可以如下：
在向该磁性随机存储器写入数据时，针对需要写入数据的存储单元104所属的存储块10(n)，需要写入数据的存储单元104所属的结构单元101对应的字线WL分别向与其连接的第一晶体管T1和第二晶体管T2施加栅极偏置电压，使第一晶体管T1和第二晶体管T2导通，在其他不需要写入数据的结构单元101连接的字线WL上施加另一偏置电压，其他不需要写入数据结构单元101的第一晶体管T1和第二晶体管T2关断。向第一选组线bl施加写入电压、第二选组线sl接地，或者第一选组线bl接地、第二选组线sl施加写入电压；存储块10(n)中与需要写入数据的存储单元104对应的第一位线BLn向与该存储单元104连接的电压控制线102施加第一偏置电压，其它第一位线BLn向与不需要写入数据的存储单元104连接的电压控制线102施加第二偏置电压，第一偏置电压与第二偏置电压不相等。
其中，如果自由层和参考层是面内磁化的CoFeB材料，势垒层为MgO.则第一偏置电压用于使电压控制线102和电极线103之间的电压差小于单向导通选择器D的开启阈值电压，单向导通选择器D处于非导通高电阻态，则MTJ两端电压差小，VCMA效应很弱，相应的MTJ的临界翻转电流密度基本不变。第二偏置电压用于使电压控制线102和电极线103之间的电压差大于单向导通选择器D的开启阈值电压，单向导通选择器D处于导通低电阻态，在VCMA效应作用下，不需要写入数据的存储单元104的临界翻转电流密度增 大。如果自由层和参考层是垂直磁化的CoFeB材料，势垒层为MgO。第一偏置电压用于使电压控制线102和电极线103之间的电压差大于单向导通选择器D的开启阈值电压，单向导通选择器D处于导通低电阻态，VCMA效应使得需要写入数据的存储单元104的临界翻转电流密度减小，第二偏置电压用于使电压控制线102和电极线103之间的电压差小于单向导通选择器D的开启阈值电压，单向导通选择器D处于截止高电阻态，VCMA效应很弱，不需要写入数据的存储单元104的自由层的垂直各向异性基本不变，相应的临界翻转电流密度不变。同时，在SOT电极线中通入合适的电流，可以使得第一偏置电压作用下的存储单元自由层发生翻转，而第二偏置电压作用下的存储单元不发生翻转。
第一偏置电压和第二偏置电压的值不相同，第一偏置电压和第二偏置电压的具体数值可以根据存储单元104的具体结构和材料参数确定。也就是说，当电压控制线102施加第一偏置电压时，可以实现向电压控制线102连接的存储单元104写入数据；当电压控制线102施加第二偏置电压时，无法向电压控制线102连接的存储单元104写入数据。
在向某个存储单元104写入数据时，可以根据需要写入的数据(0或1)判断电极线103中所需的电流方向，进而确定在第一选组线bl上施加写入电压还是在第二选组线sl上施加写入电压；同时，通过需要写入数据的存储单元104所对应的第一位线BLn向该存储单元104所连接的电压控制线102上施加第一偏置电压，通过不需要写入数据的存储单元104所对应的第一位线BLn向该存储单元104所连接的电压控制线102上施加第二偏置电压，从而实现向某个存储单元104写入数据的过程。
从磁性随机存储器读取数据的过程具体可以如下：
在从该磁性随机存储器读取数据时，针对每一存储块10(n)，可以一次性读取该存储块10(n)中某个结构单元101中所有存储单元104中存储的数据。存储单元104中数据的读取利用TMR效应。在读取某个结构单元101中所有存储单元104中存储的数据时，通过需要读取数据的结构单元101对应的字线WL分别向需要读取数据的结构单元101中的第一晶体管T1和第二晶体管T2施加栅极偏置电压，第一晶体管T1和第二晶体管T2导通。在其他不需要读取数据的结构单元101连接的字线WL上施加另一偏置电压，其他不需要读取数据结构单元101的第一晶体管T1和第二晶体管T2关断；并且，使需要读取数据的结构单元101所属的存储块10(n)中的第一选组线bl和第二选组线sl接地，从而提供接地回路。并向需要读取数据的结构单元101所属的存储块10(n)中的所有电压控制线102施加读取电压或读取电流，以及通过所有电压控制线102接收对应连接的存储单元104的反馈信息，该反馈信息用于指示对应连接的存储单元104中存储的数据。
其中，通过每个电压控制线102向对应连接的存储单元104施加读取电压时，存储单元104的反馈信息可以是存储单元104的电流、电容量等信息，在每个电压控制线102施加的读取电压相同的情况下，存储单元104处于不同阻态时，反馈的电流或电容量不同；每个电压控制线102向对应连接的存储单元104施加读取电流时，存储单元104的反馈信息可以是存储单元104的电压、电容量等信息，在每个电压控制线102施加的读取电流相同的情况下，存储单元104处于不同阻态时，反馈的电压或电容量不同。
此外，存储块10(n)中还可以包括分别与多个电压控制线102一一对应连接的多个放大器SA，多个放大器中的每个放大器用于读取对应连接的电压控制线102所接收的反馈信息。
其中，每个放大器及其外围电路等共同组成读出回路，用于输出放大器所连接的电压 控制线102对应的存储单元104的反馈信息，从而读取存储单元104中的数据。
具体地，每个放大器可以通过将存储单元104的反馈信息(例如电压、电流、电容量、充放电时间)与参考值做比较，来判断该存储单元104处于高阻态还是低阻态，进而确定该存储单元104中存储的数据。
实际应用中，在向磁性随机存储器写入数据时，上述在第一选组线bl、第二选组线sl和各电压控制线102上施加电压或通入电流的过程可以由磁性随机存储器中配置的电平控制电路进行控制，该电平控制电路用于为第一选组线bl、第二选组线sl和各电压控制线102提供所需的电压或电流。同样地，在从磁性随机存储器读取数据时，在各电压控制线102上施加电压或通入电流的过程也可以由该电平控制电路控制，该电平控制电路用于为各电压控制线102提供所需的电压或电流。
磁性随机存储器中还可以包括行地址解码电路和列地址解码电路，用于在写入或读取数据时通过字线WL和位线选择对应的存储单元104，上述电平控制电路可以根据行地址解码电路和列地址解码电路的选择来判断需要在第一选组线bl、第二选组线sl和各电压控制线102上施加的电压或电流，实现对行地址解码电路和列地址解码电路选择的某一个或某几个存储单元104进行读写操作。
其中，电平控制电路、行地址解码电路和列地址解码电路可以统称为控制电路。
在该实施例中，由于每个存储单元104包括一个MTJ和一个单向导通选择器D，因此，当相邻两个存储单元104之间存在电压差时，总有一个存储单元104中的单向导通选择器D是处于反向截止状态，因此可以有效限制不同存储单元104之间的sneak path，从而可以较好降低磁性随机存储器的写入漏电功耗。
在该实施例中，当磁性随机存储器中包括多个存储块10(n)时，不同存储块10(n)对应的电压控制线可以是不同的，也可以是相同，在此不作限定。
为了进一步降低磁性随机存储器的写入漏电功耗，当磁性随机存储器中包括多个存储块10(n)时，可以通过减小一次写操作过程中同时工作的存储块的数量，来减少不同存储块之间的sneak paths，从而减小写操作时整个磁性随机存储器的漏电功耗。为了减小一次写操作过程中同时工作的存储块的数量，可以单独控制每个存储块中的电压控制线，即不同存储块中的电压控制线是相互独立的。示例性的，在本申请中，针对每个存储块10(n)，如图9所示，每一存储块10(n)还包括：分别与多个电压控制线102一一对应连接的多个第一位线BLn(图9中以n等于0～8为例进行示意)，多个第一位线BLn中每一个位线BLn通过金属导线与对应的电压控制线102连接。这样写操作时不同存储块10(n)不会同时运行，从而可以降低整个磁性随机存储器的漏电功耗。
继续参见图9，在存储块10(n)中，与各电压控制线102一一对应的放大器SA通过第一位线BLn与电压控制线102连接，即第一位线BLn的一端与电压控制线102连接，第一位线BLn的另一端与放大器SA连接。
进一步地，在该实施例中，如图9所示，可以将第一层和第二层的6根电压控制线102通过金属导线从存储块10(n)的右端引出并连接到外围电路所在的平面，分别由6根第一位线BL0～BL5控制；第三层的3根电压控制线102通过金属导线从存储块10(n)的左端引出并连接到外围电路所在的平面，分别由3根第一位线BL6～BL8控制。在具体实施时，第一位线BL0～BL8可以设置在存储块10(n)的四周，不限于图9中的左端和右端，实现在一个存储块10(n)的外围电路平面内容纳该存储块10(n)所有的第一位线BL0～BL8，解决了3D  MRAM方案中对不同存储平面的寻址问题。字线WL和第一位线BLn分别连接行列地址解码电路。写操作时，在需要写入数据的存储单元104所在结构单元101连接的字线WL上施加栅极偏置电压，字线WL控制的第一晶体管T1和第二晶体管T2处于导通状态；在其他不需要写入数据的结构单元101连接的字线WL上施加另一偏置电压，使得相连的第一晶体管T1和第二晶体管T2处于关断状态。在需要写入数据的存储单元104所在的结构单元101的第一选组线sl和第二选组线bl之间施加写电压，则只有需要写入数据的存储单元104所在的结构单元101的电极线103上有写电流流过，即唯一选中了需要写入数据的存储单元104所属的结构单元101。同时，在需要写入数据的存储单元104连接的电压控制线102所连接的第一位线BLn上施加第一偏置电压，在选中的结构单元101中其他不需要写入数据的存储单元104连接的电压控制线102所连接的第一位线BLn上都施加第二偏置电压。在SOT和VCMA效应的共同作用下，可以实现对需要写入数据的存储单元104的选择性写入。改变第一选组线sl和第二选组线bl之间的电压极性，则可以在电极线103中产生相反方向的电流，从而写入不同信息。读操作时，一次读取选中结构单元101内所有的存储单元104中的反馈信息，即在需要读取数据的结构单元101连接的字线WL上施加栅极偏置电压，字线WL控制的第一晶体管T1和第二晶体管T2处于导通状态，在其他不需要读取数据的结构单元101连接的字线WL上施加另一偏置电压，使得相连的第一晶体管T1和第二晶体管T2处于关断状态。将需要读取数据的结构单元101的第一选组线sl和第二选组线bl都接地，同时，将该存储块10(n)的第一位线BLn接读取电压或读取电流，则只有需要读取数据的结构单元101的存储单元104上有读电流流过，实现一次读取选中结构单元101中所有存储单元104的反馈信息。
综上，采用本申请实施例提供的磁性随机存储器，由于存储阵列是3D的，该方案相比现有技术中的2D阵列，可以在保证存储单元的热稳定的前提下，通过垂直方向存储单元的叠加增加面存储密度，进而提高磁性随机存储器的存储密度。此外，在该实施例中，由于每个存储单元包括一个MTJ和一个单向导通选择器，因此，在任意两个存储单元之间有电压差形成漏电通道时，总有一个存储单元中的单向导通选择器是处于反向截止状态，因此可以有效限制不同存储单元之间的sneak paths，从而降低磁性随机存储器的写入漏电功耗。
另外，当不同的存储块对应的电压控制线和第一位线均不同时，写操作时不同存储块不会同时运行，从而可以降低写操作时并行运行的存储块的数量，减少存储块之间的sneak paths，进而可以进一步降低磁性随机存储器的写入漏电功耗。
实施例三、
参见图6和图10，该磁性随机存储器包括至少1个存储块(n)。各存储块10(n)中包括多个结构单元101、多个电压控制线102、第一选组线bl和第二选组线sl；第一选组线bl、第二选组线sl以及多个电压控制线102之间相互平行，同一个存储块10(n)的不同结构单元101之间共用第一选组线bl和第二选组线sl。多个结构单元101中的每个结构单元101包括依次堆叠的多层存储结构、字线WL、第一晶体管T1和第二晶体管T2，沿着y方向的不同存储块10(n)之间共用字线WL。多层存储结构中的每层存储结构包括电极线103以及设置于电极线103上的多个存储单元104，多个存储单元104中的每个存储单元104包括一个MTJ和一个单向导通选择器D，每个存储单元104的一端与电极线103连接，另一 端与多个电压控制线102中的一个电压控制线102连接；单向导通选择器D的正极与磁性隧道结MTJ的一端连接，单向导通选择器D的负极与电压控制线102连接，磁性隧道结MTJ的另一端与电极线103连接。每个结构单元101中的所有电极线103分别通过金属导线并联连接，第一晶体管T1和第二晶体管T2的栅极分别与字线WL连接，第一晶体管T1的源极与第一选组线bl连接，第二晶体管T2的漏极与第二选组线sl连接，第一晶体管T1的漏极通过金属导线与电极线103的第一端连接，第二晶体管T2的源极通过金属导线与电极线103的第二端连接。示例性的，金属导线的材料可为低电阻的互联金属材料，电极线可为具有大的自旋霍尔效应的材料。
向磁性随机存储器写入数据的过程具体可以如下：
在向该磁性随机存储器写入数据时，针对需要写入数据的存储单元104所属的存储块10(n)，需要写入数据的存储单元104所属的结构单元101对应的字线WL分别向与其连接的第一晶体管T1和第二晶体管T2施加栅极偏置电压，使第一晶体管T1和第二晶体管T2导通，向第一选组线bl施加写入电压、第二选组线sl接地，或者第一选组线bl接地、第二选组线sl施加写入电压；与需要写入数据的存储单元104对应的第一位线BLn向与该存储单元104连接的电压控制线102施加第一偏置电压，其它第一位线BLn向与不需要写入数据的存储单元104连接的电压控制线102施加第二偏置电压，第一偏置电压与第二偏置电压不相等。
其中，如果自由层和参考层是面内磁化的CoFeB材料，势垒层为MgO。第一偏置电压用于使电极线103和电压控制线102之间的电压差大于单向导通选择器D的开启阈值电压，单向导通选择器D处于导通低电阻态，需要写入数据的存储单元104的临界翻转电流密度变小，第二偏置电压用于使电极线103和电压控制线102之间的电压差小于单向导通选择器D的开启阈值电压，单向导通选择器D处于截止高电阻态，VCMA效应很弱，非写入数据的存储单元104的自由层的垂直各向异性基本不变，相应的临界翻转电流密度不变。如果自由层和参考层是垂直磁化的CoFeB材料，第一偏置电压用于使电极线103和电压控制线102之间的电压差小于单向导通选择器D的开启阈值电压，单向导通选择器D处于截止高电阻态，VCMA效应弱，使得需要写入数据的存储单元104的自由层的临界翻转电流密度不变，第二偏置电压用于使电极线103和电压控制线102之间的电压差大于单向导通选择器D的开启阈值电压，单向导通选择器D处于导通低电阻态，非写入单元的自由层的垂直各向异性增强，临界翻转电流密度变大。同时，在SOT电极线中通入合适的电流，可以使得第一偏置电压作用下的存储单元自由层发生翻转，而第二偏置电压作用下的存储单元不发生翻转。
第一偏置电压和第二偏置电压的值不相同，第一偏置电压和第二偏置电压的具体数值可以根据存储单元104的具体结构和材料参数确定。也就是说，当电压控制线102施加第一偏置电压时，可以实现向电压控制线102连接的存储单元104写入数据；当电压控制线102施加第二偏置电压时，无法向电压控制线102连接的存储单元104写入数据。
在向某个存储单元104写入数据时，可以根据需要写入的数据(0或1)判断电极线103中所需的电流方向，进而确定在第一选组线bl上施加写入电压还是在第二选组线sl上施加写入电压；同时，通过需要写入数据的存储单元104所对应的第一位线BLn向该存储单元104所连接的电压控制线102上施加第一偏置电压，通过不需要写入数据的存储单元104所对应的第一位线BLn向该存储单元104所连接的电压控制线102上施加第二偏置电 压，从而实现向某个存储单元104写入数据的过程。
从磁性随机存储器读取数据的过程具体可以如下：
在从该磁性随机存储器读取数据时，针对每一存储块10(n)，可以一次性读取该存储块10(n)中某个结构单元101中所有存储单元104中存储的数据。存储单元104中数据的读取利用TMR效应。在读取某个结构单元101中所有存储单元104中存储的数据时，通过需要读取数据的结构单元101对应的字线WL分别向需要读取数据的结构单元101中的第一晶体管T1和第二晶体管T2施加栅极偏置电压，第一晶体管T1和第二晶体管T2导通。在其他不需要读取数据的结构单元101连接的字线WL上施加另一偏置电压，其他不需要读取数据结构单元101的第一晶体管T1和第二晶体管T2关断；向需要读取数据的结构单元101所属的存储块10(n)中的第一选组线bl和第二选组线sl施加读取电压或读取电流，并且，使需要读取数据的结构单元101所属的存储块10(n)中的所有电压控制线102接地，以及通过所有电压控制线102接收对应连接的存储单元104的反馈信息，该反馈信息用于指示对应连接的存储单元104中存储的数据。
其中，通过第一选组线bl和第二选组线sl向待读取数据的存储单元104所属的结构单元101施加读取电压时，存储单元104的反馈信息可以是存储单元104的电流、电容量等信息，在读取电压相同的情况下，存储单元104处于不同阻态时，反馈的电流或电容量不同；当通过第一选组线bl和第二选组线sl向待读取数据的存储单元104所属的结构单元101施加读取电流时，存储单元104的反馈信息可以是存储单元104的电压、电容量等信息，在施加的读取电流相同的情况下，存储单元104处于不同阻态时，反馈的电压或电容量不同。
此外，存储块10(n)中还可以包括分别与多个电压控制线102一一对应连接的多个放大器SA，多个放大器中的每个放大器用于读取对应连接的电压控制线102所接收的反馈信息。
其中，每个放大器及其外围电路等共同组成读出回路，用于输出放大器所连接的电压控制线102对应的存储单元104的反馈信息，从而读取存储单元104中的数据。
具体地，每个放大器可以通过将存储单元104的反馈信息(例如电压、电流、电容量、充放电时间)与参考值做比较，来判断该存储单元104处于高阻态还是低阻态，进而确定该存储单元104中存储的数据。
实际应用中，在向磁性随机存储器写入数据时，上述在第一选组线bl、第二选组线sl和各电压控制线102上施加电压或通入电流的过程可以由磁性随机存储器中配置的电平控制电路进行控制，该电平控制电路用于为第一选组线bl、第二选组线sl和各电压控制线102提供所需的电压或电流。同样地，在从磁性随机存储器读取数据时，在各电压控制线102上施加电压或通入电流的过程也可以由该电平控制电路控制，该电平控制电路用于为各电压控制线102提供所需的电压或电流。
磁性随机存储器中还可以包括行地址解码电路和列地址解码电路，用于在写入或读取数据时通过字线WL和位线选择对应的存储单元104，上述电平控制电路可以根据行地址解码电路和列地址解码电路的选择来判断需要在第一选组线bl、第二选组线sl和各电压控制线102上施加的电压或电流，实现对行地址解码电路和列地址解码电路选择的某一个或某几个存储单元104进行读写操作。
其中，电平控制电路、行地址解码电路和列地址解码电路可以统称为控制电路。
在该实施例中，由于每个存储单元104包括一个MTJ和一个单向导通选择器D，因此，当相邻两个存储单元104之间存在电压差时，总有一个存储单元104中的单向导通选择器D是处于反向截止状态，因此可以有效限制不同存储单元104之间的sneak paths。从而可以较好降低磁性随机存储器的写入漏电功耗。
在该实施例中，当磁性随机存储器中包括多个存储块10(n)时，不同存储块10(n)对应的电压控制线可以是不同的，也可以是相同，在此不作限定。
为了进一步降低磁性随机存储器的写入漏电功耗，当磁性随机存储器中包括多个存储块10(n)时，可以通过减小一次写操作过程中同时工作的存储块的数量，来减少不同存储块之间的sneak paths，从而减小写操作时整个磁性随机存储器的漏电功耗。为了减小一次写操作过程中同时工作的存储块的数量，可以单独控制每个存储块中的电压控制线，即不同存储块中的电压控制线是相互独立的。示例性的，在本申请中，针对每个存储块10(n)，如图11所示，每一存储块10(n)还包括：分别与多个电压控制线102一一对应连接的多个第一位线BLn(图11中以n等于0～8为例进行示意)，多个第一位线BLn中每一个位线BLn通过金属导线与对应的电压控制线102连接。这样写操作时不同存储块10(n)不会同时运行，从而可以降低整个磁性随机存储器的总漏电功耗。
继续参见图11，在存储块10(n)中，与各电压控制线102一一对应的放大器SA通过第一位线BLn与电压控制线102连接，即第一位线BLn的一端与电压控制线102连接，第一位线BLn的另一端与放大器SA连接。
进一步地，在该实施例中，如图11所示，可以将第一层和第二层的6根电压控制线102通过金属导线从存储块10(n)的右端引出并连接到外围电路所在的平面，分别由6根第一位线BL0～BL5控制；第三层的3根电压控制线102通过金属导线从存储块10(n)的左端引出并连接到外围电路所在的平面，分别由3根第一位线BL6～BL8控制。在具体实施时，第一位线BL0～BL8可以设置在存储块的四周，不限于图11中的左端和右端，实现在一个存储块10(n)的外围电路平面内容纳该存储块10(n)所有的第一位线BL0～BL8，解决了3D MRAM方案中对不同存储平面的寻址问题。字线WL和第一位线BLn分别连接行列地址解码电路。写操作时，在需要写入数据的存储单元104所在结构单元101连接的字线WL上施加栅极偏置电压，字线WL控制的第一晶体管T1和第二晶体管T2处于导通状态，在其他不需要写入数据的结构单元101连接的字线WL上施加另一偏置电压，使得相连的第一晶体管T1和第二晶体管T2处于关断状态。在需要写入数据的存储单元104所在的结构单元101的第一选组线sl和第二选组线bl之间施加写电压，则只有需要写入数据的存储单元104所在的结构单元101的电极线103上有写电流流过，即唯一选中了需要写入数据的存储单元104所属的结构单元101。同时，在需要写入数据的存储单元104连接的电压控制线102所连接的第一位线BLn上施加第一偏置电压，在选中的结构单元101中其他不需要写入数据的存储单元104连接的电压控制线102所连接的第一位线BLn上都施加第二偏置电压。在SOT和VCMA效应的共同作用下，可以实现对需要写入数据的存储单元104的选择性写入。改变第一选组线sl和第二选组线bl之间的电压极性，则可以在电极线103中产生相反方向的电流，从而写入不同信息。读操作时，一次读取选中结构单元101内所有的存储单元104中的反馈信息，即在需要读取数据的结构单元101连接的字线WL上施加栅极偏置电压，字线WL控制的第一晶体管T1和第二晶体管T2处于导通状态，在其他不需要读取数据的结构单元101连接的字线WL上施加另一偏置电压，使得相连的第一晶 体管T1和第二晶体管T2处于关断状态。将需要读取数据的结构单元101的第一选组线sl和第二选组线bl都接读取电压或读取电流，同时，将磁性随机存储器中所有第一位线BLn接地，则只有需要读取数据的结构单元101的存储单元104上有读电流流过，实现一次读取选中结构单元101中所有存储单元104的反馈信息。
综上，采用本申请实施例提供的磁性随机存储器，由于存储阵列是3D的，该方案相比现有技术中的2D阵列，可以在保证存储单元的热稳定的前提下，通过垂直方向存储单元的叠加增加面存储密度，进而提高磁性随机存储器的存储密度。此外，在该实施例中，由于每个存储单元包括一个MTJ和一个单向导通选择器，因此，在任意两个存储单元之间有电压差形成漏电通道时，总有一个存储单元中的单向导通选择器是处于反向截止状态，因此可以有效限制不同存储单元之间的sneak paths，从而降低磁性随机存储器的写入漏电功耗。
另外，当不同的存储块对应的电压控制线和第一位线均不同时，写操作时不同存储块不会同时运行，从而可以降低写操作时并行运行的存储块的数量，减少存储块之间的sneak paths，进而可以进一步降低磁性随机存储器的写入漏电功耗。
需要说明的是，实际应用中，本申请实施例提供的磁性随机存储器中包括的存储块的数量、每个存储块中包括的结构单元的数量、每个结构单元包括的存储结构的层数以及每层电极线上包括的存储单元的个数均不做具体限定。由于电压控制线与存储单元是一一对应的，因而在图3、图8至图11的示例中，每层存储结构中与存储单元连接的电压控制线的数量也为三个，实际应用中，与存储单元连接的电压控制线的数量随存储单元的数量而改变。
基于同一技术构思，本申请实施例还提供一种电子设备。参见图12，该电子设备包括处理器1001以及与处理器1001耦合的磁性随机存储器1002，磁性随机存储器1002可以是图1所示的磁性随机存储器。具体地，处理器1001可以调用磁性随机存储器1002中存储的软件程序，以执行相应的方法，实现电子设备的相应功能。
显然，本领域的技术人员可以对本申请实施例进行各种改动和变型而不脱离本申请实施例的范围。这样，倘若本申请实施例的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (15)

  1. 一种磁性随机存储器，其特征在于，包括N个存储块，N为大于0的整数；
    每一所述存储块包括多个结构单元以及多个电压控制线；
    所述多个结构单元中的每个所述结构单元包括依次堆叠的多层存储结构，所述多层存储结构中的每层存储结构包括一个电极线以及设置于所述电极线上的多个存储单元；
    所述每个存储单元的一端与所述电极线连接，另一端与所述多个电压控制线中的一个电压控制线连接；
    所述多个存储单元中的每个存储单元包括串联连接的磁性隧道结和单向导通选择器，所述单向导通选择器的一端与所述磁性隧道结的一端连接，所述单向导通选择器的另一端与所述电压控制线连接，所述磁性隧道结的另一端与所述电极线连接。
  2. 如权利要求1所述的磁性随机存储器，其特征在于，所述每个磁性隧道结包括依次堆叠的自由层、势垒层和参考层，所述自由层与所述电极线连接，所述参考层通过所述单向导通选择器与所述电压控制线连接。
  3. 如权利要求2所述的磁性随机存储器，其特征在于，所述单向导通选择器的正极与所述磁性隧道结连接，所述单向导通选择器的负极与所述电压控制线连接。
  4. 如权利要求2所述的磁性随机存储器，其特征在于，所述单向导通选择器的正极与所述电压控制线连接，所述单向导通选择器的负极与所述磁性隧道结连接。
  5. 如权利要求1～4任一项所述的磁性随机存储器，其特征在于，所述单向导通选择器为肖特基二极管或者PN结二极管。
  6. 如权利要求1～5任一项所述的磁性随机存储器，其特征在于，所述多个电压控制线平行；所述多个结构单元所在的平面平行，且所述多个结构单元中每个结构单元所在的平面与所述多个电压控制线垂直。
  7. 如权利要求6所述的磁性随机存储器，其特征在于，每一所述存储块还包括：第一选组线和第二选组线；所述第一选组线、所述第二选组线以及所述多个电压控制线之间相互平行；
    所述多个结构单元中的每个所述结构单元中的所有电极线分别通过金属导线并联连接；
    所述每个结构单元还包括字线、第一晶体管和第二晶体管，所述第一晶体管和所述第二晶体管的栅极分别与所述字线连接，所述第一晶体管的源极与所述第一选组线连接，所述第二晶体管的漏极与所述第二选组线连接，所述第一晶体管的漏极通过所述金属导线与所述电极线的第一端连接，所述第二晶体管的源极通过所述金属导线与所述电极线的第二 端连接。
  8. 如权利要求1～7任一项所述的磁性随机存储器，其特征在于，每一所述存储块还包括：分别与所述多个电压控制线一一对应连接的多个第一位线，所述多个第一位线中每一个位线通过金属导线与对应的所述电压控制线连接。
  9. 如权利要求8所述的磁性随机存储器，其特征在于，每一所述存储块还包括：分别与所述多个第一位线一一对应连接的多个放大器，所述多个放大器中的每个放大器用于读取对应连接的第一位线所接收的反馈信息，所述反馈信息用于指示对应连接的所述存储单元中存储的数据。
  10. 一种磁性随机存储器，其特征在于，包括N个存储块，N为大于1的整数；
    每一所述存储块包括多个结构单元、多个电压控制线以及分别与所述多个电压控制线一一对应连接的多个第一位线；
    其中，所述多个结构单元中的每个所述结构单元包括依次堆叠的多层存储结构，所述多层存储结构中的每层存储结构包括一个电极线以及设置于所述电极线上的多个存储单元，所述多个存储单元中的每个存储单元包括磁性隧道结，所述每个存储单元的一端与所述电极线连接，另一端与所述多个电压控制线中的一个电压控制线连接；
    所述多个第一位线中每一个位线通过金属导线与对应的所述电压控制线连接。
  11. 如权利要求10所述的磁性随机存储器，其特征在于，所述每个磁性隧道结包括依次堆叠的自由层、势垒层和参考层，所述自由层与所述电极线连接，所述参考层与所述电压控制线连接。
  12. 如权利要求11所述的磁性随机存储器，其特征在于，所述多个电压控制线平行；所述多个结构单元所在的平面平行，且所述多个结构单元中每个结构单元所在的平面与所述多个电压控制线垂直。
  13. 如权利要求12所述的磁性随机存储器，其特征在于，每一所述存储块还包括：第一选组线和第二选组线；所述第一选组线、所述第二选组线以及所述多个电压控制线之间相互平行；
    所述多个结构单元中的每个所述结构单元中的所有电极线分别通过金属导线并联连接；
    所述每个结构单元还包括字线、第一晶体管和第二晶体管，所述第一晶体管和所述第二晶体管的栅极分别与所述字线连接，所述第一晶体管的源极与所述第一选组线连接，所述第二晶体管的漏极与所述第二选组线连接，所述第一晶体管的漏极通过所述金属导线与所述电极线的第一端连接，所述第二晶体管的源极通过所述金属导线与所述电极线的第二端连接。
  14. 如权利要求10～13任一项所述的磁性随机存储器，其特征在于，每一所述存储块 还包括：分别与所述多个第一位线一一对应连接的多个放大器，所述多个放大器中的每个放大器用于读取对应连接的第一位线所接收的反馈信息，所述反馈信息用于指示对应连接的所述存储单元中存储的数据。
  15. 一种电子设备，其特征在于，包括处理器，以及与所述处理器耦合的、如权利要求1～14任一项所述的磁性随机存储器。
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